From b4403426997ad0bca768f88a5eb89d751410980a Mon Sep 17 00:00:00 2001 From: Thomas Pietrzak Date: Mon, 3 Dec 2018 15:42:33 +0100 Subject: [PATCH] simulation + fixes --- fpga/.gitignore | 12 + fpga/Cmod-A7-Master.xdc | 16 +- fpga/forcefader.srcs/sources_1/ip/adc/adc.xci | 366 ++++++++++++++++++ .../sources_1/new/forceconverter.v | 25 ++ fpga/forcefader.srcs/sources_1/new/spring.v | 9 + fpga/forcefader.v | 110 +++--- fpga/forcefader.xpr | 214 ++++++++++ fpga/forcefader_ts.wcfg | 116 ++++++ 8 files changed, 802 insertions(+), 66 deletions(-) create mode 100644 fpga/.gitignore create mode 100644 fpga/forcefader.srcs/sources_1/ip/adc/adc.xci create mode 100644 fpga/forcefader.srcs/sources_1/new/forceconverter.v create mode 100644 fpga/forcefader.srcs/sources_1/new/spring.v create mode 100644 fpga/forcefader.xpr create mode 100644 fpga/forcefader_ts.wcfg diff --git a/fpga/.gitignore b/fpga/.gitignore new file mode 100644 index 0000000..cda6586 --- /dev/null +++ b/fpga/.gitignore @@ -0,0 +1,12 @@ +forcefader.cache +forcefader.hw +forcefader.ip_user_files +forcefader.runs +*.dcp +*.veo +*.vho +Cmod-A7-Master.xdc +*.xml +forcefader.srcs/sources_1/ip/*/* +!forcefader.srcs/sources_1/ip/*/*.xci + diff --git a/fpga/Cmod-A7-Master.xdc b/fpga/Cmod-A7-Master.xdc index 1948b0f..f581a25 100644 --- a/fpga/Cmod-A7-Master.xdc +++ b/fpga/Cmod-A7-Master.xdc @@ -8,8 +8,8 @@ set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}]; ## LEDs -set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1] -set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2] +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2] ## RGB LED #set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b @@ -21,10 +21,10 @@ set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1] ## Pmod Header JA -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1] -#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2] -#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3] -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4] +set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { dir }]; #IO_L5N_T0_D07_14 Sch=ja[1] +set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { en }]; #IO_L4N_T0_D05_14 Sch=ja[2] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[3] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L8P_T1_D11_14 Sch=ja[4] #set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7] #set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8] #set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9] @@ -32,8 +32,8 @@ set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] ## Analog XADC Pins ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12 -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15] +set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15] +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15] #set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16] #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16] diff --git a/fpga/forcefader.srcs/sources_1/ip/adc/adc.xci b/fpga/forcefader.srcs/sources_1/ip/adc/adc.xci new file mode 100644 index 0000000..e4d5b9c --- /dev/null +++ b/fpga/forcefader.srcs/sources_1/ip/adc/adc.xci @@ -0,0 +1,366 @@ + + + xilinx.com + xci + unknown + 1.0 + + + adc + + + + + + 100000000 + 0.000 + 1 + LEVEL_HIGH + + 100000000 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0.000 + + + 100000000 + 0.000 + + 100000000 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 46573 + 22500 + 21845 + 20753 + 39321 + 37355 + 27306 + 25122 + 41287 + 51763 + 43322 + 21190 + 38229 + 44622 + 22937 + 20753 + 20 + 12719 + 512 + 12 + 0 + VP_VN + 7 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 230769.23076923078 + 256 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + design + ./ + Default + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + adc + 4 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 231 + true + false + 32 + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + None + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + false + adc + 32 + 12 + false + true + true + true + true + false + true + true + true + true + false + true + true + true + false + false + false + false + false + false + false + false + VP_VN + 7 + false + ENABLE_DRP + 1 + false + false + false + true + false + Off + design + ./ + Default + false + true + VAUXP4_VAUXN4 + single_channel + 1.0 + 70.0 + 125.0 + 60.0 + 85.0 + Continuous + false + 0.95 + 1.05 + false + 1.75 + 1.89 + 1.15 + 1.25 + 1_2 + false + 0.97 + 1.03 + 1.71 + 1.8 + 0.95 + 1.00 + CONSTANT + single_channel + artix7 + digilentinc.com:cmod_a7-35t:part0:1.1 + xc7a35t + cpg236 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2018.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/forcefader.srcs/sources_1/new/forceconverter.v b/fpga/forcefader.srcs/sources_1/new/forceconverter.v new file mode 100644 index 0000000..4a32a65 --- /dev/null +++ b/fpga/forcefader.srcs/sources_1/new/forceconverter.v @@ -0,0 +1,25 @@ +module forceconverter( + input sysclk, + input signed [15:0] input_forcevalue, + output output_direction, + output reg output_pwm +); + + wire [15:0]absforce; + assign absforce = input_forcevalue < 0 ? - input_forcevalue : input_forcevalue; + + assign output_direction = input_forcevalue[15]; + + reg [9:0] slowclkcounter; + always @(posedge sysclk) slowclkcounter <= slowclkcounter + 1; + + wire slowclk; //1.9kHz + assign slowclk = slowclkcounter[9]; + + reg [15:0] forcecnt; + always @(posedge slowclk) begin + forcecnt <= forcecnt + 1; + if ((forcecnt == 0) ^ (forcecnt == absforce)) output_pwm <= ~output_pwm; + end + +endmodule diff --git a/fpga/forcefader.srcs/sources_1/new/spring.v b/fpga/forcefader.srcs/sources_1/new/spring.v new file mode 100644 index 0000000..21e54bc --- /dev/null +++ b/fpga/forcefader.srcs/sources_1/new/spring.v @@ -0,0 +1,9 @@ +module spring ( + input [11:0] position, + input [11:0] endposition, + input [7:0] stiffness, + output signed [15:0] outputforce + ); + + assign outputforce = stiffness * (endposition - position); +endmodule diff --git a/fpga/forcefader.v b/fpga/forcefader.v index ef55da9..0f602ff 100644 --- a/fpga/forcefader.v +++ b/fpga/forcefader.v @@ -1,65 +1,59 @@ -module spring ( - position, - endposition, - stiffness, - force - ); -input [11:0] position; -input [11:0] endposition; -input [7:0] stiffness; -output signed [16:0] force; - -assign force = stiffness * (endposition - position); - -endmodule - - module forcefader ( - clk, //12MHZ - input_pos, - input_touch, - output_force, - output_direction, - scl, - miso, - mosi, - cs + input sysclk, //12MHZ + input input_touch, + output en, + output dir, + input vp_in, + input vn_in, + input xa_p, + input xa_n/*, + input scl, + output miso, + input mosi, + input cs*/ ); -input clk; -input [11:0] input_pos; -input input_touch; -output reg output_force; -output output_direction; -input scl; -output miso; -input mosi; -input cs; - -reg [10:0] slowclkcounter; -always @(posedge clk) slowclkcounter <= slowclkcounter + 1; -reg signed [16:0] force; - -wire [15:0]absforce; -assign absforce = force < 0 ? - force : force; - -assign output_direction = force[16]; - -reg [15:0] forcecnt; - -wire slowclk; //5.8kHz -assign slowclk = slowclkcounter[10]; - -always @(posedge slowclk) begin - forcecnt <= forcecnt + 1; - if ((forcecnt == 0) ^ (forcecnt == absforce)) output_force <= ~output_force; -end + //get position from ADC + wire enable; + reg [6:0] address_in = 7'h14; + wire ready; + wire [11:0] input_pos; + + adc adc_instance ( + .daddr_in(address_in), + .dclk_in(sysclk), + .den_in(enable), + .di_in(0), + .dwe_in(0), + .vauxp4(xa_p), + .vauxn4(xa_n), + .busy_out(), + .channel_out(), + .do_out(input_pos), + .drdy_out(ready), + .eoc_out(enable), + .eos_out(), + .alarm_out(), + .vp_in(vp_in), + .vn_in(vn_in) + ); + + wire signed [15:0] outputforce; + + //compute spring force + spring spring_instance( + .position(input_pos), + .endposition(12'b000000000010), + .stiffness(8'b00000011), + .outputforce(outputforce) + ); -spring spring_instance( - .position(input_pos), - .endposition({1'b0, 10'b1}), - .stiffness(8'b00010000), - .force(force) + //converts force to pwm + direction + forceconverter forceconverter_instance( + .sysclk(sysclk), + .input_forcevalue(outputforce), + .output_direction(dir), + .output_pwm(en) ); endmodule diff --git a/fpga/forcefader.xpr b/fpga/forcefader.xpr new file mode 100644 index 0000000..ce64695 --- /dev/null +++ b/fpga/forcefader.xpr @@ -0,0 +1,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/forcefader_ts.wcfg b/fpga/forcefader_ts.wcfg new file mode 100644 index 0000000..f619122 --- /dev/null +++ b/fpga/forcefader_ts.wcfg @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + sysclk + sysclk + + + input_touch + input_touch + + + en + en + + + dir + dir + + + vp_in + vp_in + + + vn_in + vn_in + + + xa_p + xa_p + + + xa_n + xa_n + + + enable + enable + + + address_in[6:0] + address_in[6:0] + + + ready + ready + + + Force + label + + input_pos[11:0] + input_pos[11:0] + + + endposition[11:0] + endposition[11:0] + + + stiffness[7:0] + stiffness[7:0] + + + output_direction + output_direction + + + absforce[15:0] + absforce[15:0] + + + outputforce[15:0] + outputforce[15:0] + + + + PWM + label + + + slowclk + slowclk + + + output_pwm + output_pwm + + + forcecnt[15:0] + forcecnt[15:0] + + + slowclkcounter[9:0] + slowclkcounter[9:0] + + + -- 2.30.2