From 3ed1dd23af2743b51a462a76c6118b77c694a80a Mon Sep 17 00:00:00 2001
From: Thomas Pietrzak <thomas.pietrzak@gmail.com>
Date: Mon, 5 Nov 2018 15:37:53 +0100
Subject: [PATCH] test FPGA

---
 fpga/forcefader.v | 65 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 fpga/forcefader.v

diff --git a/fpga/forcefader.v b/fpga/forcefader.v
new file mode 100644
index 0000000..ef55da9
--- /dev/null
+++ b/fpga/forcefader.v
@@ -0,0 +1,65 @@
+module spring (
+  position,
+  endposition,
+  stiffness,
+  force
+  );
+input [11:0] position;
+input [11:0] endposition;
+input [7:0] stiffness;
+output signed [16:0] force;
+
+assign force = stiffness * (endposition - position);
+
+endmodule
+
+
+module forcefader (
+  clk, //12MHZ
+  input_pos,
+  input_touch,
+  output_force,
+  output_direction,
+  scl,
+  miso,
+  mosi,
+  cs
+);
+input clk;
+input [11:0] input_pos;
+input input_touch;
+output reg output_force;
+output output_direction;
+input scl;
+output miso;
+input mosi;
+input cs;
+
+reg [10:0] slowclkcounter;
+always @(posedge clk) slowclkcounter <= slowclkcounter + 1;
+
+reg signed [16:0] force;
+
+wire [15:0]absforce;
+assign absforce = force < 0 ? - force : force;
+
+assign output_direction = force[16];
+
+reg [15:0] forcecnt;
+
+wire slowclk; //5.8kHz
+assign slowclk = slowclkcounter[10];
+
+always @(posedge slowclk) begin
+  forcecnt <= forcecnt + 1;
+  if ((forcecnt == 0) ^ (forcecnt == absforce)) output_force <= ~output_force;
+end
+
+spring spring_instance(
+  .position(input_pos),
+  .endposition({1'b0, 10'b1}),
+  .stiffness(8'b00010000),
+  .force(force)
+  );
+
+endmodule
-- 
2.30.2