From: Nicolas 'Pixel' Noble <nicolas@nobis-crew.org>
Date: Sun, 14 Oct 2018 06:57:18 +0000 (-0700)
Subject: Adding SPI test bench.
X-Git-Url: https://git.thomaspietrzak.com/?a=commitdiff_plain;h=681554325d5a2162c47acdaefcebaddce372edb4;p=testlcd.git

Adding SPI test bench.
---

diff --git a/spi_tb.v b/spi_tb.v
new file mode 100644
index 0000000..4fdd31e
--- /dev/null
+++ b/spi_tb.v
@@ -0,0 +1,62 @@
+`timescale 1us / 10ns
+
+module spi_tb;
+
+// Inputs
+reg clk;
+reg miso;
+reg [7:0] din;
+reg r;
+reg s;
+
+// Outputs
+wire sclk;
+wire mosi;
+wire ssel;
+wire [7:0] dout;
+wire done;
+
+// Instantiate the Unit Under Test (UUT)
+master_spi #(
+  .CPOL(0),
+  .CPHA(0)
+)
+uut (
+  .clk(clk),
+  .sclk(sclk),
+  .mosi(mosi),
+  .miso(miso),
+  .ssel(ssel),
+  .din(din),
+  .dout(dout),
+  .done(done),
+  .r(r),
+  .s(s)
+);
+
+always
+  #10 clk = ~clk;
+
+initial begin
+  // Initialize Inputs
+  clk = 0;
+  miso = 0;
+  din = 0;
+  r = 0;
+  s = 0;
+
+  // Wait 100 ns for global reset to finish
+  #100;
+
+  // Add stimulus here
+  din = 8'haa;
+  s = 1'b1;
+  #20;
+  s = 1'b0;
+end
+
+initial begin
+  $monitor($time, " clk=%b, sclk=%b, mosi=%b, miso=%b, ssel=%b, din=%h, dout=%h, done=%b, r=%b, s=%b", clk, sclk, mosi, miso, ssel, din, dout, done, r, s);
+end
+
+endmodule