From: Thomas Pietrzak Date: Tue, 4 Dec 2018 13:52:09 +0000 (+0100) Subject: fix clocks X-Git-Url: https://git.thomaspietrzak.com/?a=commitdiff_plain;h=3b8a6258afc383aeb9b73b2ee45b26005645216e;p=forcefader.git fix clocks --- diff --git a/fpga/forcefader.srcs/sources_1/new/forceconverter.v b/fpga/forcefader.srcs/sources_1/new/forceconverter.v index 4a32a65..bd68670 100644 --- a/fpga/forcefader.srcs/sources_1/new/forceconverter.v +++ b/fpga/forcefader.srcs/sources_1/new/forceconverter.v @@ -1,25 +1,36 @@ module forceconverter( input sysclk, - input signed [15:0] input_forcevalue, + input signed [16:0] input_forcevalue, output output_direction, - output reg output_pwm + output reg output_pwm = 0 ); - wire [15:0]absforce; + wire [16:0]absforce; assign absforce = input_forcevalue < 0 ? - input_forcevalue : input_forcevalue; - assign output_direction = input_forcevalue[15]; + assign output_direction = input_forcevalue[16]; - reg [9:0] slowclkcounter; - always @(posedge sysclk) slowclkcounter <= slowclkcounter + 1; - + // 2.94KHz + reg [11:0] slowclkcounter = 0; + reg [11:0] currentamplitude = 0; + always @(posedge sysclk) begin + slowclkcounter <= slowclkcounter + 1; + if (slowclkcounter == 0) begin + output_pwm <= ~output_pwm; + currentamplitude <= absforce[15:4]; + end + else if (slowclkcounter == currentamplitude) begin + output_pwm <= ~output_pwm; + end + end +/* wire slowclk; //1.9kHz assign slowclk = slowclkcounter[9]; - reg [15:0] forcecnt; + reg [15:0] forcecnt = 0; always @(posedge slowclk) begin forcecnt <= forcecnt + 1; if ((forcecnt == 0) ^ (forcecnt == absforce)) output_pwm <= ~output_pwm; end - +*/ endmodule diff --git a/fpga/forcefader.srcs/sources_1/new/spring.v b/fpga/forcefader.srcs/sources_1/new/spring.v index 21e54bc..6627c65 100644 --- a/fpga/forcefader.srcs/sources_1/new/spring.v +++ b/fpga/forcefader.srcs/sources_1/new/spring.v @@ -2,7 +2,7 @@ module spring ( input [11:0] position, input [11:0] endposition, input [7:0] stiffness, - output signed [15:0] outputforce + output signed [16:0] outputforce ); assign outputforce = stiffness * (endposition - position); diff --git a/fpga/forcefader.v b/fpga/forcefader.v index 0f602ff..1753d02 100644 --- a/fpga/forcefader.v +++ b/fpga/forcefader.v @@ -38,7 +38,7 @@ module forcefader ( .vn_in(vn_in) ); - wire signed [15:0] outputforce; + wire signed [16:0] outputforce; //compute spring force spring spring_instance( diff --git a/fpga/forcefader.xpr b/fpga/forcefader.xpr index ce64695..d86b5d2 100644 --- a/fpga/forcefader.xpr +++ b/fpga/forcefader.xpr @@ -32,7 +32,7 @@