SPI working.

diff --git a/clocks.v b/clocks.v
index 1db097113c5f1d26e8172ec11aeeabf2dbd38c91..6d8a41e35a45ba4b3bea10beab61a7a807ded739 100644 (file)
--- a/clocks.v
+++ b/clocks.v
@@ -1,5 +1,6 @@
 module clocks(
   clkpin, // 50MHz
+  clk50,
   rst,
   locked,
   clk,    // 300MHz
@@ -11,6 +12,7 @@ input clkpin;
 input rst;
 output locked;
 output clk;
+output clk50;
 output spiclk;
 output tftclk;
 
@@ -121,4 +123,6 @@ FD U2_FD3_INST(.C(U2_CLKIN_IN), .D(U2_FD2_Q_OUT), .Q(U2_FD3_Q_OUT));
 OR2 U2_OR2_INST(.I0(U2_LOCKED_INV_RST), .I1(U2_OR3_O_OUT), .O(U2_RST_IN));
 OR3 U2_OR3_INST(.I0(U2_FD3_Q_OUT), .I1(U2_FD2_Q_OUT), .I2(U2_FD1_Q_OUT), .O(U2_OR3_O_OUT));
 
+assign clk50 = U1_CLKIN_IBUFG;
+
 endmodule

diff --git a/spi.v b/spi.v
index 5c8111d39ad1cfc0cbe419e865be04cf57c9da02..1027efdd42b9219a795c473f3e92ef49c9a96c3c 100644 (file)
--- a/spi.v
+++ b/spi.v
@@ -10,8 +10,9 @@ module master_spi
   ssel,
   din,
   dout,
-  ready,
-  enable
+  done,
+  r,
+  s
 );
 
 function integer log2;
@@ -28,10 +29,9 @@ output reg mosi = 0;
 output reg ssel = 1;
 input [WIDTH-1:0] din;
 output [WIDTH-1:0] dout;
-output reg ready;
-input enable;
-
-initial ready = 1;
+output reg done;
+input r;
+input s;
 
 reg started = 0;
 reg [log2(WIDTH)-1:0] counter;
@@ -40,31 +40,28 @@ reg [WIDTH-1:0] sp_out = 0;
 
 assign dout = sp_out;
 
-always @(posedge clk) if (enable) begin
-  if (!started) begin
-    sp_in <= din;
-    sp_out <= 0;
-    started <= 1;
+always @(posedge clk) begin
+  if (r) begin
+    started <= 0;
+    done <= 0;
     ssel <= 1;
-    ready <= 0;
-    counter <= WIDTH;
-  end else begin
+  end else if (started) begin
     if (counter == 0) begin
-      started <= 0;
       ssel <= 1;
-      ready <= 1;
+      done <= 1;
     end else begin
       ssel <= 0;
-      ready <= 0;
       mosi <= sp_in[WIDTH-1];
       sp_in <= sp_in << 1;
       sp_out <= (sp_out << 1) | miso;
       counter <= counter - 1;
     end
+  end else if (s) begin
+    sp_in <= din;
+    sp_out <= 0;
+    started <= 1;
+    counter <= WIDTH;
   end
-end else begin
-  ssel <= 1;
-  ready <= 1;
 end
 
-endmodule
\ No newline at end of file
+endmodule

diff --git a/top.v b/top.v
index a3bea875ce125902ef78269ff1c8f194cfd9a22d..fce0dbf1ecbf01ed42af75aeba0bbdeb97633e70 100644 (file)
--- a/top.v
+++ b/top.v
@@ -11,10 +11,12 @@ output [3:0] led;
 wire clk;    // 300MHz
 wire spiclk; // 20MHz
 wire tftclk; // 6.667MHz
+wire clk50;
 
 clocks clocks_instance(
   .clkpin(clkpin),
   .rst(1'b0),
+  .clk50(clk50),
   .clk(clk),
   .spiclk(spiclk),
   .tftclk(tftclk)
@@ -24,28 +26,30 @@ reg slowclk; // 1Hz
 reg [31:0] counter = 0;
 wire [23:0] spi_in;
 wire [23:0] spi_out;
-wire spi_ready;
-reg spi_enable = 0;
 wire mosi;
 wire ssel;
+reg spi_r = 0;
+reg spi_s = 0;
+wire spi_done;
 
-assign led[0] = slowclk;
-assign led[1] = ssel;
-assign led[2] = mosi;
-assign led[3] = spi_ready;
+assign led[0] = ~slowclk;
+assign led[1] = ~ssel;
+assign led[2] = ~mosi;
+assign led[3] = ~spi_done;
 
 master_spi #(
   .WIDTH(24)
 )
-master_spi_instance (
+master_spi_instance(
   .clk(slowclk),
   .mosi(mosi),
   .miso(1'b0),
   .ssel(ssel),
   .din(spi_in),
   .dout(spi_out),
-  .ready(spi_ready),
-  .enable(spi_enable)
+  .done(spi_done),
+  .r(spi_r),
+  .s(spi_s)
 );
 
 reg [1:0] state = 0;
@@ -105,29 +109,29 @@ end
 assign spi_in = init_sequence[index];
 
 reg [1:0] button_state = 0;
-always @(posedge clk) begin
-  if (button_state == 2'b10) state <= 1;
-  button_state <= {button_state[0], button};
-end
 
 always @(posedge slowclk) begin
   case(state)
-    1: begin state <= 2; index <= 0; end
-    2: if (spi_ready) spi_enable <= 1;
-    3: if (spi_ready) begin
-          spi_enable <= 0;
-          state <= index == 45 ? 0 : 2;
-          index <= index + 1;
+    0: if (button_state == 2'b10) begin state <= 1; index <= 0; end
+    1: begin state <= 2; spi_r <= 1; spi_s <= 0; end
+    2: begin state <= 3; spi_r <= 0; spi_s <= 1; end
+    3: begin
+      spi_s <= 0;
+      if (spi_done) begin
+        state <= index == 45 ? 0 : 1;
+        index <= index + 1;
+      end
     end
   endcase
+  button_state <= { button_state[0], button };
 end
 
-always @(posedge clk) begin
-  if (counter == 150000000) begin
+always @(posedge clk50) begin
+  if (counter == 25000000) begin
     counter <= 0;
-        slowclk <= ~slowclk;
+    slowclk <= ~slowclk;
   end else begin
-    counter <= counter + 1;     
+    counter <= counter + 1;
   end
 end