--- /dev/null
+*.adb
+*.lk
+*.ihx
+*.cdb
+*.asm
+*.lst
+*.map
+*.rst
+*.sym
+*.rel
+*.lib
+*~
--- /dev/null
+include common.mk
+
+TARGET = test.ihx
+TARGET_OBJS = stm8periphlib/stm8s.lib lcd.rel
+#TARGET_OBJS = $(addprefix stm8periphlib/src/, $(addsuffix .rel, $(basename $(TARGET_SRC))))
+#ihx
+
+CFLAGS = -DSTM8S003 -mstm8 --Werror --debug
+LDFLAGS = --debug --out-fmt-ihx -mstm8
+
+all: $(TARGET)
+
+flash: $(TARGET)
+ $(FLASH) -c stlink -p stm8s003 -w $(TARGET)
+
+.PHONY: clean all flash stm8s
+
+stm8periphlib/stm8s.lib: stm8s
+
+stm8s:
+ @echo "Entering stm8s"
+ make -C stm8periphlib
+
+clean:
+ @echo "Cleaning root"
+ $(RM) -f $(TARGET) $(TARGET_LIB) *.adb *.asm *.bi4 *.lst *.mem *.rel *.sym *.lk *.map *.rst *.cdb *.omf
+ make -C stm8periphlib clean
+
+#--out-fmt-ihx
+
+#ifneq ($(TARGET),)
+#TARGET_HEX = $(addsuffix .hex, $(basename $(TARGET)))
+#TARGET_ELF = $(addsuffix .elf, $(basename $(TARGET)))
+#TARGET_BIN = $(addsuffix .bin, $(basename $(TARGET)))
+#TARGET_OBJS += $(addsuffix .rel, $(basename $(TARGET)))
+#endif
+
+#$(TARGET_HEX): $(TARGET_OBJS)
+# echo $(CC) -o $@ $(TARGET_OBJS) $(LDFLAGS)
+# $(CC) $(LDFLAGS) -o $@ $(TARGET_OBJS)
+
+#$(TARGET_ELF): $(TARGET_OBJS)
+# echo $(CC) -o $@ $(TARGET_OBJS) $(LDFLAGS)
+# $(CC) $(LDFLAGS) -o $@ $(TARGET_OBJS)
+
+#$(TARGET_BIN): $(TARGET_ELF)
+# $(OC) $< -O binary $@
+
+include stm8periphlib/config.mk
+include rules.mk
+
+
--- /dev/null
+CC = sdcc
+LD = sdld
+OC = sdobjcopy
+AR=sdar
+FLASH = stm8flash
+RM = rm
+
+CFLAGS = -c -mstm8 -DSTM8S003 --Werror --debug --opt-code-size
+LDFLAGS = -rc --debug --out-fmt-ihx -mstm8
+
+
--- /dev/null
+#include "lcd.h"
+
+
+#include <stm8s_spi.h>
+
+#define PIN_V0 GPIO_PIN_0
+#define PIN_RS GPIO_PIN_1
+#define PIN_RW GPIO_PIN_7
+#define PIN_E GPIO_PIN_0
+
+#define PORT_V0 GPIOB
+#define PORT_RS GPIOB
+#define PORT_RW GPIOB
+#define PORT_E GPIOB
+
+#define CLEAR 0x01
+#define HOME 0x02
+#define ENTRY 0x04
+ #define CURSORRIGHT 0x02
+ #define CURSORLEFT 0x00
+ #define SHIFT 0x01
+#define DISPLAY 0x08
+ #define BACKGROUND 0x04
+ #define CURSOR 0x02
+ #define CURSORBLINK 0x01
+#define CDSHIFT 0x10
+ #define CURLEFT 0x00
+ #define CURRIGHT 0x40
+ #define DISPLEFT 0x80
+ #define DISPRIGHT 0xc0
+#define FUNCTION 0x20
+ #define 8BITS 0x10
+ #define 4BITS 0x00
+ #define 2LINES 0x08
+ #define 1LINE 0x00
+ #define 5X11DOTS 0x04
+ #define 8X8DOTS 0x00
+#define SETCGRAMADDR 0x40
+#define SETDDRAMADDR 0x80
+
+#define BUSY 0x80
+#define NOTBUSY 0x00
+
+void lcd_init()
+{
+ //init GPIO
+ GPIO_Init(GPIOC, GPIO_PIN_5, GPIO_MODE_OUT_OD_LOW_FAST); //SCK
+ GPIO_Init(GPIOC, GPIO_PIN_6, GPIO_MODE_OUT_OD_LOW_FAST); //MOSI
+// GPIO_Init(GPIOC, GPIO_PIN_7, GPIO_MODE_OUT_OD_LOW_FAST); //MISO
+
+ GPIO_Init(PORT_V0, PIN_V0, GPIO_MODE_OUT_OD_LOW_FAST); //VO
+ GPIO_Init(PORT_RS, PIN_RS, GPIO_MODE_OUT_OD_LOW_FAST); //RS
+ GPIO_Init(PORT_RW, PIN_RW, GPIO_MODE_OUT_OD_LOW_FAST); //RW
+ GPIO_Init(PORT_E, PIN_E, GPIO_MODE_OUT_OD_LOW_FAST); //E
+
+ //init SPI
+ void SPI_Init(SPI_FIRSTBIT_MSB,
+ SPI_BAUDRATEPRESCALER_2,
+ SPI_MODE_MASTER, SPI_CLOCKPOLARITY_LOW,
+ SPI_CLOCKPHASE_1EDGE,
+ SPI_DATADIRECTION_2LINES_FULLDUPLEX,
+ SPI_NSS_SOFT, 7);
+}
+
+void delay(uint8_t t)
+{
+ uint32_t i;
+ for (i = 0 ; i < t*1000 ; i++);
+}
+
+void clear_display()
+{
+ uint8_t byte = CLEAR;
+ GPIO_WriteLow(PORT_SD, PIN_SD);
+ GPIO_WriteLow(PORT_RW, PIN_RW);
+ SPI_SendData(byte);
+ delay(2);
+}
+
+void return_home()
+{
+ uint8_t byte = HOME;
+ GPIO_WriteLow(PORT_SD, PIN_SD);
+ GPIO_WriteLow(PORT_RW, PIN_RW);
+ SPI_SendData(byte);
+ delay(2);
+}
+
+void move_to(uint8_t line, uint8_t column)
+{
+ if (line > 1 || column > 0x0f)
+ return
+
+ //move to position
+ uint8_t byte = SETDDRAMADDR + 4 * line + column;
+ GPIO_WriteLow(PORT_SD, PIN_SD);
+ GPIO_WriteLow(PORT_RW, PIN_RW);
+ SPI_SendData(byte);
+}
+
+void draw_char(uint8_t c)
+{
+ //write char
+ GPIO_WriteHigh(PORT_SD, PIN_SD);
+ GPIO_WriteLow(PORT_RW, PIN_RW);
+ SPI_SendData(c);
+}
+
+
+void draw_string(uint8_t *c)
+{
+ uint8_t i = 0;
+ while (*c && ++i < 16)
+ draw_char(++c);
+}
+
+
+
--- /dev/null
+#pragma once
+
+#include <stm8s.h>
+
+void lcd_init();
+void clear_display();
+void return_home();
+void move_to(uint8_t line, uint8_t column);
+void draw_char(uint8_t c);
+void draw_string(uint8_t *c);
+
--- /dev/null
+
+%.ihx: %.rel $(TARGET_OBJS)
+ @echo "Building target"
+ $(CC) $(LDFLAGS) $^
+
+#%.rel: %.c
+# $(CC) $(CFLAGS) -c $<
+#-o $@
+
+%.rel: %.c
+ @echo "Compile $<"
+ $(CC) $(CFLAGS) $(addprefix -I, $(TARGET_INCLUDES)) -c $< -o $@
+
--- /dev/null
+include ../common.mk
+include config.mk
+
+SRC = src/stm8s_gpio.c src/stm8s_spi.c
+TARGET_OBJS = $(addsuffix .rel, $(basename $(SRC)))
+TARGET_LIB = stm8s.lib
+TARGET_INCLUDES += inc
+
+all: $(TARGET_LIB)
+
+.PHONY: clean all
+
+$(TARGET_LIB): $(TARGET_OBJS)
+ $(AR) -rc $@ $<
+
+clean:
+ @echo "Cleaning stm8lib"
+ $(RM) -f $(TARGET) $(TARGET_LIB) src/*.adb src/*.asm src/*.bi4 src/*.lst src/*.mem src/*.rel src/*.sym src/*.lk src/*.map src/*.rst src/*.cdb src/*.omf
+
+include ../rules.mk
+
--- /dev/null
+TARGET_INCLUDES += stm8periphlib/inc
+
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all HW registers definitions and memory mapping.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_H\r
+#define __STM8S_H\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM8S or STM8A device used in your\r
+ application. */\r
+\r
+ /* #define STM8S208 */ /*!< STM8S High density devices with CAN */\r
+ /* #define STM8S207 */ /*!< STM8S High density devices without CAN */\r
+ /* #define STM8S007 */ /*!< STM8S Value Line High density devices */\r
+ /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */\r
+ /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */\r
+ /* #define STM8S105 */ /*!< STM8S Medium density devices */\r
+ /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */\r
+ /* #define STM8AF626x */ /*!< STM8A Medium density devices */\r
+ /* #define STM8S103 */ /*!< STM8S Low density devices */\r
+ /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */\r
+ /* #define STM8S903 */ /*!< STM8S Low density devices */\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor. \r
+\r
+ - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,\r
+ STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory\r
+ density ranges between 32 to 128 Kbytes\r
+ - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,\r
+ STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory \r
+ density ranges between 8 to 32 Kbytes\r
+ - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers\r
+ where the Flash memory density ranges between 32 to 128 Kbytes.\r
+ - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers\r
+ where the Flash memory density ranges between 16 to 32-Kbytes.\r
+ - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers\r
+ where the Flash density is 8 Kbytes. */\r
+\r
+#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \\r
+ !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \\r
+ !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \\r
+ !defined (STM8S003)&& !defined (STM8S005) \r
+ #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* Library configuration section */\r
+/******************************************************************************/\r
+/* Check the used compiler */\r
+#if defined(__CSMC__)\r
+ #define _COSMIC_\r
+#elif defined(__RCST7__)\r
+ #define _RAISONANCE_\r
+#elif defined(__ICCSTM8__)\r
+ #define _IAR_\r
+#else\r
+ #error "Unsupported Compiler!" /* Compiler defines not found */\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/* Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will be\r
+ based on direct access to peripherals registers */\r
+ #define USE_STDPERIPH_DRIVER\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application\r
+\r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */\r
+#if !defined HSE_Value\r
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/\r
+ #else\r
+ #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/\r
+ #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */\r
+#endif /* HSE_Value */\r
+\r
+/**\r
+ * @brief Definition of Device on-chip RC oscillator frequencies\r
+ */\r
+#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */\r
+#define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */\r
+\r
+#ifdef _COSMIC_\r
+ #define FAR @far\r
+ #define NEAR @near\r
+ #define TINY @tiny\r
+ #define EEPROM @eeprom\r
+ #define CONST const\r
+#elif defined (_RAISONANCE_) /* __RCST7__ */\r
+ #define FAR far\r
+ #define NEAR data\r
+ #define TINY page0\r
+ #define EEPROM eeprom\r
+ #define CONST code\r
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ /*!< Used with memory Models for code higher than 64K */\r
+ #define MEMCPY fmemcpy\r
+ #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */\r
+ /*!< Used with memory Models for code less than 64K */\r
+ #define MEMCPY memcpy\r
+ #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */ \r
+#else /*_IAR_*/\r
+ #define FAR __far\r
+ #define NEAR __near\r
+ #define TINY __tiny\r
+ #define EEPROM __eeprom\r
+ #define CONST const\r
+#endif /* __CSMC__ */\r
+\r
+/* For FLASH routines, select whether pointer will be declared as near (2 bytes,\r
+ to handle code smaller than 64KB) or far (3 bytes, to handle code larger \r
+ than 64K) */\r
+\r
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \\r
+ defined (STM8S903) || defined (STM8AF626x)\r
+/*!< Used with memory Models for code smaller than 64K */\r
+ #define PointerAttr NEAR\r
+#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */\r
+/*!< Used with memory Models for code higher than 64K */\r
+ #define PointerAttr FAR\r
+#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */\r
+\r
+/* Uncomment the line below to enable the FLASH functions execution from RAM */\r
+#if !defined (RAM_EXECUTION)\r
+/* #define RAM_EXECUTION (1) */\r
+#endif /* RAM_EXECUTION */\r
+\r
+#ifdef RAM_EXECUTION\r
+ #ifdef _COSMIC_\r
+ #define IN_RAM(a) a\r
+ #elif defined (_RAISONANCE_) /* __RCST7__ */\r
+ #define IN_RAM(a) a inram\r
+ #else /*_IAR_*/\r
+ #define IN_RAM(a) __ramfunc a\r
+ #endif /* _COSMIC_ */\r
+#else \r
+ #define IN_RAM(a) a\r
+#endif /* RAM_EXECUTION */\r
+\r
+/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/\r
+#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */ \r
+#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01) /*!< [23:16] sub1 version */\r
+#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */\r
+#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ \r
+#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM8S_STDPERIPH_VERSION_RC))\r
+\r
+/******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/* Exported types and constants ----------------------------------------------*/\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*!< Signed integer types */\r
+typedef signed char int8_t;\r
+typedef signed short int16_t;\r
+typedef signed long int32_t;\r
+\r
+/*!< Unsigned integer types */\r
+typedef unsigned char uint8_t;\r
+typedef unsigned short uint16_t;\r
+typedef unsigned long uint32_t;\r
+\r
+/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */\r
+\r
+typedef int32_t s32;\r
+typedef int16_t s16;\r
+typedef int8_t s8;\r
+\r
+typedef uint32_t u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t u8;\r
+\r
+\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+#define U8_MAX (255)\r
+#define S8_MAX (127)\r
+#define S8_MIN (-128)\r
+#define U16_MAX (65535u)\r
+#define S16_MAX (32767)\r
+#define S16_MIN (-32768)\r
+#define U32_MAX (4294967295uL)\r
+#define S32_MAX (2147483647)\r
+#define S32_MIN (-2147483648uL)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup MAP_FILE_Exported_Types_and_Constants\r
+ * @{\r
+ */\r
+\r
+/******************************************************************************/\r
+/* IP registers structures */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief General Purpose I/Os (GPIO)\r
+ */\r
+typedef struct GPIO_struct\r
+{\r
+ __IO uint8_t ODR; /*!< Output Data Register */\r
+ __IO uint8_t IDR; /*!< Input Data Register */\r
+ __IO uint8_t DDR; /*!< Data Direction Register */\r
+ __IO uint8_t CR1; /*!< Configuration Register 1 */\r
+ __IO uint8_t CR2; /*!< Configuration Register 2 */\r
+}\r
+GPIO_TypeDef;\r
+\r
+/** @addtogroup GPIO_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+/**\r
+ * @brief Analog to Digital Converter (ADC1)\r
+ */\r
+ typedef struct ADC1_struct\r
+ {\r
+ __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ uint8_t RESERVED[12]; /*!< Reserved byte */\r
+ __IO uint8_t CSR; /*!< ADC1 control status register */\r
+ __IO uint8_t CR1; /*!< ADC1 configuration register 1 */\r
+ __IO uint8_t CR2; /*!< ADC1 configuration register 2 */\r
+ __IO uint8_t CR3; /*!< ADC1 configuration register 3 */\r
+ __IO uint8_t DRH; /*!< ADC1 Data high */\r
+ __IO uint8_t DRL; /*!< ADC1 Data low */\r
+ __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */\r
+ __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */\r
+ __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/\r
+ __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/\r
+ __IO uint8_t LTRH; /*!< ADC1 low threshold register high */\r
+ __IO uint8_t LTRL; /*!< ADC1 low threshold register low */\r
+ __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */\r
+ __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */\r
+ __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */\r
+ __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */\r
+ }\r
+ ADC1_TypeDef;\r
+\r
+/** @addtogroup ADC1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+ #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03)\r
+ #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF)\r
+ #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */\r
+ #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */\r
+ #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */\r
+ #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */\r
+ #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */\r
+\r
+ #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */\r
+ #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */\r
+ #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */\r
+\r
+ #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */\r
+ #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */\r
+ #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */\r
+ #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */\r
+\r
+ #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */\r
+ #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */\r
+\r
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Analog to Digital Converter (ADC2)\r
+ */\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)\r
+ typedef struct ADC2_struct\r
+ {\r
+ __IO uint8_t CSR; /*!< ADC2 control status register */\r
+ __IO uint8_t CR1; /*!< ADC2 configuration register 1 */\r
+ __IO uint8_t CR2; /*!< ADC2 configuration register 2 */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t DRH; /*!< ADC2 Data high */\r
+ __IO uint8_t DRL; /*!< ADC2 Data low */\r
+ __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */\r
+ __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */\r
+ }\r
+ ADC2_TypeDef;\r
+\r
+/** @addtogroup ADC2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+ #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */\r
+ #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */\r
+ #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */\r
+\r
+ #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */\r
+ #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */\r
+ #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */\r
+\r
+ #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */\r
+ #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */\r
+ #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */\r
+\r
+#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Auto Wake Up (AWU) peripheral registers.\r
+ */\r
+typedef struct AWU_struct\r
+{\r
+ __IO uint8_t CSR; /*!< AWU Control status register */\r
+ __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */\r
+ __IO uint8_t TBR; /*!< AWU Time base selection register */\r
+}\r
+AWU_TypeDef;\r
+\r
+/** @addtogroup AWU_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)\r
+#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)\r
+#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup AWU_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */\r
+#define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */\r
+#define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */\r
+\r
+#define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */\r
+\r
+#define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Beeper (BEEP) peripheral registers.\r
+ */\r
+\r
+typedef struct BEEP_struct\r
+{\r
+ __IO uint8_t CSR; /*!< BEEP Control status register */\r
+}\r
+BEEP_TypeDef;\r
+\r
+/** @addtogroup BEEP_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup BEEP_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */\r
+#define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */\r
+#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Clock Controller (CLK)\r
+ */\r
+typedef struct CLK_struct\r
+{\r
+ __IO uint8_t ICKR; /*!< Internal Clocks Control Register */\r
+ __IO uint8_t ECKR; /*!< External Clocks Control Register */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t CMSR; /*!< Clock Master Status Register */\r
+ __IO uint8_t SWR; /*!< Clock Master Switch Register */\r
+ __IO uint8_t SWCR; /*!< Switch Control Register */\r
+ __IO uint8_t CKDIVR; /*!< Clock Divider Register */\r
+ __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */\r
+ __IO uint8_t CSSR; /*!< Clock Security System Register */\r
+ __IO uint8_t CCOR; /*!< Configurable Clock Output Register */\r
+ __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */\r
+ __IO uint8_t SWIMCCR; /*!< SWIM clock control register */\r
+}\r
+CLK_TypeDef;\r
+\r
+/** @addtogroup CLK_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)\r
+#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)\r
+#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)\r
+#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)\r
+#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)\r
+#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)\r
+#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CLK_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+#define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */\r
+#define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */\r
+#define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */\r
+#define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */\r
+#define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */\r
+#define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */\r
+\r
+#define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */\r
+#define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */\r
+\r
+#define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */\r
+\r
+#define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */\r
+\r
+#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */\r
+#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */\r
+#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */\r
+#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/\r
+\r
+#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */\r
+#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */\r
+\r
+#define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */ \r
+#define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */\r
+#define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */\r
+#define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */\r
+#define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */\r
+#define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */\r
+#define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */\r
+#define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */\r
+#define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */\r
+#define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */\r
+#define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */\r
+\r
+#define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */\r
+#define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */\r
+#define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */\r
+\r
+#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */\r
+#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */\r
+#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */\r
+#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */\r
+\r
+#define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */\r
+#define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */\r
+#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */\r
+#define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */\r
+\r
+#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */\r
+\r
+#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer with complementary PWM outputs (TIM1)\r
+ */\r
+\r
+typedef struct TIM1_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t SMCR; /*!< Synchro mode control register */\r
+ __IO uint8_t ETR; /*!< external trigger register */\r
+ __IO uint8_t IER; /*!< interrupt enable register*/\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */\r
+ __IO uint8_t CCMR4; /*!< CC mode register 4 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CCER2; /*!< CC enable register 2 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCRH; /*!< prescaler high */\r
+ __IO uint8_t PSCRL; /*!< prescaler low */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t RCR; /*!< Repetition Counter register */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */\r
+ __IO uint8_t CCR4H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR4L; /*!< capture/compare register 3 low */\r
+ __IO uint8_t BKR; /*!< Break Register */\r
+ __IO uint8_t DTR; /*!< dead-time register */\r
+ __IO uint8_t OISR; /*!< Output idle register */\r
+}\r
+TIM1_TypeDef;\r
+\r
+/** @addtogroup TIM1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */\r
+#define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */\r
+#define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/* CR2*/\r
+#define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */\r
+#define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */\r
+#define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */\r
+#define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */\r
+/* SMCR*/\r
+#define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */\r
+#define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */\r
+#define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */\r
+/*ETR*/\r
+#define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */\r
+#define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */\r
+#define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */\r
+#define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */\r
+/*IER*/\r
+#define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */\r
+#define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */\r
+#define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/\r
+#define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */\r
+#define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */\r
+#define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */\r
+#define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */\r
+#define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */\r
+#define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */\r
+#define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */\r
+#define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+\r
+#define CCMR_TIxDirect_Set ((uint8_t)0x01)\r
+/*CCER1*/\r
+#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */\r
+#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */\r
+#define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */\r
+#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */\r
+#define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */\r
+#define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */\r
+#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */\r
+#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */\r
+#define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTRH*/\r
+#define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+/*CNTRL*/\r
+#define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCH*/\r
+#define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*PSCL*/\r
+#define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */\r
+/*ARR*/\r
+#define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*RCR*/\r
+#define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */\r
+/*CCR1*/\r
+#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+/*CCR4*/\r
+#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */\r
+#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */\r
+/*BKR*/\r
+#define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */\r
+#define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */\r
+#define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */\r
+#define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */\r
+#define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */\r
+#define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */\r
+#define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */\r
+/*DTR*/\r
+#define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */\r
+/*OISR*/\r
+#define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */\r
+#define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */\r
+#define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */\r
+#define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */\r
+#define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */\r
+#define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */\r
+#define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer (TIM2)\r
+ */\r
+\r
+typedef struct TIM2_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+#if defined(STM8S103) || defined(STM8S003)\r
+ uint8_t RESERVED1; /*!< Reserved register */\r
+ uint8_t RESERVED2; /*!< Reserved register */\r
+#endif\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CCER2; /*!< CC enable register 2 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */\r
+}\r
+TIM2_TypeDef;\r
+\r
+/** @addtogroup TIM2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTR*/\r
+#define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer (TIM3)\r
+ */\r
+typedef struct TIM3_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+}\r
+TIM3_TypeDef;\r
+\r
+/** @addtogroup TIM3_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM3_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CNTR*/\r
+#define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 8-bit system timer (TIM4)\r
+ */\r
+\r
+typedef struct TIM4_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+#if defined(STM8S103) || defined(STM8S003)\r
+ uint8_t RESERVED1; /*!< Reserved register */\r
+ uint8_t RESERVED2; /*!< Reserved register */\r
+#endif\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CNTR; /*!< counter register */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARR; /*!< auto-reload register */\r
+}\r
+TIM4_TypeDef;\r
+\r
+/** @addtogroup TIM4_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM4_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*EGR*/\r
+#define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CNTR*/\r
+#define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */\r
+/*ARR*/\r
+#define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer with synchro module (TIM5)\r
+ */\r
+\r
+typedef struct TIM5_struct\r
+{\r
+ __IO uint8_t CR1; /*!<TIM5 Control Register 1 */\r
+ __IO uint8_t CR2; /*!<TIM5 Control Register 2 */\r
+ __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */\r
+ __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */\r
+ __IO uint8_t SR1; /*!<TIM5 Status Register 1 */\r
+ __IO uint8_t SR2; /*!<TIM5 Status Register 2 */\r
+ __IO uint8_t EGR; /*!<TIM5 Event Generation Register */\r
+ __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */\r
+ __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */\r
+ __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */\r
+ __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */\r
+ __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */\r
+ __IO uint8_t CNTRH; /*!<TIM5 Counter High */\r
+ __IO uint8_t CNTRL; /*!<TIM5 Counter Low */\r
+ __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */\r
+ __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */\r
+ __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */\r
+ __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */\r
+ __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */\r
+ __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */\r
+ __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */\r
+ __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */\r
+ __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */\r
+}TIM5_TypeDef;\r
+\r
+/** @addtogroup TIM5_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM5_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/* CR2*/\r
+#define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */\r
+#define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */\r
+/* SMCR*/\r
+#define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */\r
+#define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */\r
+#define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */\r
+/*IER*/\r
+#define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */\r
+#define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTR*/\r
+#define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+/*CCMR*/\r
+#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 8-bit system timer with synchro module(TIM6)\r
+ */\r
+\r
+typedef struct TIM6_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t SMCR; /*!< Synchro mode control register */\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CNTR; /*!< counter register */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARR; /*!< auto-reload register */\r
+}\r
+TIM6_TypeDef;\r
+/** @addtogroup TIM6_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+* @}\r
+*/\r
+\r
+/** @addtogroup TIM6_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */\r
+#define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */\r
+#define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */\r
+#define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */\r
+#define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */\r
+/* CR2*/\r
+#define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */\r
+/* SMCR*/\r
+#define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */\r
+#define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */\r
+#define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */\r
+/* IER*/\r
+#define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */\r
+#define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */\r
+/* SR1*/\r
+#define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */\r
+/* EGR*/\r
+#define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */\r
+/* CNTR*/\r
+#define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */\r
+/* PSCR*/\r
+#define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */\r
+\r
+#define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */\r
+/**\r
+ * @}\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Inter-Integrated Circuit (I2C)\r
+ */\r
+\r
+typedef struct I2C_struct\r
+{\r
+ __IO uint8_t CR1; /*!< I2C control register 1 */\r
+ __IO uint8_t CR2; /*!< I2C control register 2 */\r
+ __IO uint8_t FREQR; /*!< I2C frequency register */\r
+ __IO uint8_t OARL; /*!< I2C own address register LSB */\r
+ __IO uint8_t OARH; /*!< I2C own address register MSB */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ __IO uint8_t DR; /*!< I2C data register */\r
+ __IO uint8_t SR1; /*!< I2C status register 1 */\r
+ __IO uint8_t SR2; /*!< I2C status register 2 */\r
+ __IO uint8_t SR3; /*!< I2C status register 3 */\r
+ __IO uint8_t ITR; /*!< I2C interrupt register */\r
+ __IO uint8_t CCRL; /*!< I2C clock control register low */\r
+ __IO uint8_t CCRH; /*!< I2C clock control register high */\r
+ __IO uint8_t TRISER; /*!< I2C maximum rise time register */\r
+ uint8_t RESERVED2; /*!< Reserved byte */\r
+}\r
+I2C_TypeDef;\r
+\r
+/** @addtogroup I2C_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define I2C_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_OARL_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_OARH_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_DR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR3_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_ITR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */\r
+#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */\r
+\r
+#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */\r
+#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */\r
+#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */\r
+#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */\r
+#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */\r
+\r
+#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */\r
+\r
+#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */\r
+#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */\r
+\r
+#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */\r
+#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */\r
+#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */\r
+\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */\r
+\r
+#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */\r
+\r
+#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */\r
+#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */\r
+#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */\r
+#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */\r
+\r
+#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */\r
+#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */\r
+#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */\r
+#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */\r
+\r
+#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */\r
+#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */\r
+#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */\r
+\r
+#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */\r
+\r
+#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */\r
+#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */\r
+\r
+#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Interrupt Controller (ITC)\r
+ */\r
+\r
+typedef struct ITC_struct\r
+{\r
+ __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */\r
+ __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */\r
+ __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */\r
+ __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */\r
+ __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */\r
+ __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */\r
+ __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */\r
+ __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */\r
+}\r
+ITC_TypeDef;\r
+\r
+/** @addtogroup ITC_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CPU_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief External Interrupt Controller (EXTI)\r
+ */\r
+\r
+typedef struct EXTI_struct\r
+{\r
+ __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */\r
+ __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */\r
+}\r
+EXTI_TypeDef;\r
+\r
+/** @addtogroup EXTI_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup EXTI_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */\r
+\r
+#define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */\r
+#define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief FLASH program and Data memory (FLASH)\r
+ */\r
+\r
+typedef struct FLASH_struct\r
+{\r
+ __IO uint8_t CR1; /*!< Flash control register 1 */\r
+ __IO uint8_t CR2; /*!< Flash control register 2 */\r
+ __IO uint8_t NCR2; /*!< Flash complementary control register 2 */\r
+ __IO uint8_t FPR; /*!< Flash protection register */\r
+ __IO uint8_t NFPR; /*!< Flash complementary protection register */\r
+ __IO uint8_t IAPSR; /*!< Flash in-application programming status register */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ uint8_t RESERVED2; /*!< Reserved byte */\r
+ __IO uint8_t PUKR; /*!< Flash program memory unprotection register */\r
+ uint8_t RESERVED3; /*!< Reserved byte */\r
+ __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */\r
+}\r
+FLASH_TypeDef;\r
+\r
+/** @addtogroup FLASH_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)\r
+#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)\r
+#define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */\r
+#define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */\r
+#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */\r
+#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */\r
+\r
+#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */\r
+#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */\r
+#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */\r
+#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */\r
+#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */\r
+\r
+#define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */\r
+#define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */\r
+#define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */\r
+#define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */\r
+#define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */\r
+\r
+#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */\r
+#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */\r
+#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */\r
+#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */\r
+#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */\r
+\r
+#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */\r
+\r
+#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Option Bytes (OPT)\r
+ */\r
+typedef struct OPT_struct\r
+{\r
+ __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */\r
+ __IO uint8_t OPT1; /*!< Option byte 1: User boot code */\r
+ __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */\r
+ __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */\r
+ __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */\r
+ __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */\r
+ __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */\r
+ __IO uint8_t OPT4; /*!< Option byte 4: Clock option */\r
+ __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */\r
+ __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */\r
+ __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */\r
+ uint8_t RESERVED1; /*!< Reserved Option byte*/\r
+ uint8_t RESERVED2; /*!< Reserved Option byte*/\r
+ __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */\r
+ __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */\r
+}\r
+OPT_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Independent Watchdog (IWDG)\r
+ */\r
+\r
+typedef struct IWDG_struct\r
+{\r
+ __IO uint8_t KR; /*!< Key Register */\r
+ __IO uint8_t PR; /*!< Prescaler Register */\r
+ __IO uint8_t RLR; /*!< Reload Register */\r
+}\r
+IWDG_TypeDef;\r
+\r
+/** @addtogroup IWDG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define IWDG_PR_RESET_VALUE ((uint8_t)0x00)\r
+#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Window Watchdog (WWDG)\r
+ */\r
+\r
+typedef struct WWDG_struct\r
+{\r
+ __IO uint8_t CR; /*!< Control Register */\r
+ __IO uint8_t WR; /*!< Window Register */\r
+}\r
+WWDG_TypeDef;\r
+\r
+/** @addtogroup WWDG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)\r
+#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup WWDG_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */\r
+\r
+#define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */\r
+#define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Reset Controller (RST)\r
+ */\r
+\r
+typedef struct RST_struct\r
+{\r
+ __IO uint8_t SR; /*!< Reset status register */\r
+}\r
+RST_TypeDef;\r
+\r
+/** @addtogroup RST_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */\r
+#define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */\r
+#define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */\r
+#define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */\r
+#define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Serial Peripheral Interface (SPI)\r
+ */\r
+\r
+typedef struct SPI_struct\r
+{\r
+ __IO uint8_t CR1; /*!< SPI control register 1 */\r
+ __IO uint8_t CR2; /*!< SPI control register 2 */\r
+ __IO uint8_t ICR; /*!< SPI interrupt control register */\r
+ __IO uint8_t SR; /*!< SPI status register */\r
+ __IO uint8_t DR; /*!< SPI data I/O register */\r
+ __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */\r
+ __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */\r
+ __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */\r
+}\r
+SPI_TypeDef;\r
+\r
+/** @addtogroup SPI_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */\r
+#define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */\r
+#define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register reset value */\r
+#define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */\r
+#define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */\r
+#define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */\r
+#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */\r
+#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */\r
+#define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */\r
+#define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */\r
+#define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */\r
+#define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */\r
+#define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */\r
+\r
+#define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */\r
+#define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */\r
+#define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */\r
+#define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */\r
+#define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */\r
+#define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */\r
+#define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */\r
+\r
+#define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */\r
+#define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */\r
+#define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */\r
+#define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */\r
+\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */\r
+#define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)\r
+ */\r
+\r
+typedef struct UART1_struct\r
+{\r
+ __IO uint8_t SR; /*!< UART1 status register */\r
+ __IO uint8_t DR; /*!< UART1 data register */\r
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */\r
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< UART1 control register 1 */\r
+ __IO uint8_t CR2; /*!< UART1 control register 2 */\r
+ __IO uint8_t CR3; /*!< UART1 control register 3 */\r
+ __IO uint8_t CR4; /*!< UART1 control register 4 */\r
+ __IO uint8_t CR5; /*!< UART1 control register 5 */\r
+ __IO uint8_t GTR; /*!< UART1 guard time register */\r
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */\r
+}\r
+UART1_TypeDef;\r
+\r
+/** @addtogroup UART1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART1_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR5_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_GTR_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */\r
+\r
+#define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */\r
+#define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */\r
+\r
+#define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */\r
+#define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */\r
+#define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */\r
+#define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */\r
+\r
+#define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+#define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */\r
+#define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */\r
+#define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */\r
+#define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */\r
+\r
+#define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */\r
+\r
+#define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */\r
+#define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */\r
+#define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */\r
+#define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */\r
+#define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)\r
+ */\r
+\r
+typedef struct UART2_struct\r
+{\r
+ __IO uint8_t SR; /*!< UART1 status register */\r
+ __IO uint8_t DR; /*!< UART1 data register */\r
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */\r
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< UART1 control register 1 */\r
+ __IO uint8_t CR2; /*!< UART1 control register 2 */\r
+ __IO uint8_t CR3; /*!< UART1 control register 3 */\r
+ __IO uint8_t CR4; /*!< UART1 control register 4 */\r
+ __IO uint8_t CR5; /*!< UART1 control register 5 */\r
+ __IO uint8_t CR6; /*!< UART1 control register 6 */\r
+ __IO uint8_t GTR; /*!< UART1 guard time register */\r
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */\r
+}\r
+UART2_TypeDef;\r
+\r
+/** @addtogroup UART2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART2_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR5_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR6_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_GTR_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */\r
+\r
+#define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */\r
+#define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */\r
+\r
+#define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */\r
+#define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */\r
+#define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */\r
+#define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */\r
+\r
+#define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+#define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */\r
+#define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */\r
+#define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */\r
+#define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */\r
+\r
+#define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */\r
+\r
+#define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */\r
+#define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */\r
+#define UART2_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */\r
+#define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */\r
+#define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */\r
+\r
+#define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */\r
+#define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */\r
+#define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */\r
+#define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */\r
+#define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */\r
+#define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)\r
+ */\r
+\r
+typedef struct UART3_struct\r
+{\r
+ __IO uint8_t SR; /*!< status register */\r
+ __IO uint8_t DR; /*!< data register */\r
+ __IO uint8_t BRR1; /*!< baud rate register */\r
+ __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t CR3; /*!< control register 3 */\r
+ __IO uint8_t CR4; /*!< control register 4 */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t CR6; /*!< control register 5 */\r
+}\r
+UART3_TypeDef;\r
+\r
+/** @addtogroup UART3_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART3_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR6_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART3_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */\r
+\r
+#define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */\r
+#define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */\r
+\r
+#define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */\r
+#define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */\r
+#define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */\r
+#define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */\r
+\r
+#define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+\r
+#define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */\r
+\r
+#define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */\r
+#define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */\r
+#define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */\r
+#define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */\r
+#define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */\r
+#define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Controller Area Network (CAN)\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint8_t MCR; /*!< CAN master control register */\r
+ __IO uint8_t MSR; /*!< CAN master status register */\r
+ __IO uint8_t TSR; /*!< CAN transmit status register */\r
+ __IO uint8_t TPR; /*!< CAN transmit priority register */\r
+ __IO uint8_t RFR; /*!< CAN receive FIFO register */\r
+ __IO uint8_t IER; /*!< CAN interrupt enable register */\r
+ __IO uint8_t DGR; /*!< CAN diagnosis register */\r
+ __IO uint8_t PSR; /*!< CAN page selection register */\r
+\r
+ union\r
+ {\r
+ struct\r
+ {\r
+ __IO uint8_t MCSR;\r
+ __IO uint8_t MDLCR;\r
+ __IO uint8_t MIDR1;\r
+ __IO uint8_t MIDR2;\r
+ __IO uint8_t MIDR3;\r
+ __IO uint8_t MIDR4;\r
+ __IO uint8_t MDAR1;\r
+ __IO uint8_t MDAR2;\r
+ __IO uint8_t MDAR3;\r
+ __IO uint8_t MDAR4;\r
+ __IO uint8_t MDAR5;\r
+ __IO uint8_t MDAR6;\r
+ __IO uint8_t MDAR7;\r
+ __IO uint8_t MDAR8;\r
+ __IO uint8_t MTSRL;\r
+ __IO uint8_t MTSRH;\r
+ }\r
+ TxMailbox;\r
+\r
+ struct\r
+ {\r
+ __IO uint8_t FR01;\r
+ __IO uint8_t FR02;\r
+ __IO uint8_t FR03;\r
+ __IO uint8_t FR04;\r
+ __IO uint8_t FR05;\r
+ __IO uint8_t FR06;\r
+ __IO uint8_t FR07;\r
+ __IO uint8_t FR08;\r
+\r
+ __IO uint8_t FR09;\r
+ __IO uint8_t FR10;\r
+ __IO uint8_t FR11;\r
+ __IO uint8_t FR12;\r
+ __IO uint8_t FR13;\r
+ __IO uint8_t FR14;\r
+ __IO uint8_t FR15;\r
+ __IO uint8_t FR16;\r
+ }\r
+ Filter;\r
+ \r
+\r
+ struct\r
+ {\r
+ __IO uint8_t F0R1;\r
+ __IO uint8_t F0R2;\r
+ __IO uint8_t F0R3;\r
+ __IO uint8_t F0R4;\r
+ __IO uint8_t F0R5;\r
+ __IO uint8_t F0R6;\r
+ __IO uint8_t F0R7;\r
+ __IO uint8_t F0R8;\r
+\r
+ __IO uint8_t F1R1;\r
+ __IO uint8_t F1R2;\r
+ __IO uint8_t F1R3;\r
+ __IO uint8_t F1R4;\r
+ __IO uint8_t F1R5;\r
+ __IO uint8_t F1R6;\r
+ __IO uint8_t F1R7;\r
+ __IO uint8_t F1R8;\r
+ }\r
+ Filter01;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t F2R1;\r
+ __IO uint8_t F2R2;\r
+ __IO uint8_t F2R3;\r
+ __IO uint8_t F2R4;\r
+ __IO uint8_t F2R5;\r
+ __IO uint8_t F2R6;\r
+ __IO uint8_t F2R7;\r
+ __IO uint8_t F2R8;\r
+ \r
+ __IO uint8_t F3R1;\r
+ __IO uint8_t F3R2;\r
+ __IO uint8_t F3R3;\r
+ __IO uint8_t F3R4;\r
+ __IO uint8_t F3R5;\r
+ __IO uint8_t F3R6;\r
+ __IO uint8_t F3R7;\r
+ __IO uint8_t F3R8;\r
+ }\r
+ Filter23;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t F4R1;\r
+ __IO uint8_t F4R2;\r
+ __IO uint8_t F4R3;\r
+ __IO uint8_t F4R4;\r
+ __IO uint8_t F4R5;\r
+ __IO uint8_t F4R6;\r
+ __IO uint8_t F4R7;\r
+ __IO uint8_t F4R8;\r
+ \r
+ __IO uint8_t F5R1;\r
+ __IO uint8_t F5R2;\r
+ __IO uint8_t F5R3;\r
+ __IO uint8_t F5R4;\r
+ __IO uint8_t F5R5;\r
+ __IO uint8_t F5R6;\r
+ __IO uint8_t F5R7;\r
+ __IO uint8_t F5R8;\r
+ }\r
+ Filter45;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t ESR;\r
+ __IO uint8_t EIER;\r
+ __IO uint8_t TECR;\r
+ __IO uint8_t RECR;\r
+ __IO uint8_t BTR1;\r
+ __IO uint8_t BTR2;\r
+ u8 Reserved1[2];\r
+ __IO uint8_t FMR1;\r
+ __IO uint8_t FMR2;\r
+ __IO uint8_t FCR1;\r
+ __IO uint8_t FCR2;\r
+ __IO uint8_t FCR3;\r
+ u8 Reserved2[3];\r
+ }\r
+ Config;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t MFMI;\r
+ __IO uint8_t MDLCR;\r
+ __IO uint8_t MIDR1;\r
+ __IO uint8_t MIDR2;\r
+ __IO uint8_t MIDR3;\r
+ __IO uint8_t MIDR4;\r
+ __IO uint8_t MDAR1;\r
+ __IO uint8_t MDAR2;\r
+ __IO uint8_t MDAR3;\r
+ __IO uint8_t MDAR4;\r
+ __IO uint8_t MDAR5;\r
+ __IO uint8_t MDAR6;\r
+ __IO uint8_t MDAR7;\r
+ __IO uint8_t MDAR8;\r
+ __IO uint8_t MTSRL;\r
+ __IO uint8_t MTSRH;\r
+ }\r
+ RxFIFO;\r
+ }Page; \r
+} CAN_TypeDef;\r
+/** @addtogroup CAN_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*******************************Common****************************************/\r
+/* CAN Master Control Register bits */\r
+#define CAN_MCR_INRQ ((uint8_t)0x01)\r
+#define CAN_MCR_SLEEP ((uint8_t)0x02)\r
+#define CAN_MCR_TXFP ((uint8_t)0x04)\r
+#define CAN_MCR_RFLM ((uint8_t)0x08)\r
+#define CAN_MCR_NART ((uint8_t)0x10)\r
+#define CAN_MCR_AWUM ((uint8_t)0x20)\r
+#define CAN_MCR_ABOM ((uint8_t)0x40)\r
+#define CAN_MCR_TTCM ((uint8_t)0x80)\r
+\r
+/* CAN Master Status Register bits */\r
+#define CAN_MSR_INAK ((uint8_t)0x01)\r
+#define CAN_MSR_SLAK ((uint8_t)0x02)\r
+#define CAN_MSR_ERRI ((uint8_t)0x04)\r
+#define CAN_MSR_WKUI ((uint8_t)0x08)\r
+#define CAN_MSR_TX ((uint8_t)0x10)\r
+#define CAN_MSR_RX ((uint8_t)0x20)\r
+\r
+/* CAN Transmit Status Register bits */\r
+#define CAN_TSR_RQCP0 ((uint8_t)0x01)\r
+#define CAN_TSR_RQCP1 ((uint8_t)0x02)\r
+#define CAN_TSR_RQCP2 ((uint8_t)0x04)\r
+#define CAN_TSR_RQCP012 ((uint8_t)0x07)\r
+#define CAN_TSR_TXOK0 ((uint8_t)0x10)\r
+#define CAN_TSR_TXOK1 ((uint8_t)0x20)\r
+#define CAN_TSR_TXOK2 ((uint8_t)0x40)\r
+\r
+#define CAN_TPR_CODE0 ((uint8_t)0x01)\r
+#define CAN_TPR_TME0 ((uint8_t)0x04)\r
+#define CAN_TPR_TME1 ((uint8_t)0x08)\r
+#define CAN_TPR_TME2 ((uint8_t)0x10)\r
+#define CAN_TPR_LOW0 ((uint8_t)0x20)\r
+#define CAN_TPR_LOW1 ((uint8_t)0x40)\r
+#define CAN_TPR_LOW2 ((uint8_t)0x80)\r
+/* CAN Receive FIFO Register bits */\r
+#define CAN_RFR_FMP01 ((uint8_t)0x03)\r
+#define CAN_RFR_FULL ((uint8_t)0x08)\r
+#define CAN_RFR_FOVR ((uint8_t)0x10)\r
+#define CAN_RFR_RFOM ((uint8_t)0x20)\r
+\r
+/* CAN Interrupt Register bits */\r
+#define CAN_IER_TMEIE ((uint8_t)0x01)\r
+#define CAN_IER_FMPIE ((uint8_t)0x02)\r
+#define CAN_IER_FFIE ((uint8_t)0x04)\r
+#define CAN_IER_FOVIE ((uint8_t)0x08)\r
+#define CAN_IER_WKUIE ((uint8_t)0x80)\r
+\r
+\r
+/* CAN diagnostic Register bits */\r
+#define CAN_DGR_LBKM ((uint8_t)0x01)\r
+#define CAN_DGR_SLIM ((uint8_t)0x02)\r
+#define CAN_DGR_SAMP ((uint8_t)0x04)\r
+#define CAN_DGR_RX ((uint8_t)0x08)\r
+#define CAN_DGR_TXM2E ((uint8_t)0x10)\r
+\r
+\r
+/* CAN page select Register bits */\r
+#define CAN_PSR_PS0 ((uint8_t)0x01)\r
+#define CAN_PSR_PS1 ((uint8_t)0x02)\r
+#define CAN_PSR_PS2 ((uint8_t)0x04)\r
+\r
+/*********************Tx MailBox & Fifo Page common bits***********************/\r
+#define CAN_MCSR_TXRQ ((uint8_t)0x01)\r
+#define CAN_MCSR_ABRQ ((uint8_t)0x02)\r
+#define CAN_MCSR_RQCP ((uint8_t)0x04)\r
+#define CAN_MCSR_TXOK ((uint8_t)0x08)\r
+#define CAN_MCSR_ALST ((uint8_t)0x10)\r
+#define CAN_MCSR_TERR ((uint8_t)0x20)\r
+\r
+#define CAN_MDLCR_DLC ((uint8_t)0x0F)\r
+#define CAN_MDLCR_TGT ((uint8_t)0x80)\r
+\r
+#define CAN_MIDR1_RTR ((uint8_t)0x20)\r
+#define CAN_MIDR1_IDE ((uint8_t)0x40)\r
+\r
+\r
+/*************************Filter Page******************************************/\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_ESR_EWGF ((uint8_t)0x01)\r
+#define CAN_ESR_EPVF ((uint8_t)0x02)\r
+#define CAN_ESR_BOFF ((uint8_t)0x04)\r
+#define CAN_ESR_LEC0 ((uint8_t)0x10)\r
+#define CAN_ESR_LEC1 ((uint8_t)0x20)\r
+#define CAN_ESR_LEC2 ((uint8_t)0x40)\r
+#define CAN_ESR_LEC ((uint8_t)0x70)\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_EIER_EWGIE ((uint8_t)0x01)\r
+#define CAN_EIER_EPVIE ((uint8_t)0x02)\r
+#define CAN_EIER_BOFIE ((uint8_t)0x04)\r
+#define CAN_EIER_LECIE ((uint8_t)0x10)\r
+#define CAN_EIER_ERRIE ((uint8_t)0x80) \r
+\r
+/* CAN transmit error counter Register bits(CAN_TECR) */\r
+#define CAN_TECR_TEC0 ((uint8_t)0x01) \r
+#define CAN_TECR_TEC1 ((uint8_t)0x02) \r
+#define CAN_TECR_TEC2 ((uint8_t)0x04) \r
+#define CAN_TECR_TEC3 ((uint8_t)0x08) \r
+#define CAN_TECR_TEC4 ((uint8_t)0x10) \r
+#define CAN_TECR_TEC5 ((uint8_t)0x20) \r
+#define CAN_TECR_TEC6 ((uint8_t)0x40) \r
+#define CAN_TECR_TEC7 ((uint8_t)0x80) \r
+\r
+/* CAN RECEIVE error counter Register bits(CAN_TECR) */\r
+#define CAN_RECR_REC0 ((uint8_t)0x01) \r
+#define CAN_RECR_REC1 ((uint8_t)0x02) \r
+#define CAN_RECR_REC2 ((uint8_t)0x04) \r
+#define CAN_RECR_REC3 ((uint8_t)0x08) \r
+#define CAN_RECR_REC4 ((uint8_t)0x10) \r
+#define CAN_RECR_REC5 ((uint8_t)0x20) \r
+#define CAN_RECR_REC6 ((uint8_t)0x40) \r
+#define CAN_RECR_REC7 ((uint8_t)0x80) \r
+\r
+/* CAN filter mode register bits (CAN_FMR) */\r
+#define CAN_FMR1_FML0 ((uint8_t)0x01) \r
+#define CAN_FMR1_FMH0 ((uint8_t)0x02) \r
+#define CAN_FMR1_FML1 ((uint8_t)0x04) \r
+#define CAN_FMR1_FMH1 ((uint8_t)0x08) \r
+#define CAN_FMR1_FML2 ((uint8_t)0x10) \r
+#define CAN_FMR1_FMH2 ((uint8_t)0x20) \r
+#define CAN_FMR1_FML3 ((uint8_t)0x40) \r
+#define CAN_FMR1_FMH3 ((uint8_t)0x80) \r
+\r
+#define CAN_FMR2_FML4 ((uint8_t)0x01) \r
+#define CAN_FMR2_FMH4 ((uint8_t)0x02) \r
+#define CAN_FMR2_FML5 ((uint8_t)0x04) \r
+#define CAN_FMR2_FMH5 ((uint8_t)0x08) \r
+\r
+/* CAN filter Config register bits (CAN_FCR) */\r
+#define CAN_FCR1_FACT0 ((uint8_t)0x01) \r
+#define CAN_FCR1_FACT1 ((uint8_t)0x10) \r
+#define CAN_FCR2_FACT2 ((uint8_t)0x01) \r
+#define CAN_FCR2_FACT3 ((uint8_t)0x10) \r
+#define CAN_FCR3_FACT4 ((uint8_t)0x01) \r
+#define CAN_FCR3_FACT5 ((uint8_t)0x10) \r
+\r
+#define CAN_FCR1_FSC00 ((uint8_t)0x02) \r
+#define CAN_FCR1_FSC01 ((uint8_t)0x04) \r
+#define CAN_FCR1_FSC10 ((uint8_t)0x20) \r
+#define CAN_FCR1_FSC11 ((uint8_t)0x40) \r
+#define CAN_FCR2_FSC20 ((uint8_t)0x02) \r
+#define CAN_FCR2_FSC21 ((uint8_t)0x04) \r
+#define CAN_FCR2_FSC30 ((uint8_t)0x20) \r
+#define CAN_FCR2_FSC31 ((uint8_t)0x40) \r
+#define CAN_FCR3_FSC40 ((uint8_t)0x02) \r
+#define CAN_FCR3_FSC41 ((uint8_t)0x04) \r
+#define CAN_FCR3_FSC50 ((uint8_t)0x20) \r
+#define CAN_FCR3_FSC51 ((uint8_t)0x40)\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CAN_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CAN_MCR_RESET_VALUE ((uint8_t)0x02)\r
+#define CAN_MSR_RESET_VALUE ((uint8_t)0x02)\r
+#define CAN_TSR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)\r
+#define CAN_RFR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)\r
+#define CAN_PSR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+#define CAN_ESR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_EIER_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_TECR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_RECR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)\r
+#define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)\r
+#define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_FCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+#define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration Registers (CFG)\r
+ */\r
+\r
+typedef struct CFG_struct\r
+{\r
+ __IO uint8_t GCR; /*!< Global Configuration register */\r
+}\r
+CFG_TypeDef;\r
+\r
+/** @addtogroup CFG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CFG_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */\r
+#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripherals Base Address */\r
+/******************************************************************************/\r
+\r
+/** @addtogroup MAP_FILE_Base_Addresses\r
+ * @{\r
+ */\r
+#define OPT_BaseAddress 0x4800\r
+#define GPIOA_BaseAddress 0x5000\r
+#define GPIOB_BaseAddress 0x5005\r
+#define GPIOC_BaseAddress 0x500A\r
+#define GPIOD_BaseAddress 0x500F\r
+#define GPIOE_BaseAddress 0x5014\r
+#define GPIOF_BaseAddress 0x5019\r
+#define GPIOG_BaseAddress 0x501E\r
+#define GPIOH_BaseAddress 0x5023\r
+#define GPIOI_BaseAddress 0x5028\r
+#define FLASH_BaseAddress 0x505A\r
+#define EXTI_BaseAddress 0x50A0\r
+#define RST_BaseAddress 0x50B3\r
+#define CLK_BaseAddress 0x50C0\r
+#define WWDG_BaseAddress 0x50D1\r
+#define IWDG_BaseAddress 0x50E0\r
+#define AWU_BaseAddress 0x50F0\r
+#define BEEP_BaseAddress 0x50F3\r
+#define SPI_BaseAddress 0x5200\r
+#define I2C_BaseAddress 0x5210\r
+#define UART1_BaseAddress 0x5230\r
+#define UART2_BaseAddress 0x5240\r
+#define UART3_BaseAddress 0x5240\r
+#define TIM1_BaseAddress 0x5250\r
+#define TIM2_BaseAddress 0x5300\r
+#define TIM3_BaseAddress 0x5320\r
+#define TIM4_BaseAddress 0x5340\r
+#define TIM5_BaseAddress 0x5300\r
+#define TIM6_BaseAddress 0x5340\r
+#define ADC1_BaseAddress 0x53E0\r
+#define ADC2_BaseAddress 0x5400\r
+#define CAN_BaseAddress 0x5420\r
+#define CFG_BaseAddress 0x7F60\r
+#define ITC_BaseAddress 0x7F70\r
+#define DM_BaseAddress 0x7F90\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripherals declarations */\r
+/******************************************************************************/\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+ #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)\r
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+#define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */\r
+\r
+#define AWU ((AWU_TypeDef *) AWU_BaseAddress)\r
+\r
+#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)\r
+\r
+#if defined (STM8S208) || defined (STM8AF52Ax)\r
+ #define CAN ((CAN_TypeDef *) CAN_BaseAddress)\r
+#endif /* (STM8S208) || (STM8AF52Ax) */\r
+\r
+#define CLK ((CLK_TypeDef *) CLK_BaseAddress)\r
+\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)\r
+\r
+#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)\r
+\r
+#define OPT ((OPT_TypeDef *) OPT_BaseAddress)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)\r
+\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)\r
+\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)\r
+\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)\r
+\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)\r
+\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)\r
+\r
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */\r
+\r
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)\r
+ #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+\r
+#define RST ((RST_TypeDef *) RST_BaseAddress)\r
+\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)\r
+\r
+#define SPI ((SPI_TypeDef *) SPI_BaseAddress)\r
+#define I2C ((I2C_TypeDef *) I2C_BaseAddress)\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)\r
+ #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */\r
+\r
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)\r
+ #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)\r
+#endif /* STM8S105 || STM8S005 || STM8AF626x */\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+\r
+#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/\r
+\r
+#ifdef STM8S903\r
+ #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)\r
+ #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)\r
+#endif /* STM8S903 */ \r
+\r
+#define ITC ((ITC_TypeDef *) ITC_BaseAddress)\r
+\r
+#define CFG ((CFG_TypeDef *) CFG_BaseAddress)\r
+\r
+#define DM ((DM_TypeDef *) DM_BaseAddress)\r
+\r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm8s_conf.h"\r
+#endif\r
+\r
+/* Exported macro --------------------------------------------------------------*/\r
+\r
+/*============================== Interrupts ====================================*/\r
+#ifdef _RAISONANCE_\r
+ #include <intrins.h>\r
+ #define enableInterrupts() _rim_() /* enable interrupts */\r
+ #define disableInterrupts() _sim_() /* disable interrupts */\r
+ #define rim() _rim_() /* enable interrupts */\r
+ #define sim() _sim_() /* disable interrupts */\r
+ #define nop() _nop_() /* No Operation */\r
+ #define trap() _trap_() /* Trap (soft IT) */\r
+ #define wfi() _wfi_() /* Wait For Interrupt */\r
+ #define halt() _halt_() /* Halt */\r
+#elif defined(_COSMIC_)\r
+ #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */\r
+ #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */\r
+ #define rim() {_asm("rim\n");} /* enable interrupts */\r
+ #define sim() {_asm("sim\n");} /* disable interrupts */\r
+ #define nop() {_asm("nop\n");} /* No Operation */\r
+ #define trap() {_asm("trap\n");} /* Trap (soft IT) */\r
+ #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */\r
+ #define halt() {_asm("halt\n");} /* Halt */\r
+#else /*_IAR_*/\r
+ #include <intrinsics.h>\r
+ #define enableInterrupts() __enable_interrupt() /* enable interrupts */\r
+ #define disableInterrupts() __disable_interrupt() /* disable interrupts */\r
+ #define rim() __enable_interrupt() /* enable interrupts */\r
+ #define sim() __disable_interrupt() /* disable interrupts */\r
+ #define nop() __no_operation() /* No Operation */\r
+ #define trap() __trap() /* Trap (soft IT) */\r
+ #define wfi() __wait_for_interrupt() /* Wait For Interrupt */\r
+ #define halt() __halt() /* Halt */\r
+#endif /*_RAISONANCE_*/\r
+\r
+/*============================== Interrupt vector Handling ========================*/\r
+\r
+#ifdef _COSMIC_\r
+ #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)\r
+ #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)\r
+#endif /* _COSMIC_ */\r
+\r
+#ifdef _RAISONANCE_\r
+ #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b\r
+ #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap\r
+#endif /* _RAISONANCE_ */\r
+\r
+#ifdef _IAR_\r
+ #define STRINGVECTOR(x) #x\r
+ #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )\r
+ #define INTERRUPT_HANDLER( a, b ) \\r
+ _Pragma( VECTOR_ID( (b)+2 ) ) \\r
+ __interrupt void (a)( void )\r
+ #define INTERRUPT_HANDLER_TRAP(a) \\r
+ _Pragma( VECTOR_ID( 1 ) ) \\r
+ __interrupt void (a) (void) \r
+#endif /* _IAR_ */\r
+\r
+/*============================== Interrupt Handler declaration ========================*/\r
+#ifdef _COSMIC_\r
+ #define INTERRUPT @far @interrupt\r
+#elif defined(_IAR_)\r
+ #define INTERRUPT __interrupt\r
+#endif /* _COSMIC_ */\r
+\r
+/*============================== Handling bits ====================================*/\r
+/*-----------------------------------------------------------------------------\r
+Method : I\r
+Description : Handle the bit from the character variables.\r
+Comments : The different parameters of commands are\r
+ - VAR : Name of the character variable where the bit is located.\r
+ - Place : Bit position in the variable (7 6 5 4 3 2 1 0)\r
+ - Value : Can be 0 (reset bit) or not 0 (set bit)\r
+ The "MskBit" command allows to select some bits in a source\r
+ variables and copy it in a destination var (return the value).\r
+ The "ValBit" command returns the value of a bit in a char\r
+ variable: the bit is reset if it returns 0 else the bit is set.\r
+ This method generates not an optimised code yet.\r
+-----------------------------------------------------------------------------*/\r
+#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )\r
+#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )\r
+\r
+#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )\r
+#define AffBit(VAR,Place,Value) ((Value) ? \\r
+ ((VAR) |= ((uint8_t)1<<(Place))) : \\r
+ ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))\r
+#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )\r
+\r
+#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))\r
+\r
+#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */\r
+#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */\r
+#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */\r
+#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */\r
+\r
+/*============================== Assert Macros ====================================*/\r
+#define IS_STATE_VALUE_OK(SensitivityValue) \\r
+ (((SensitivityValue) == ENABLE) || \\r
+ ((SensitivityValue) == DISABLE))\r
+\r
+/*-----------------------------------------------------------------------------\r
+Method : II\r
+Description : Handle directly the bit.\r
+Comments : The idea is to handle directly with the bit name. For that, it is\r
+ necessary to have RAM area descriptions (example: HW register...)\r
+ and the following command line for each area.\r
+ This method generates the most optimized code.\r
+-----------------------------------------------------------------------------*/\r
+\r
+#define AREA 0x00 /* The area of bits begins at address 0x10. */\r
+\r
+#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )\r
+#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )\r
+#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM8S_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**
+ ******************************************************************************
+ * @file stm8s.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 18-November-2011
+ * @brief This file contains all HW registers definitions and memory mapping.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8S_H
+#define __STM8S_H
+
+/** @addtogroup STM8S_StdPeriph_Driver
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM8S or STM8A device used in your
+ application. */
+
+ /* #define STM8S208 */ /*!< STM8S High density devices with CAN */
+ /* #define STM8S207 */ /*!< STM8S High density devices without CAN */
+ /* #define STM8S007 */ /*!< STM8S Value Line High density devices */
+ /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */
+ /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */
+ /* #define STM8S105 */ /*!< STM8S Medium density devices */
+ /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */
+ /* #define STM8AF626x */ /*!< STM8A Medium density devices */
+ /* #define STM8S103 */ /*!< STM8S Low density devices */
+ /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */
+ /* #define STM8S903 */ /*!< STM8S Low density devices */
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
+ STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
+ density ranges between 32 to 128 Kbytes
+ - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
+ STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory
+ density ranges between 8 to 32 Kbytes
+ - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers
+ where the Flash memory density ranges between 32 to 128 Kbytes.
+ - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
+ where the Flash memory density ranges between 16 to 32-Kbytes.
+ - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers
+ where the Flash density is 8 Kbytes. */
+
+#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
+ !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
+ !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
+ !defined (STM8S003)&& !defined (STM8S005)
+ #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"
+#endif
+
+/******************************************************************************/
+/* Library configuration section */
+/******************************************************************************/
+/* Check the used compiler */
+#if defined(__CSMC__)
+ #define _COSMIC_
+#elif defined(__RCST7__)
+ #define _RAISONANCE_
+#elif defined(__ICCSTM8__)
+ #define _IAR_
+#elif defined(SDCC)
+ #define _SDCC_
+#else
+ #error "Unsupported Compiler!" /* Compiler defines not found */
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/* Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will be
+ based on direct access to peripherals registers */
+ #define USE_STDPERIPH_DRIVER
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_Value
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax)
+ #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/
+ #else
+ #define HSE_VALUE ((u32)14745600) /* Value of the External oscillator in Hz*/
+ #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */
+#endif /* HSE_Value */
+
+/**
+ * @brief Definition of Device on-chip RC oscillator frequencies
+ */
+#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
+#define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */
+
+#ifdef _COSMIC_
+ #define FAR @far
+ #define NEAR @near
+ #define TINY @tiny
+ #define EEPROM @eeprom
+ #define CONST const
+#elif defined (_RAISONANCE_) /* __RCST7__ */
+ #define FAR far
+ #define NEAR data
+ #define TINY page0
+ #define EEPROM eeprom
+ #define CONST code
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax)
+ /*!< Used with memory Models for code higher than 64K */
+ #define MEMCPY fmemcpy
+ #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */
+ /*!< Used with memory Models for code less than 64K */
+ #define MEMCPY memcpy
+ #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
+#else /*_IAR_*/
+ #define FAR __far
+// #define NEAR __near
+ #define NEAR //hack SDCC gets confused by __near
+ #define TINY __tiny
+ #define EEPROM __eeprom
+ #define CONST const
+#endif /* __CSMC__ */
+
+/* For FLASH routines, select whether pointer will be declared as near (2 bytes,
+ to handle code smaller than 64KB) or far (3 bytes, to handle code larger
+ than 64K) */
+
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \
+ defined (STM8S903) || defined (STM8AF626x)
+/*!< Used with memory Models for code smaller than 64K */
+ //#define PointerAttr NEAR
+ #define PointerAttr NEAR
+
+#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
+/*!< Used with memory Models for code higher than 64K */
+ #define PointerAttr FAR
+#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */
+
+/* Uncomment the line below to enable the FLASH functions execution from RAM */
+#if !defined (RAM_EXECUTION)
+/* #define RAM_EXECUTION (1) */
+#endif /* RAM_EXECUTION */
+
+#ifdef RAM_EXECUTION
+ #ifdef _COSMIC_
+ #define IN_RAM(a) a
+ #elif defined (_RAISONANCE_) /* __RCST7__ */
+ #define IN_RAM(a) a inram
+ #else /*_IAR_*/
+ #define IN_RAM(a) __ramfunc a
+ #endif /* _COSMIC_ */
+#else
+ #define IN_RAM(a) a
+#endif /* RAM_EXECUTION */
+
+/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/
+#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */
+#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01) /*!< [23:16] sub1 version */
+#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */
+#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */
+#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM8S_STDPERIPH_VERSION_RC))
+
+/******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Exported types and constants ----------------------------------------------*/
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+#define __I volatile const /*!< defines 'read only' permissions */
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+#if defined(SDCC)
+#include <stdint.h>
+#else
+/*!< Signed integer types */
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed long int32_t;
+
+/*!< Unsigned integer types */
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned long uint32_t;
+#endif
+
+/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX (255)
+#define S8_MAX (127)
+#define S8_MIN (-128)
+#define U16_MAX (65535u)
+#define S16_MAX (32767)
+#define S16_MIN (-32768)
+#define U32_MAX (4294967295uL)
+#define S32_MAX (2147483647)
+#define S32_MIN (-2147483648uL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup MAP_FILE_Exported_Types_and_Constants
+ * @{
+ */
+
+/******************************************************************************/
+/* IP registers structures */
+/******************************************************************************/
+
+/**
+ * @brief General Purpose I/Os (GPIO)
+ */
+ typedef volatile struct GPIO_struct
+{
+ __IO uint8_t ODR; /*!< Output Data Register */
+ __IO uint8_t IDR; /*!< Input Data Register */
+ __IO uint8_t DDR; /*!< Data Direction Register */
+ __IO uint8_t CR1; /*!< Configuration Register 1 */
+ __IO uint8_t CR2; /*!< Configuration Register 2 */
+}
+GPIO_TypeDef;
+
+/** @addtogroup GPIO_Registers_Reset_Value
+ * @{
+ */
+
+#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
+#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
+ defined(STM8S903) || defined(STM8AF626x)
+/**
+ * @brief Analog to Digital Converter (ADC1)
+ */
+ typedef volatile struct ADC1_struct
+ {
+ __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */
+ __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */
+ __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */
+ uint8_t RESERVED[12]; /*!< Reserved byte */
+ __IO uint8_t CSR; /*!< ADC1 control status register */
+ __IO uint8_t CR1; /*!< ADC1 configuration register 1 */
+ __IO uint8_t CR2; /*!< ADC1 configuration register 2 */
+ __IO uint8_t CR3; /*!< ADC1 configuration register 3 */
+ __IO uint8_t DRH; /*!< ADC1 Data high */
+ __IO uint8_t DRL; /*!< ADC1 Data low */
+ __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */
+ __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */
+ __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/
+ __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/
+ __IO uint8_t LTRH; /*!< ADC1 low threshold register high */
+ __IO uint8_t LTRL; /*!< ADC1 low threshold register low */
+ __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */
+ __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */
+ __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */
+ __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */
+ }
+ ADC1_TypeDef;
+
+/** @addtogroup ADC1_Registers_Reset_Value
+ * @{
+ */
+ #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03)
+ #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF)
+ #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00)
+ #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC1_Registers_Bits_Definition
+ * @{
+ */
+ #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
+ #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
+ #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
+ #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */
+ #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
+
+ #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
+ #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
+ #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
+
+ #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
+ #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
+ #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
+ #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */
+
+ #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */
+ #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */
+
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Analog to Digital Converter (ADC2)
+ */
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
+ typedef volatile struct ADC2_struct
+ {
+ __IO uint8_t CSR; /*!< ADC2 control status register */
+ __IO uint8_t CR1; /*!< ADC2 configuration register 1 */
+ __IO uint8_t CR2; /*!< ADC2 configuration register 2 */
+ uint8_t RESERVED; /*!< Reserved byte */
+ __IO uint8_t DRH; /*!< ADC2 Data high */
+ __IO uint8_t DRL; /*!< ADC2 Data low */
+ __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */
+ __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */
+ }
+ ADC2_TypeDef;
+
+/** @addtogroup ADC2_Registers_Reset_Value
+ * @{
+ */
+ #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00)
+ #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00)
+ #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00)
+ #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
+ #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @addtogroup ADC2_Registers_Bits_Definition
+ * @{
+ */
+ #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
+ #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
+ #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
+
+ #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
+ #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
+ #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
+
+ #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
+ #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
+ #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
+
+#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+
+/**
+ * @brief Auto Wake Up (AWU) peripheral registers.
+ */
+ typedef volatile struct AWU_struct
+{
+ __IO uint8_t CSR; /*!< AWU Control status register */
+ __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
+ __IO uint8_t TBR; /*!< AWU Time base selection register */
+}
+AWU_TypeDef;
+
+/** @addtogroup AWU_Registers_Reset_Value
+ * @{
+ */
+#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
+#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
+#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup AWU_Registers_Bits_Definition
+ * @{
+ */
+
+#define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */
+#define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
+#define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */
+
+#define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
+
+#define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Beeper (BEEP) peripheral registers.
+ */
+
+ typedef volatile struct BEEP_struct
+{
+ __IO uint8_t CSR; /*!< BEEP Control status register */
+}
+BEEP_TypeDef;
+
+/** @addtogroup BEEP_Registers_Reset_Value
+ * @{
+ */
+#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @addtogroup BEEP_Registers_Bits_Definition
+ * @{
+ */
+#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
+#define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */
+#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Clock Controller (CLK)
+ */
+ typedef volatile struct CLK_struct
+{
+ __IO uint8_t ICKR; /*!< Internal Clocks Control Register */
+ __IO uint8_t ECKR; /*!< External Clocks Control Register */
+ uint8_t RESERVED; /*!< Reserved byte */
+ __IO uint8_t CMSR; /*!< Clock Master Status Register */
+ __IO uint8_t SWR; /*!< Clock Master Switch Register */
+ __IO uint8_t SWCR; /*!< Switch Control Register */
+ __IO uint8_t CKDIVR; /*!< Clock Divider Register */
+ __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */
+ __IO uint8_t CSSR; /*!< Clock Security System Register */
+ __IO uint8_t CCOR; /*!< Configurable Clock Output Register */
+ __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */
+ uint8_t RESERVED1; /*!< Reserved byte */
+ __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
+ __IO uint8_t SWIMCCR; /*!< SWIM clock control register */
+}
+CLK_TypeDef;
+
+/** @addtogroup CLK_Registers_Reset_Value
+ * @{
+ */
+
+#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
+#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
+#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)
+#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
+#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
+#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
+#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
+#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CLK_Registers_Bits_Definition
+ * @{
+ */
+#define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
+#define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */
+#define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */
+#define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
+#define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */
+#define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */
+
+#define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */
+#define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */
+
+#define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */
+
+#define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */
+
+#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */
+#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */
+#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */
+#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/
+
+#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */
+#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */
+
+#define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */
+#define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */
+#define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */
+#define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */
+#define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */
+#define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */
+#define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */
+#define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */
+#define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */
+#define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */
+#define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */
+
+#define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */
+#define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */
+#define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */
+
+#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */
+#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */
+#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */
+#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */
+
+#define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */
+#define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */
+#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */
+#define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */
+
+#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */
+
+#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer with complementary PWM outputs (TIM1)
+ */
+
+ typedef volatile struct TIM1_struct
+{
+ __IO uint8_t CR1; /*!< control register 1 */
+ __IO uint8_t CR2; /*!< control register 2 */
+ __IO uint8_t SMCR; /*!< Synchro mode control register */
+ __IO uint8_t ETR; /*!< external trigger register */
+ __IO uint8_t IER; /*!< interrupt enable register*/
+ __IO uint8_t SR1; /*!< status register 1 */
+ __IO uint8_t SR2; /*!< status register 2 */
+ __IO uint8_t EGR; /*!< event generation register */
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */
+ __IO uint8_t CCMR4; /*!< CC mode register 4 */
+ __IO uint8_t CCER1; /*!< CC enable register 1 */
+ __IO uint8_t CCER2; /*!< CC enable register 2 */
+ __IO uint8_t CNTRH; /*!< counter high */
+ __IO uint8_t CNTRL; /*!< counter low */
+ __IO uint8_t PSCRH; /*!< prescaler high */
+ __IO uint8_t PSCRL; /*!< prescaler low */
+ __IO uint8_t ARRH; /*!< auto-reload register high */
+ __IO uint8_t ARRL; /*!< auto-reload register low */
+ __IO uint8_t RCR; /*!< Repetition Counter register */
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
+ __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
+ __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
+ __IO uint8_t BKR; /*!< Break Register */
+ __IO uint8_t DTR; /*!< dead-time register */
+ __IO uint8_t OISR; /*!< Output idle register */
+}
+TIM1_TypeDef;
+
+/** @addtogroup TIM1_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
+#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
+#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
+#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM1_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */
+#define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */
+#define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
+/* CR2*/
+#define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */
+#define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */
+#define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */
+#define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */
+/* SMCR*/
+#define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
+#define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */
+#define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
+/*ETR*/
+#define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
+#define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */
+#define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
+#define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
+/*IER*/
+#define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
+#define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
+#define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/
+#define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
+#define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
+#define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
+#define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
+#define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
+#define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */
+#define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
+#define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */
+#define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
+#define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
+#define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
+#define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
+
+#define CCMR_TIxDirect_Set ((uint8_t)0x01)
+/*CCER1*/
+#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
+#define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
+#define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */
+#define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */
+#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
+#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
+#define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTRH*/
+#define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
+/*CNTRL*/
+#define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCH*/
+#define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*PSCL*/
+#define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
+/*ARR*/
+#define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*RCR*/
+#define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
+/*CCR1*/
+#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+/*CCR4*/
+#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
+#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
+/*BKR*/
+#define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */
+#define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
+#define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */
+#define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */
+#define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */
+#define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */
+#define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */
+/*DTR*/
+#define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
+/*OISR*/
+#define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
+#define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
+#define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
+#define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
+#define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
+#define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
+#define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer (TIM2)
+ */
+
+ typedef volatile struct TIM2_struct
+{
+ __IO uint8_t CR1; /*!< control register 1 */
+#if defined(STM8S103) || defined(STM8S003)
+ uint8_t RESERVED1; /*!< Reserved register */
+ uint8_t RESERVED2; /*!< Reserved register */
+#endif
+ __IO uint8_t IER; /*!< interrupt enable register */
+ __IO uint8_t SR1; /*!< status register 1 */
+ __IO uint8_t SR2; /*!< status register 2 */
+ __IO uint8_t EGR; /*!< event generation register */
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */
+ __IO uint8_t CCER1; /*!< CC enable register 1 */
+ __IO uint8_t CCER2; /*!< CC enable register 2 */
+ __IO uint8_t CNTRH; /*!< counter high */
+ __IO uint8_t CNTRL; /*!< counter low */
+ __IO uint8_t PSCR; /*!< prescaler register */
+ __IO uint8_t ARRH; /*!< auto-reload register high */
+ __IO uint8_t ARRL; /*!< auto-reload register low */
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
+}
+TIM2_TypeDef;
+
+/** @addtogroup TIM2_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
+#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
+#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
+#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM2_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
+#define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTR*/
+#define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer (TIM3)
+ */
+ typedef volatile struct TIM3_struct
+{
+ __IO uint8_t CR1; /*!< control register 1 */
+ __IO uint8_t IER; /*!< interrupt enable register */
+ __IO uint8_t SR1; /*!< status register 1 */
+ __IO uint8_t SR2; /*!< status register 2 */
+ __IO uint8_t EGR; /*!< event generation register */
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */
+ __IO uint8_t CCER1; /*!< CC enable register 1 */
+ __IO uint8_t CNTRH; /*!< counter high */
+ __IO uint8_t CNTRL; /*!< counter low */
+ __IO uint8_t PSCR; /*!< prescaler register */
+ __IO uint8_t ARRH; /*!< auto-reload register high */
+ __IO uint8_t ARRL; /*!< auto-reload register low */
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
+}
+TIM3_TypeDef;
+
+/** @addtogroup TIM3_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)
+#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
+#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
+#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM3_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
+#define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CNTR*/
+#define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 8-bit system timer (TIM4)
+ */
+
+ typedef volatile struct TIM4_struct
+{
+ __IO uint8_t CR1; /*!< control register 1 */
+#if defined(STM8S103) || defined(STM8S003)
+ uint8_t RESERVED1; /*!< Reserved register */
+ uint8_t RESERVED2; /*!< Reserved register */
+#endif
+ __IO uint8_t IER; /*!< interrupt enable register */
+ __IO uint8_t SR1; /*!< status register 1 */
+ __IO uint8_t EGR; /*!< event generation register */
+ __IO uint8_t CNTR; /*!< counter register */
+ __IO uint8_t PSCR; /*!< prescaler register */
+ __IO uint8_t ARR; /*!< auto-reload register */
+}
+TIM4_TypeDef;
+
+/** @addtogroup TIM4_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM4_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/*EGR*/
+#define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CNTR*/
+#define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */
+/*ARR*/
+#define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer with synchro module (TIM5)
+ */
+
+ typedef volatile struct TIM5_struct
+{
+ __IO uint8_t CR1; /*!<TIM5 Control Register 1 */
+ __IO uint8_t CR2; /*!<TIM5 Control Register 2 */
+ __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */
+ __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */
+ __IO uint8_t SR1; /*!<TIM5 Status Register 1 */
+ __IO uint8_t SR2; /*!<TIM5 Status Register 2 */
+ __IO uint8_t EGR; /*!<TIM5 Event Generation Register */
+ __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */
+ __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */
+ __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */
+ __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */
+ __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */
+ __IO uint8_t CNTRH; /*!<TIM5 Counter High */
+ __IO uint8_t CNTRL; /*!<TIM5 Counter Low */
+ __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */
+ __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */
+ __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */
+ __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */
+ __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */
+ __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */
+ __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */
+ __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */
+ __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */
+}TIM5_TypeDef;
+
+/** @addtogroup TIM5_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
+#define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
+#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
+#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM5_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
+#define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
+#define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
+#define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
+/* CR2*/
+#define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */
+#define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */
+/* SMCR*/
+#define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */
+#define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
+/*IER*/
+#define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
+#define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
+#define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
+#define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTR*/
+#define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+/*CCMR*/
+#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 8-bit system timer with synchro module(TIM6)
+ */
+
+ typedef volatile struct TIM6_struct
+{
+ __IO uint8_t CR1; /*!< control register 1 */
+ __IO uint8_t CR2; /*!< control register 2 */
+ __IO uint8_t SMCR; /*!< Synchro mode control register */
+ __IO uint8_t IER; /*!< interrupt enable register */
+ __IO uint8_t SR1; /*!< status register 1 */
+ __IO uint8_t EGR; /*!< event generation register */
+ __IO uint8_t CNTR; /*!< counter register */
+ __IO uint8_t PSCR; /*!< prescaler register */
+ __IO uint8_t ARR; /*!< auto-reload register */
+}
+TIM6_TypeDef;
+/** @addtogroup TIM6_Registers_Reset_Value
+ * @{
+ */
+#define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_IER_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
+#define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
+
+/**
+* @}
+*/
+
+/** @addtogroup TIM6_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
+#define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
+#define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */
+#define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */
+#define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */
+/* CR2*/
+#define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */
+/* SMCR*/
+#define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */
+#define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
+/* IER*/
+#define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
+#define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
+/* SR1*/
+#define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
+/* EGR*/
+#define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
+#define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */
+/* CNTR*/
+#define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
+/* PSCR*/
+#define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */
+
+#define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
+/**
+ * @}
+ */
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Inter-Integrated Circuit (I2C)
+ */
+
+ typedef volatile struct I2C_struct
+{
+ __IO uint8_t CR1; /*!< I2C control register 1 */
+ __IO uint8_t CR2; /*!< I2C control register 2 */
+ __IO uint8_t FREQR; /*!< I2C frequency register */
+ __IO uint8_t OARL; /*!< I2C own address register LSB */
+ __IO uint8_t OARH; /*!< I2C own address register MSB */
+ uint8_t RESERVED1; /*!< Reserved byte */
+ __IO uint8_t DR; /*!< I2C data register */
+ __IO uint8_t SR1; /*!< I2C status register 1 */
+ __IO uint8_t SR2; /*!< I2C status register 2 */
+ __IO uint8_t SR3; /*!< I2C status register 3 */
+ __IO uint8_t ITR; /*!< I2C interrupt register */
+ __IO uint8_t CCRL; /*!< I2C clock control register low */
+ __IO uint8_t CCRH; /*!< I2C clock control register high */
+ __IO uint8_t TRISER; /*!< I2C maximum rise time register */
+ uint8_t RESERVED2; /*!< Reserved byte */
+}
+I2C_TypeDef;
+
+/** @addtogroup I2C_Registers_Reset_Value
+ * @{
+ */
+
+#define I2C_CR1_RESET_VALUE ((uint8_t)0x00)
+#define I2C_CR2_RESET_VALUE ((uint8_t)0x00)
+#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
+#define I2C_OARL_RESET_VALUE ((uint8_t)0x00)
+#define I2C_OARH_RESET_VALUE ((uint8_t)0x00)
+#define I2C_DR_RESET_VALUE ((uint8_t)0x00)
+#define I2C_SR1_RESET_VALUE ((uint8_t)0x00)
+#define I2C_SR2_RESET_VALUE ((uint8_t)0x00)
+#define I2C_SR3_RESET_VALUE ((uint8_t)0x00)
+#define I2C_ITR_RESET_VALUE ((uint8_t)0x00)
+#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
+#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
+#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Registers_Bits_Definition
+ * @{
+ */
+
+#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */
+#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */
+
+#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */
+#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */
+#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */
+#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */
+#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */
+
+#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */
+
+#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
+#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */
+
+#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */
+#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */
+#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */
+
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */
+
+#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */
+
+#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */
+#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */
+#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */
+#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */
+#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */
+
+#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */
+#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */
+#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */
+#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */
+
+#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */
+#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */
+#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */
+
+#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */
+
+#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */
+#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */
+#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
+
+#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Interrupt Controller (ITC)
+ */
+
+ typedef volatile struct ITC_struct
+{
+ __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */
+ __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */
+ __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */
+ __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */
+ __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */
+ __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
+ __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
+ __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
+}
+ITC_TypeDef;
+
+/** @addtogroup ITC_Registers_Reset_Value
+ * @{
+ */
+
+#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CPU_Registers_Bits_Definition
+ * @{
+ */
+
+#define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief External Interrupt Controller (EXTI)
+ */
+
+ typedef volatile struct EXTI_struct
+{
+ __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
+ __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
+}
+EXTI_TypeDef;
+
+/** @addtogroup EXTI_Registers_Reset_Value
+ * @{
+ */
+
+#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
+#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Registers_Bits_Definition
+ * @{
+ */
+
+#define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
+#define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */
+#define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
+#define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */
+
+#define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */
+#define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */
+
+/**
+ * @}
+ */
+
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief FLASH program and Data memory (FLASH)
+ */
+
+ typedef volatile struct FLASH_struct
+{
+ __IO uint8_t CR1; /*!< Flash control register 1 */
+ __IO uint8_t CR2; /*!< Flash control register 2 */
+ __IO uint8_t NCR2; /*!< Flash complementary control register 2 */
+ __IO uint8_t FPR; /*!< Flash protection register */
+ __IO uint8_t NFPR; /*!< Flash complementary protection register */
+ __IO uint8_t IAPSR; /*!< Flash in-application programming status register */
+ uint8_t RESERVED1; /*!< Reserved byte */
+ uint8_t RESERVED2; /*!< Reserved byte */
+ __IO uint8_t PUKR; /*!< Flash program memory unprotection register */
+ uint8_t RESERVED3; /*!< Reserved byte */
+ __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */
+}
+FLASH_TypeDef;
+
+/** @addtogroup FLASH_Registers_Reset_Value
+ * @{
+ */
+
+#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
+#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
+#define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
+#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
+#define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)
+#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Registers_Bits_Definition
+ * @{
+ */
+
+#define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */
+#define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */
+#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */
+#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */
+
+#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */
+#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */
+#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */
+#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */
+#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */
+
+#define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */
+#define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */
+#define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */
+#define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */
+#define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */
+
+#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */
+#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */
+#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */
+#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */
+#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */
+
+#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */
+
+#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Option Bytes (OPT)
+ */
+ typedef volatile struct OPT_struct
+{
+ __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
+ __IO uint8_t OPT1; /*!< Option byte 1: User boot code */
+ __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */
+ __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */
+ __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */
+ __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */
+ __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */
+ __IO uint8_t OPT4; /*!< Option byte 4: Clock option */
+ __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */
+ __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */
+ __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */
+ uint8_t RESERVED1; /*!< Reserved Option byte*/
+ uint8_t RESERVED2; /*!< Reserved Option byte*/
+ __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */
+ __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
+}
+OPT_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Independent Watchdog (IWDG)
+ */
+
+ typedef volatile struct IWDG_struct
+{
+ __IO uint8_t KR; /*!< Key Register */
+ __IO uint8_t PR; /*!< Prescaler Register */
+ __IO uint8_t RLR; /*!< Reload Register */
+}
+IWDG_TypeDef;
+
+/** @addtogroup IWDG_Registers_Reset_Value
+ * @{
+ */
+
+#define IWDG_PR_RESET_VALUE ((uint8_t)0x00)
+#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Window Watchdog (WWDG)
+ */
+
+ typedef volatile struct WWDG_struct
+{
+ __IO uint8_t CR; /*!< Control Register */
+ __IO uint8_t WR; /*!< Window Register */
+}
+WWDG_TypeDef;
+
+/** @addtogroup WWDG_Registers_Reset_Value
+ * @{
+ */
+
+#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
+#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Registers_Bits_Definition
+ * @{
+ */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */
+
+#define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */
+#define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Reset Controller (RST)
+ */
+
+ typedef volatile struct RST_struct
+{
+ __IO uint8_t SR; /*!< Reset status register */
+}
+RST_TypeDef;
+
+/** @addtogroup RST_Registers_Bits_Definition
+ * @{
+ */
+
+#define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */
+#define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */
+#define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */
+#define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */
+#define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Serial Peripheral Interface (SPI)
+ */
+
+ typedef volatile struct SPI_struct
+{
+ __IO uint8_t CR1; /*!< SPI control register 1 */
+ __IO uint8_t CR2; /*!< SPI control register 2 */
+ __IO uint8_t ICR; /*!< SPI interrupt control register */
+ __IO uint8_t SR; /*!< SPI status register */
+ __IO uint8_t DR; /*!< SPI data I/O register */
+ __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */
+ __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
+ __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
+}
+SPI_TypeDef;
+
+/** @addtogroup SPI_Registers_Reset_Value
+ * @{
+ */
+
+#define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */
+#define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */
+#define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register reset value */
+#define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */
+#define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */
+#define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */
+#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
+#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Registers_Bits_Definition
+ * @{
+ */
+
+#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
+#define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */
+#define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */
+#define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */
+#define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */
+#define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */
+
+#define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */
+#define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */
+#define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */
+#define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */
+#define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */
+#define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */
+#define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */
+
+#define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */
+#define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */
+#define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */
+#define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
+
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */
+#define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)
+ */
+
+ typedef volatile struct UART1_struct
+{
+ __IO uint8_t SR; /*!< UART1 status register */
+ __IO uint8_t DR; /*!< UART1 data register */
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
+ __IO uint8_t CR1; /*!< UART1 control register 1 */
+ __IO uint8_t CR2; /*!< UART1 control register 2 */
+ __IO uint8_t CR3; /*!< UART1 control register 3 */
+ __IO uint8_t CR4; /*!< UART1 control register 4 */
+ __IO uint8_t CR5; /*!< UART1 control register 5 */
+ __IO uint8_t GTR; /*!< UART1 guard time register */
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */
+}
+UART1_TypeDef;
+
+/** @addtogroup UART1_Registers_Reset_Value
+ * @{
+ */
+
+#define UART1_SR_RESET_VALUE ((uint8_t)0xC0)
+#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
+#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
+#define UART1_CR1_RESET_VALUE ((uint8_t)0x00)
+#define UART1_CR2_RESET_VALUE ((uint8_t)0x00)
+#define UART1_CR3_RESET_VALUE ((uint8_t)0x00)
+#define UART1_CR4_RESET_VALUE ((uint8_t)0x00)
+#define UART1_CR5_RESET_VALUE ((uint8_t)0x00)
+#define UART1_GTR_RESET_VALUE ((uint8_t)0x00)
+#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART1_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
+#define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
+#define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
+#define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
+#define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
+#define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
+#define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
+#define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
+
+#define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */
+
+#define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
+#define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */
+
+#define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
+#define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
+#define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */
+#define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */
+#define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
+#define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */
+#define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */
+#define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */
+
+#define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
+#define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
+#define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
+#define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
+#define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
+
+#define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
+#define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
+#define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */
+#define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */
+#define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */
+#define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
+
+#define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
+#define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
+#define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */
+
+#define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */
+#define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
+#define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
+#define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
+#define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)
+ */
+
+ typedef volatile struct UART2_struct
+{
+ __IO uint8_t SR; /*!< UART1 status register */
+ __IO uint8_t DR; /*!< UART1 data register */
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
+ __IO uint8_t CR1; /*!< UART1 control register 1 */
+ __IO uint8_t CR2; /*!< UART1 control register 2 */
+ __IO uint8_t CR3; /*!< UART1 control register 3 */
+ __IO uint8_t CR4; /*!< UART1 control register 4 */
+ __IO uint8_t CR5; /*!< UART1 control register 5 */
+ __IO uint8_t CR6; /*!< UART1 control register 6 */
+ __IO uint8_t GTR; /*!< UART1 guard time register */
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */
+}
+UART2_TypeDef;
+
+/** @addtogroup UART2_Registers_Reset_Value
+ * @{
+ */
+
+#define UART2_SR_RESET_VALUE ((uint8_t)0xC0)
+#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
+#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR1_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR2_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR3_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR4_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR5_RESET_VALUE ((uint8_t)0x00)
+#define UART2_CR6_RESET_VALUE ((uint8_t)0x00)
+#define UART2_GTR_RESET_VALUE ((uint8_t)0x00)
+#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART2_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
+#define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
+#define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
+#define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
+#define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
+#define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
+#define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
+#define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
+
+#define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */
+
+#define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
+#define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */
+
+#define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
+#define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
+#define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */
+#define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */
+#define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
+#define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */
+#define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */
+#define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */
+
+#define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
+#define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
+#define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
+#define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
+#define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
+
+#define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
+#define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
+#define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */
+#define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */
+#define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */
+#define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
+
+#define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
+#define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
+#define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */
+
+#define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */
+#define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
+#define UART2_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
+#define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
+#define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */
+
+#define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */
+#define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */
+#define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
+#define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
+#define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */
+#define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */
+
+/**
+ * @}
+ */
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)
+ */
+
+ typedef volatile struct UART3_struct
+{
+ __IO uint8_t SR; /*!< status register */
+ __IO uint8_t DR; /*!< data register */
+ __IO uint8_t BRR1; /*!< baud rate register */
+ __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */
+ __IO uint8_t CR1; /*!< control register 1 */
+ __IO uint8_t CR2; /*!< control register 2 */
+ __IO uint8_t CR3; /*!< control register 3 */
+ __IO uint8_t CR4; /*!< control register 4 */
+ uint8_t RESERVED; /*!< Reserved byte */
+ __IO uint8_t CR6; /*!< control register 5 */
+}
+UART3_TypeDef;
+
+/** @addtogroup UART3_Registers_Reset_Value
+ * @{
+ */
+
+#define UART3_SR_RESET_VALUE ((uint8_t)0xC0)
+#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
+#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
+#define UART3_CR1_RESET_VALUE ((uint8_t)0x00)
+#define UART3_CR2_RESET_VALUE ((uint8_t)0x00)
+#define UART3_CR3_RESET_VALUE ((uint8_t)0x00)
+#define UART3_CR4_RESET_VALUE ((uint8_t)0x00)
+#define UART3_CR6_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART3_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
+#define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
+#define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
+#define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
+#define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
+#define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
+#define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
+#define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
+
+#define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */
+
+#define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
+#define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */
+
+#define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
+#define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
+#define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */
+#define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */
+#define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
+#define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */
+#define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */
+#define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */
+
+#define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */
+#define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
+#define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
+#define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
+#define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
+
+#define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
+#define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
+
+#define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
+#define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
+#define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */
+
+#define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */
+#define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */
+#define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
+#define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */
+#define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */
+#define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */
+
+/**
+ * @}
+ */
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Controller Area Network (CAN)
+ */
+
+ typedef volatile struct
+{
+ __IO uint8_t MCR; /*!< CAN master control register */
+ __IO uint8_t MSR; /*!< CAN master status register */
+ __IO uint8_t TSR; /*!< CAN transmit status register */
+ __IO uint8_t TPR; /*!< CAN transmit priority register */
+ __IO uint8_t RFR; /*!< CAN receive FIFO register */
+ __IO uint8_t IER; /*!< CAN interrupt enable register */
+ __IO uint8_t DGR; /*!< CAN diagnosis register */
+ __IO uint8_t PSR; /*!< CAN page selection register */
+
+ union
+ {
+ struct
+ {
+ __IO uint8_t MCSR;
+ __IO uint8_t MDLCR;
+ __IO uint8_t MIDR1;
+ __IO uint8_t MIDR2;
+ __IO uint8_t MIDR3;
+ __IO uint8_t MIDR4;
+ __IO uint8_t MDAR1;
+ __IO uint8_t MDAR2;
+ __IO uint8_t MDAR3;
+ __IO uint8_t MDAR4;
+ __IO uint8_t MDAR5;
+ __IO uint8_t MDAR6;
+ __IO uint8_t MDAR7;
+ __IO uint8_t MDAR8;
+ __IO uint8_t MTSRL;
+ __IO uint8_t MTSRH;
+ }
+ TxMailbox;
+
+ struct
+ {
+ __IO uint8_t FR01;
+ __IO uint8_t FR02;
+ __IO uint8_t FR03;
+ __IO uint8_t FR04;
+ __IO uint8_t FR05;
+ __IO uint8_t FR06;
+ __IO uint8_t FR07;
+ __IO uint8_t FR08;
+
+ __IO uint8_t FR09;
+ __IO uint8_t FR10;
+ __IO uint8_t FR11;
+ __IO uint8_t FR12;
+ __IO uint8_t FR13;
+ __IO uint8_t FR14;
+ __IO uint8_t FR15;
+ __IO uint8_t FR16;
+ }
+ Filter;
+
+
+ struct
+ {
+ __IO uint8_t F0R1;
+ __IO uint8_t F0R2;
+ __IO uint8_t F0R3;
+ __IO uint8_t F0R4;
+ __IO uint8_t F0R5;
+ __IO uint8_t F0R6;
+ __IO uint8_t F0R7;
+ __IO uint8_t F0R8;
+
+ __IO uint8_t F1R1;
+ __IO uint8_t F1R2;
+ __IO uint8_t F1R3;
+ __IO uint8_t F1R4;
+ __IO uint8_t F1R5;
+ __IO uint8_t F1R6;
+ __IO uint8_t F1R7;
+ __IO uint8_t F1R8;
+ }
+ Filter01;
+
+ struct
+ {
+ __IO uint8_t F2R1;
+ __IO uint8_t F2R2;
+ __IO uint8_t F2R3;
+ __IO uint8_t F2R4;
+ __IO uint8_t F2R5;
+ __IO uint8_t F2R6;
+ __IO uint8_t F2R7;
+ __IO uint8_t F2R8;
+
+ __IO uint8_t F3R1;
+ __IO uint8_t F3R2;
+ __IO uint8_t F3R3;
+ __IO uint8_t F3R4;
+ __IO uint8_t F3R5;
+ __IO uint8_t F3R6;
+ __IO uint8_t F3R7;
+ __IO uint8_t F3R8;
+ }
+ Filter23;
+
+ struct
+ {
+ __IO uint8_t F4R1;
+ __IO uint8_t F4R2;
+ __IO uint8_t F4R3;
+ __IO uint8_t F4R4;
+ __IO uint8_t F4R5;
+ __IO uint8_t F4R6;
+ __IO uint8_t F4R7;
+ __IO uint8_t F4R8;
+
+ __IO uint8_t F5R1;
+ __IO uint8_t F5R2;
+ __IO uint8_t F5R3;
+ __IO uint8_t F5R4;
+ __IO uint8_t F5R5;
+ __IO uint8_t F5R6;
+ __IO uint8_t F5R7;
+ __IO uint8_t F5R8;
+ }
+ Filter45;
+
+ struct
+ {
+ __IO uint8_t ESR;
+ __IO uint8_t EIER;
+ __IO uint8_t TECR;
+ __IO uint8_t RECR;
+ __IO uint8_t BTR1;
+ __IO uint8_t BTR2;
+ u8 Reserved1[2];
+ __IO uint8_t FMR1;
+ __IO uint8_t FMR2;
+ __IO uint8_t FCR1;
+ __IO uint8_t FCR2;
+ __IO uint8_t FCR3;
+ u8 Reserved2[3];
+ }
+ Config;
+
+ struct
+ {
+ __IO uint8_t MFMI;
+ __IO uint8_t MDLCR;
+ __IO uint8_t MIDR1;
+ __IO uint8_t MIDR2;
+ __IO uint8_t MIDR3;
+ __IO uint8_t MIDR4;
+ __IO uint8_t MDAR1;
+ __IO uint8_t MDAR2;
+ __IO uint8_t MDAR3;
+ __IO uint8_t MDAR4;
+ __IO uint8_t MDAR5;
+ __IO uint8_t MDAR6;
+ __IO uint8_t MDAR7;
+ __IO uint8_t MDAR8;
+ __IO uint8_t MTSRL;
+ __IO uint8_t MTSRH;
+ }
+ RxFIFO;
+ }Page;
+} CAN_TypeDef;
+/** @addtogroup CAN_Registers_Bits_Definition
+ * @{
+ */
+/*******************************Common****************************************/
+/* CAN Master Control Register bits */
+#define CAN_MCR_INRQ ((uint8_t)0x01)
+#define CAN_MCR_SLEEP ((uint8_t)0x02)
+#define CAN_MCR_TXFP ((uint8_t)0x04)
+#define CAN_MCR_RFLM ((uint8_t)0x08)
+#define CAN_MCR_NART ((uint8_t)0x10)
+#define CAN_MCR_AWUM ((uint8_t)0x20)
+#define CAN_MCR_ABOM ((uint8_t)0x40)
+#define CAN_MCR_TTCM ((uint8_t)0x80)
+
+/* CAN Master Status Register bits */
+#define CAN_MSR_INAK ((uint8_t)0x01)
+#define CAN_MSR_SLAK ((uint8_t)0x02)
+#define CAN_MSR_ERRI ((uint8_t)0x04)
+#define CAN_MSR_WKUI ((uint8_t)0x08)
+#define CAN_MSR_TX ((uint8_t)0x10)
+#define CAN_MSR_RX ((uint8_t)0x20)
+
+/* CAN Transmit Status Register bits */
+#define CAN_TSR_RQCP0 ((uint8_t)0x01)
+#define CAN_TSR_RQCP1 ((uint8_t)0x02)
+#define CAN_TSR_RQCP2 ((uint8_t)0x04)
+#define CAN_TSR_RQCP012 ((uint8_t)0x07)
+#define CAN_TSR_TXOK0 ((uint8_t)0x10)
+#define CAN_TSR_TXOK1 ((uint8_t)0x20)
+#define CAN_TSR_TXOK2 ((uint8_t)0x40)
+
+#define CAN_TPR_CODE0 ((uint8_t)0x01)
+#define CAN_TPR_TME0 ((uint8_t)0x04)
+#define CAN_TPR_TME1 ((uint8_t)0x08)
+#define CAN_TPR_TME2 ((uint8_t)0x10)
+#define CAN_TPR_LOW0 ((uint8_t)0x20)
+#define CAN_TPR_LOW1 ((uint8_t)0x40)
+#define CAN_TPR_LOW2 ((uint8_t)0x80)
+/* CAN Receive FIFO Register bits */
+#define CAN_RFR_FMP01 ((uint8_t)0x03)
+#define CAN_RFR_FULL ((uint8_t)0x08)
+#define CAN_RFR_FOVR ((uint8_t)0x10)
+#define CAN_RFR_RFOM ((uint8_t)0x20)
+
+/* CAN Interrupt Register bits */
+#define CAN_IER_TMEIE ((uint8_t)0x01)
+#define CAN_IER_FMPIE ((uint8_t)0x02)
+#define CAN_IER_FFIE ((uint8_t)0x04)
+#define CAN_IER_FOVIE ((uint8_t)0x08)
+#define CAN_IER_WKUIE ((uint8_t)0x80)
+
+
+/* CAN diagnostic Register bits */
+#define CAN_DGR_LBKM ((uint8_t)0x01)
+#define CAN_DGR_SLIM ((uint8_t)0x02)
+#define CAN_DGR_SAMP ((uint8_t)0x04)
+#define CAN_DGR_RX ((uint8_t)0x08)
+#define CAN_DGR_TXM2E ((uint8_t)0x10)
+
+
+/* CAN page select Register bits */
+#define CAN_PSR_PS0 ((uint8_t)0x01)
+#define CAN_PSR_PS1 ((uint8_t)0x02)
+#define CAN_PSR_PS2 ((uint8_t)0x04)
+
+/*********************Tx MailBox & Fifo Page common bits***********************/
+#define CAN_MCSR_TXRQ ((uint8_t)0x01)
+#define CAN_MCSR_ABRQ ((uint8_t)0x02)
+#define CAN_MCSR_RQCP ((uint8_t)0x04)
+#define CAN_MCSR_TXOK ((uint8_t)0x08)
+#define CAN_MCSR_ALST ((uint8_t)0x10)
+#define CAN_MCSR_TERR ((uint8_t)0x20)
+
+#define CAN_MDLCR_DLC ((uint8_t)0x0F)
+#define CAN_MDLCR_TGT ((uint8_t)0x80)
+
+#define CAN_MIDR1_RTR ((uint8_t)0x20)
+#define CAN_MIDR1_IDE ((uint8_t)0x40)
+
+
+/*************************Filter Page******************************************/
+
+/* CAN Error Status Register bits */
+#define CAN_ESR_EWGF ((uint8_t)0x01)
+#define CAN_ESR_EPVF ((uint8_t)0x02)
+#define CAN_ESR_BOFF ((uint8_t)0x04)
+#define CAN_ESR_LEC0 ((uint8_t)0x10)
+#define CAN_ESR_LEC1 ((uint8_t)0x20)
+#define CAN_ESR_LEC2 ((uint8_t)0x40)
+#define CAN_ESR_LEC ((uint8_t)0x70)
+
+/* CAN Error Status Register bits */
+#define CAN_EIER_EWGIE ((uint8_t)0x01)
+#define CAN_EIER_EPVIE ((uint8_t)0x02)
+#define CAN_EIER_BOFIE ((uint8_t)0x04)
+#define CAN_EIER_LECIE ((uint8_t)0x10)
+#define CAN_EIER_ERRIE ((uint8_t)0x80)
+
+/* CAN transmit error counter Register bits(CAN_TECR) */
+#define CAN_TECR_TEC0 ((uint8_t)0x01)
+#define CAN_TECR_TEC1 ((uint8_t)0x02)
+#define CAN_TECR_TEC2 ((uint8_t)0x04)
+#define CAN_TECR_TEC3 ((uint8_t)0x08)
+#define CAN_TECR_TEC4 ((uint8_t)0x10)
+#define CAN_TECR_TEC5 ((uint8_t)0x20)
+#define CAN_TECR_TEC6 ((uint8_t)0x40)
+#define CAN_TECR_TEC7 ((uint8_t)0x80)
+
+/* CAN RECEIVE error counter Register bits(CAN_TECR) */
+#define CAN_RECR_REC0 ((uint8_t)0x01)
+#define CAN_RECR_REC1 ((uint8_t)0x02)
+#define CAN_RECR_REC2 ((uint8_t)0x04)
+#define CAN_RECR_REC3 ((uint8_t)0x08)
+#define CAN_RECR_REC4 ((uint8_t)0x10)
+#define CAN_RECR_REC5 ((uint8_t)0x20)
+#define CAN_RECR_REC6 ((uint8_t)0x40)
+#define CAN_RECR_REC7 ((uint8_t)0x80)
+
+/* CAN filter mode register bits (CAN_FMR) */
+#define CAN_FMR1_FML0 ((uint8_t)0x01)
+#define CAN_FMR1_FMH0 ((uint8_t)0x02)
+#define CAN_FMR1_FML1 ((uint8_t)0x04)
+#define CAN_FMR1_FMH1 ((uint8_t)0x08)
+#define CAN_FMR1_FML2 ((uint8_t)0x10)
+#define CAN_FMR1_FMH2 ((uint8_t)0x20)
+#define CAN_FMR1_FML3 ((uint8_t)0x40)
+#define CAN_FMR1_FMH3 ((uint8_t)0x80)
+
+#define CAN_FMR2_FML4 ((uint8_t)0x01)
+#define CAN_FMR2_FMH4 ((uint8_t)0x02)
+#define CAN_FMR2_FML5 ((uint8_t)0x04)
+#define CAN_FMR2_FMH5 ((uint8_t)0x08)
+
+/* CAN filter Config register bits (CAN_FCR) */
+#define CAN_FCR1_FACT0 ((uint8_t)0x01)
+#define CAN_FCR1_FACT1 ((uint8_t)0x10)
+#define CAN_FCR2_FACT2 ((uint8_t)0x01)
+#define CAN_FCR2_FACT3 ((uint8_t)0x10)
+#define CAN_FCR3_FACT4 ((uint8_t)0x01)
+#define CAN_FCR3_FACT5 ((uint8_t)0x10)
+
+#define CAN_FCR1_FSC00 ((uint8_t)0x02)
+#define CAN_FCR1_FSC01 ((uint8_t)0x04)
+#define CAN_FCR1_FSC10 ((uint8_t)0x20)
+#define CAN_FCR1_FSC11 ((uint8_t)0x40)
+#define CAN_FCR2_FSC20 ((uint8_t)0x02)
+#define CAN_FCR2_FSC21 ((uint8_t)0x04)
+#define CAN_FCR2_FSC30 ((uint8_t)0x20)
+#define CAN_FCR2_FSC31 ((uint8_t)0x40)
+#define CAN_FCR3_FSC40 ((uint8_t)0x02)
+#define CAN_FCR3_FSC41 ((uint8_t)0x04)
+#define CAN_FCR3_FSC50 ((uint8_t)0x20)
+#define CAN_FCR3_FSC51 ((uint8_t)0x40)
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Registers_Reset_Value
+ * @{
+ */
+
+#define CAN_MCR_RESET_VALUE ((uint8_t)0x02)
+#define CAN_MSR_RESET_VALUE ((uint8_t)0x02)
+#define CAN_TSR_RESET_VALUE ((uint8_t)0x00)
+#define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
+#define CAN_RFR_RESET_VALUE ((uint8_t)0x00)
+#define CAN_IER_RESET_VALUE ((uint8_t)0x00)
+#define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
+#define CAN_PSR_RESET_VALUE ((uint8_t)0x00)
+
+#define CAN_ESR_RESET_VALUE ((uint8_t)0x00)
+#define CAN_EIER_RESET_VALUE ((uint8_t)0x00)
+#define CAN_TECR_RESET_VALUE ((uint8_t)0x00)
+#define CAN_RECR_RESET_VALUE ((uint8_t)0x00)
+#define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
+#define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
+#define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
+#define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
+#define CAN_FCR_RESET_VALUE ((uint8_t)0x00)
+
+#define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
+#define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
+#define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Configuration Registers (CFG)
+ */
+
+ typedef volatile struct CFG_struct
+{
+ __IO uint8_t GCR; /*!< Global Configuration register */
+}
+CFG_TypeDef;
+
+/** @addtogroup CFG_Registers_Reset_Value
+ * @{
+ */
+
+#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CFG_Registers_Bits_Definition
+ * @{
+ */
+
+#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
+#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* Peripherals Base Address */
+/******************************************************************************/
+
+/** @addtogroup MAP_FILE_Base_Addresses
+ * @{
+ */
+#define OPT_BaseAddress 0x4800
+#define GPIOA_BaseAddress 0x5000
+#define GPIOB_BaseAddress 0x5005
+#define GPIOC_BaseAddress 0x500A
+#define GPIOD_BaseAddress 0x500F
+#define GPIOE_BaseAddress 0x5014
+#define GPIOF_BaseAddress 0x5019
+#define GPIOG_BaseAddress 0x501E
+#define GPIOH_BaseAddress 0x5023
+#define GPIOI_BaseAddress 0x5028
+#define FLASH_BaseAddress 0x505A
+#define EXTI_BaseAddress 0x50A0
+#define RST_BaseAddress 0x50B3
+#define CLK_BaseAddress 0x50C0
+#define WWDG_BaseAddress 0x50D1
+#define IWDG_BaseAddress 0x50E0
+#define AWU_BaseAddress 0x50F0
+#define BEEP_BaseAddress 0x50F3
+#define SPI_BaseAddress 0x5200
+#define I2C_BaseAddress 0x5210
+#define UART1_BaseAddress 0x5230
+#define UART2_BaseAddress 0x5240
+#define UART3_BaseAddress 0x5240
+#define TIM1_BaseAddress 0x5250
+#define TIM2_BaseAddress 0x5300
+#define TIM3_BaseAddress 0x5320
+#define TIM4_BaseAddress 0x5340
+#define TIM5_BaseAddress 0x5300
+#define TIM6_BaseAddress 0x5340
+#define ADC1_BaseAddress 0x53E0
+#define ADC2_BaseAddress 0x5400
+#define CAN_BaseAddress 0x5420
+#define CFG_BaseAddress 0x7F60
+#define ITC_BaseAddress 0x7F70
+#define DM_BaseAddress 0x7F90
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* Peripherals declarations */
+/******************************************************************************/
+
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
+ defined(STM8S903) || defined(STM8AF626x)
+ #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */
+
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax)
+#define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */
+
+#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
+
+#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
+
+#if defined (STM8S208) || defined (STM8AF52Ax)
+ #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
+#endif /* (STM8S208) || (STM8AF52Ax) */
+
+#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
+
+#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
+
+#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
+
+#define OPT ((OPT_TypeDef *) OPT_BaseAddress)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
+
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
+
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
+
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
+
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
+
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
+
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */
+
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax)
+ #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
+ #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
+
+#define RST ((RST_TypeDef *) RST_BaseAddress)
+
+#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
+#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
+
+#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
+#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
+
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
+ defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
+ #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */
+
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)
+ #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
+#endif /* STM8S105 || STM8S005 || STM8AF626x */
+
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax)
+ #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
+
+#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
+
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax) || defined (STM8AF626x)
+ #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
+
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
+ #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/
+
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \
+ defined (STM8AF62Ax) || defined (STM8AF626x)
+ #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
+
+#ifdef STM8S903
+ #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
+ #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
+#endif /* STM8S903 */
+
+#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
+
+#define CFG ((CFG_TypeDef *) CFG_BaseAddress)
+
+#define DM ((DM_TypeDef *) DM_BaseAddress)
+
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm8s_conf.h"
+#endif
+
+/* Exported macro --------------------------------------------------------------*/
+
+/*============================== Interrupts ====================================*/
+#ifdef _RAISONANCE_
+ #include <intrins.h>
+ #define enableInterrupts() _rim_() /* enable interrupts */
+ #define disableInterrupts() _sim_() /* disable interrupts */
+ #define rim() _rim_() /* enable interrupts */
+ #define sim() _sim_() /* disable interrupts */
+ #define nop() _nop_() /* No Operation */
+ #define trap() _trap_() /* Trap (soft IT) */
+ #define wfi() _wfi_() /* Wait For Interrupt */
+ #define halt() _halt_() /* Halt */
+#elif defined(_COSMIC_)
+ #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
+ #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */
+ #define rim() {_asm("rim\n");} /* enable interrupts */
+ #define sim() {_asm("sim\n");} /* disable interrupts */
+ #define nop() {_asm("nop\n");} /* No Operation */
+ #define trap() {_asm("trap\n");} /* Trap (soft IT) */
+ #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */
+ #define halt() {_asm("halt\n");} /* Halt */
+#elif defined(_SDCC_)
+ #define enableInterrupts() {__asm__("rim\n");} /* enable interrupts */
+ #define disableInterrupts() {__asm__("sim\n");} /* disable interrupts */
+ #define rim() {__asm__("rim\n");} /* enable interrupts */
+ #define sim() {__asm__("sim\n");} /* disable interrupts */
+ #define nop() {__asm__("nop\n");} /* No Operation */
+ #define trap() {__asm__("trap\n");} /* Trap (soft IT) */
+ #define wfi() {__asm__("wfi\n");} /* Wait For Interrupt */
+ #define halt() {__asm__("halt\n");} /* Halt */
+#else /*_IAR_*/
+ #include <intrinsics.h>
+ #define enableInterrupts() __enable_interrupt() /* enable interrupts */
+ #define disableInterrupts() __disable_interrupt() /* disable interrupts */
+ #define rim() __enable_interrupt() /* enable interrupts */
+ #define sim() __disable_interrupt() /* disable interrupts */
+ #define nop() __no_operation() /* No Operation */
+ #define trap() __trap() /* Trap (soft IT) */
+ #define wfi() __wait_for_interrupt() /* Wait For Interrupt */
+ #define halt() __halt() /* Halt */
+#endif /*_RAISONANCE_*/
+
+/*============================== Interrupt vector Handling ========================*/
+
+#ifdef _COSMIC_
+ #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
+ #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
+#endif /* _COSMIC_ */
+
+#ifdef _RAISONANCE_
+ #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
+ #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
+#endif /* _RAISONANCE_ */
+
+#ifdef _IAR_
+ #define STRINGVECTOR(x) #x
+ #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
+ #define INTERRUPT_HANDLER( a, b ) \
+ _Pragma( VECTOR_ID( (b)+2 ) ) \
+ __interrupt void (a)( void )
+ #define INTERRUPT_HANDLER_TRAP(a) \
+ _Pragma( VECTOR_ID( 1 ) ) \
+ __interrupt void (a) (void)
+#endif /* _IAR_ */
+
+/*============================== Interrupt Handler declaration ========================*/
+#ifdef _COSMIC_
+ #define INTERRUPT @far @interrupt
+#elif defined(_IAR_)
+ #define INTERRUPT __interrupt
+#endif /* _COSMIC_ */
+
+/*============================== Handling bits ====================================*/
+/*-----------------------------------------------------------------------------
+Method : I
+Description : Handle the bit from the character variables.
+Comments : The different parameters of commands are
+ - VAR : Name of the character variable where the bit is located.
+ - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
+ - Value : Can be 0 (reset bit) or not 0 (set bit)
+ The "MskBit" command allows to select some bits in a source
+ variables and copy it in a destination var (return the value).
+ The "ValBit" command returns the value of a bit in a char
+ variable: the bit is reset if it returns 0 else the bit is set.
+ This method generates not an optimised code yet.
+-----------------------------------------------------------------------------*/
+#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
+#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
+
+#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
+#define AffBit(VAR,Place,Value) ((Value) ? \
+ ((VAR) |= ((uint8_t)1<<(Place))) : \
+ ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
+#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
+
+#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
+
+#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */
+#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */
+#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */
+#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */
+
+/*============================== Assert Macros ====================================*/
+#define IS_STATE_VALUE_OK(SensitivityValue) \
+ (((SensitivityValue) == ENABLE) || \
+ ((SensitivityValue) == DISABLE))
+
+/*-----------------------------------------------------------------------------
+Method : II
+Description : Handle directly the bit.
+Comments : The idea is to handle directly with the bit name. For that, it is
+ necessary to have RAM area descriptions (example: HW register...)
+ and the following command line for each area.
+ This method generates the most optimized code.
+-----------------------------------------------------------------------------*/
+
+#define AREA 0x00 /* The area of bits begins at address 0x10. */
+
+#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
+#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
+#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
+
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM8S_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_adc1.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the prototypes/macros for the ADC1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_ADC1_H\r
+#define __STM8S_ADC1_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup ADC1_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief ADC1 clock prescaler selection\r
+ */\r
+\r
+typedef enum \r
+{\r
+ ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, /**< Prescaler selection fADC1 = fcpu/2 */\r
+ ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, /**< Prescaler selection fADC1 = fcpu/3 */\r
+ ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, /**< Prescaler selection fADC1 = fcpu/4 */\r
+ ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30, /**< Prescaler selection fADC1 = fcpu/6 */\r
+ ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, /**< Prescaler selection fADC1 = fcpu/8 */\r
+ ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC1 = fcpu/10 */\r
+ ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC1 = fcpu/12 */\r
+ ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70 /**< Prescaler selection fADC1 = fcpu/18 */\r
+} ADC1_PresSel_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 External conversion trigger event selection\r
+ */\r
+typedef enum \r
+{\r
+ ADC1_EXTTRIG_TIM = (uint8_t)0x00, /**< Conversion from Internal TIM1 TRGO event */\r
+ ADC1_EXTTRIG_GPIO = (uint8_t)0x10 /**< Conversion from External interrupt on ADC_ETR pin*/\r
+} ADC1_ExtTrig_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 data alignment\r
+ */\r
+typedef enum \r
+{\r
+ ADC1_ALIGN_LEFT = (uint8_t)0x00, /**< Data alignment left */\r
+ ADC1_ALIGN_RIGHT = (uint8_t)0x08 /**< Data alignment right */\r
+} ADC1_Align_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 Interrupt source\r
+ */\r
+typedef enum \r
+{\r
+ ADC1_IT_AWDIE = (uint16_t)0x010, /**< Analog WDG interrupt enable */\r
+ ADC1_IT_EOCIE = (uint16_t)0x020, /**< EOC interrupt enable */\r
+ ADC1_IT_AWD = (uint16_t)0x140, /**< Analog WDG status */\r
+ ADC1_IT_AWS0 = (uint16_t)0x110, /**< Analog channel 0 status */\r
+ ADC1_IT_AWS1 = (uint16_t)0x111, /**< Analog channel 1 status */\r
+ ADC1_IT_AWS2 = (uint16_t)0x112, /**< Analog channel 2 status */\r
+ ADC1_IT_AWS3 = (uint16_t)0x113, /**< Analog channel 3 status */\r
+ ADC1_IT_AWS4 = (uint16_t)0x114, /**< Analog channel 4 status */\r
+ ADC1_IT_AWS5 = (uint16_t)0x115, /**< Analog channel 5 status */\r
+ ADC1_IT_AWS6 = (uint16_t)0x116, /**< Analog channel 6 status */\r
+ ADC1_IT_AWS7 = (uint16_t)0x117, /**< Analog channel 7 status */\r
+ ADC1_IT_AWS8 = (uint16_t)0x118, /**< Analog channel 8 status */\r
+ ADC1_IT_AWS9 = (uint16_t)0x119, /**< Analog channel 9 status */\r
+ ADC1_IT_AWS12 = (uint16_t)0x11C, /**< Analog channel 12 status */\r
+ /* refer to product datasheet for channel 12 availability */\r
+ ADC1_IT_EOC = (uint16_t)0x080 /**< EOC pending bit */\r
+\r
+} ADC1_IT_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 Flags\r
+ */\r
+typedef enum \r
+{\r
+ ADC1_FLAG_OVR = (uint8_t)0x41, /**< Overrun status flag */\r
+ ADC1_FLAG_AWD = (uint8_t)0x40, /**< Analog WDG status */\r
+ ADC1_FLAG_AWS0 = (uint8_t)0x10, /**< Analog channel 0 status */\r
+ ADC1_FLAG_AWS1 = (uint8_t)0x11, /**< Analog channel 1 status */\r
+ ADC1_FLAG_AWS2 = (uint8_t)0x12, /**< Analog channel 2 status */\r
+ ADC1_FLAG_AWS3 = (uint8_t)0x13, /**< Analog channel 3 status */\r
+ ADC1_FLAG_AWS4 = (uint8_t)0x14, /**< Analog channel 4 status */\r
+ ADC1_FLAG_AWS5 = (uint8_t)0x15, /**< Analog channel 5 status */\r
+ ADC1_FLAG_AWS6 = (uint8_t)0x16, /**< Analog channel 6 status */\r
+ ADC1_FLAG_AWS7 = (uint8_t)0x17, /**< Analog channel 7 status */\r
+ ADC1_FLAG_AWS8 = (uint8_t)0x18, /**< Analog channel 8 status*/\r
+ ADC1_FLAG_AWS9 = (uint8_t)0x19, /**< Analog channel 9 status */\r
+ ADC1_FLAG_AWS12 = (uint8_t)0x1C, /**< Analog channel 12 status */\r
+ /* refer to product datasheet for channel 12 availability */\r
+ ADC1_FLAG_EOC = (uint8_t)0x80 /**< EOC falg */\r
+}ADC1_Flag_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief ADC1 schmitt Trigger\r
+ */\r
+typedef enum \r
+{\r
+ ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */\r
+ ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */\r
+ ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */\r
+ ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */\r
+ ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */\r
+ ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */\r
+ ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */\r
+ ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */\r
+ ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */\r
+ ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */\r
+ ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */ \r
+ /* refer to product datasheet for channel 12 availability */ \r
+ ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF /**< Schmitt trigger disable on All channels */ \r
+} ADC1_SchmittTrigg_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 conversion mode selection\r
+ */\r
+\r
+typedef enum \r
+{\r
+ ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, /**< Single conversion mode */\r
+ ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 /**< Continuous conversion mode */\r
+} ADC1_ConvMode_TypeDef;\r
+\r
+/**\r
+ * @brief ADC1 analog channel selection\r
+ */\r
+\r
+typedef enum \r
+{\r
+ ADC1_CHANNEL_0 = (uint8_t)0x00, /**< Analog channel 0 */\r
+ ADC1_CHANNEL_1 = (uint8_t)0x01, /**< Analog channel 1 */\r
+ ADC1_CHANNEL_2 = (uint8_t)0x02, /**< Analog channel 2 */\r
+ ADC1_CHANNEL_3 = (uint8_t)0x03, /**< Analog channel 3 */\r
+ ADC1_CHANNEL_4 = (uint8_t)0x04, /**< Analog channel 4 */\r
+ ADC1_CHANNEL_5 = (uint8_t)0x05, /**< Analog channel 5 */\r
+ ADC1_CHANNEL_6 = (uint8_t)0x06, /**< Analog channel 6 */\r
+ ADC1_CHANNEL_7 = (uint8_t)0x07, /**< Analog channel 7 */\r
+ ADC1_CHANNEL_8 = (uint8_t)0x08, /**< Analog channel 8 */\r
+ ADC1_CHANNEL_9 = (uint8_t)0x09, /**< Analog channel 9 */\r
+ ADC1_CHANNEL_12 = (uint8_t)0x0C /**< Analog channel 12 */ \r
+ /* refer to product datasheet for channel 12 availability */\r
+} ADC1_Channel_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup ADC1_Private_Macros\r
+ * @brief Macros used by the assert function to check the different functions parameters.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different prescaler's values.\r
+ */\r
+#define IS_ADC1_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \\r
+ ((PRESCALER) == ADC1_PRESSEL_FCPU_D18))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different external trigger values.\r
+ */\r
+#define IS_ADC1_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC1_EXTTRIG_TIM) || \\r
+ ((EXTRIG) == ADC1_EXTTRIG_GPIO))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different alignment modes.\r
+ */\r
+#define IS_ADC1_ALIGN_OK(ALIGN) (((ALIGN) == ADC1_ALIGN_LEFT) || \\r
+ ((ALIGN) == ADC1_ALIGN_RIGHT))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the Interrupt source.\r
+ */\r
+#define IS_ADC1_IT_OK(IT) (((IT) == ADC1_IT_EOCIE) || \\r
+ ((IT) == ADC1_IT_AWDIE))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the ADC1 Flag.\r
+ */\r
+#define IS_ADC1_FLAG_OK(FLAG) (((FLAG) == ADC1_FLAG_EOC)|| \\r
+ ((FLAG) == ADC1_FLAG_OVR) || \\r
+ ((FLAG) == ADC1_FLAG_AWD) || \\r
+ ((FLAG) == ADC1_FLAG_AWS0) || \\r
+ ((FLAG) == ADC1_FLAG_AWS1) || \\r
+ ((FLAG) == ADC1_FLAG_AWS2) || \\r
+ ((FLAG) == ADC1_FLAG_AWS3) || \\r
+ ((FLAG) == ADC1_FLAG_AWS4) || \\r
+ ((FLAG) == ADC1_FLAG_AWS5) || \\r
+ ((FLAG) == ADC1_FLAG_AWS6) || \\r
+ ((FLAG) == ADC1_FLAG_AWS7) || \\r
+ ((FLAG) == ADC1_FLAG_AWS8) || \\r
+ ((FLAG) == ADC1_FLAG_AWS9))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the ADC1 pending bits.\r
+ */\r
+#define IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT) (((ITPENDINGBIT) == ADC1_IT_EOC) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWD) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS0) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS1) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS2) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS3) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS4) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS5) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS6) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS7) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS8) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS12) || \\r
+ ((ITPENDINGBIT) == ADC1_IT_AWS9))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different schmitt trigger values.\r
+ */\r
+#define IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \\r
+ ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different conversion modes.\r
+ */\r
+#define IS_ADC1_CONVERSIONMODE_OK(MODE) (((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \\r
+ ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different channels values.\r
+ */\r
+#define IS_ADC1_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC1_CHANNEL_0) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_1) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_2) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_3) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_4) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_5) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_6) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_7) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_8) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_12) || \\r
+ ((CHANNEL) == ADC1_CHANNEL_9))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the possible buffer values.\r
+ */\r
+#define IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup ADC1_Exported_Functions\r
+ * @{\r
+ */\r
+void ADC1_DeInit(void);\r
+void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode, \r
+ ADC1_Channel_TypeDef ADC1_Channel,\r
+ ADC1_PresSel_TypeDef ADC1_PrescalerSelection, \r
+ ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, \r
+ FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, \r
+ ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, \r
+ FunctionalState ADC1_SchmittTriggerState);\r
+void ADC1_Cmd(FunctionalState NewState);\r
+void ADC1_ScanModeCmd(FunctionalState NewState);\r
+void ADC1_DataBufferCmd(FunctionalState NewState);\r
+void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState);\r
+void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler);\r
+void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel,\r
+ FunctionalState NewState);\r
+void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode, \r
+ ADC1_Channel_TypeDef ADC1_Channel, \r
+ ADC1_Align_TypeDef ADC1_Align);\r
+void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState);\r
+void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState);\r
+void ADC1_StartConversion(void);\r
+uint16_t ADC1_GetConversionValue(void);\r
+void ADC1_SetHighThreshold(uint16_t Threshold);\r
+void ADC1_SetLowThreshold(uint16_t Threshold);\r
+uint16_t ADC1_GetBufferValue(uint8_t Buffer);\r
+FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel);\r
+FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag);\r
+void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag);\r
+ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit);\r
+void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_ADC1_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_adc2.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the prototypes/macros for the ADC2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_ADC2_H\r
+#define __STM8S_ADC2_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup ADC2_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief ADC2 clock prescaler selection\r
+ */\r
+\r
+typedef enum {\r
+ ADC2_PRESSEL_FCPU_D2 = (uint8_t)0x00, /**< Prescaler selection fADC2 = fcpu/2 */\r
+ ADC2_PRESSEL_FCPU_D3 = (uint8_t)0x10, /**< Prescaler selection fADC2 = fcpu/3 */\r
+ ADC2_PRESSEL_FCPU_D4 = (uint8_t)0x20, /**< Prescaler selection fADC2 = fcpu/4 */\r
+ ADC2_PRESSEL_FCPU_D6 = (uint8_t)0x30, /**< Prescaler selection fADC2 = fcpu/6 */\r
+ ADC2_PRESSEL_FCPU_D8 = (uint8_t)0x40, /**< Prescaler selection fADC2 = fcpu/8 */\r
+ ADC2_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC2 = fcpu/10 */\r
+ ADC2_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC2 = fcpu/12 */\r
+ ADC2_PRESSEL_FCPU_D18 = (uint8_t)0x70 /**< Prescaler selection fADC2 = fcpu/18 */\r
+} ADC2_PresSel_TypeDef;\r
+\r
+/**\r
+ * @brief ADC2 External conversion trigger event selection\r
+ */\r
+typedef enum {\r
+ ADC2_EXTTRIG_TIM = (uint8_t)0x00, /**< Conversion from Internal TIM TRGO event */\r
+ ADC2_EXTTRIG_GPIO = (uint8_t)0x01 /**< Conversion from External interrupt on ADC_ETR pin*/\r
+} ADC2_ExtTrig_TypeDef;\r
+\r
+/**\r
+ * @brief ADC2 data alignment\r
+ */\r
+typedef enum {\r
+ ADC2_ALIGN_LEFT = (uint8_t)0x00, /**< Data alignment left */\r
+ ADC2_ALIGN_RIGHT = (uint8_t)0x08 /**< Data alignment right */\r
+} ADC2_Align_TypeDef;\r
+\r
+/**\r
+ * @brief ADC2 schmitt Trigger\r
+ */\r
+typedef enum {\r
+ ADC2_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */\r
+ ADC2_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */\r
+ ADC2_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */\r
+ ADC2_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */\r
+ ADC2_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */\r
+ ADC2_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */\r
+ ADC2_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */\r
+ ADC2_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */\r
+ ADC2_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */\r
+ ADC2_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */\r
+ ADC2_SCHMITTTRIG_CHANNEL10 = (uint8_t)0x0A, /**< Schmitt trigger disable on AIN10 */\r
+ ADC2_SCHMITTTRIG_CHANNEL11 = (uint8_t)0x0B, /**< Schmitt trigger disable on AIN11 */\r
+ ADC2_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */\r
+ ADC2_SCHMITTTRIG_CHANNEL13 = (uint8_t)0x0D, /**< Schmitt trigger disable on AIN13 */\r
+ ADC2_SCHMITTTRIG_CHANNEL14 = (uint8_t)0x0E, /**< Schmitt trigger disable on AIN14 */\r
+ ADC2_SCHMITTTRIG_CHANNEL15 = (uint8_t)0x0F, /**< Schmitt trigger disable on AIN15 */\r
+ ADC2_SCHMITTTRIG_ALL = (uint8_t)0x1F /**< Schmitt trigger disable on all channels */\r
+\r
+} ADC2_SchmittTrigg_TypeDef;\r
+\r
+/**\r
+ * @brief ADC2 conversion mode selection\r
+ */\r
+\r
+typedef enum {\r
+ ADC2_CONVERSIONMODE_SINGLE = (uint8_t)0x00, /**< Single conversion mode */\r
+ ADC2_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 /**< Continuous conversion mode */\r
+} ADC2_ConvMode_TypeDef;\r
+\r
+/**\r
+ * @brief ADC2 analog channel selection\r
+ */\r
+\r
+typedef enum {\r
+ ADC2_CHANNEL_0 = (uint8_t)0x00, /**< Analog channel 0 */\r
+ ADC2_CHANNEL_1 = (uint8_t)0x01, /**< Analog channel 1 */\r
+ ADC2_CHANNEL_2 = (uint8_t)0x02, /**< Analog channel 2 */\r
+ ADC2_CHANNEL_3 = (uint8_t)0x03, /**< Analog channel 3 */\r
+ ADC2_CHANNEL_4 = (uint8_t)0x04, /**< Analog channel 4 */\r
+ ADC2_CHANNEL_5 = (uint8_t)0x05, /**< Analog channel 5 */\r
+ ADC2_CHANNEL_6 = (uint8_t)0x06, /**< Analog channel 6 */\r
+ ADC2_CHANNEL_7 = (uint8_t)0x07, /**< Analog channel 7 */\r
+ ADC2_CHANNEL_8 = (uint8_t)0x08, /**< Analog channel 8 */\r
+ ADC2_CHANNEL_9 = (uint8_t)0x09, /**< Analog channel 9 */\r
+ ADC2_CHANNEL_10 = (uint8_t)0x0A, /**< Analog channel 10 */\r
+ ADC2_CHANNEL_11 = (uint8_t)0x0B, /**< Analog channel 11 */\r
+ ADC2_CHANNEL_12 = (uint8_t)0x0C, /**< Analog channel 12 */\r
+ ADC2_CHANNEL_13 = (uint8_t)0x0D, /**< Analog channel 13 */\r
+ ADC2_CHANNEL_14 = (uint8_t)0x0E, /**< Analog channel 14 */\r
+ ADC2_CHANNEL_15 = (uint8_t)0x0F /**< Analog channel 15 */\r
+} ADC2_Channel_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup ADC2_Private_Macros\r
+ * @brief Macros used by the assert function to check the different functions parameters.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different prescaler's values.\r
+ */\r
+#define IS_ADC2_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC2_PRESSEL_FCPU_D2) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D3) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D4) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D6) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D8) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D10) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D12) || \\r
+ ((PRESCALER) == ADC2_PRESSEL_FCPU_D18))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different external trigger values.\r
+ */\r
+#define IS_ADC2_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC2_EXTTRIG_TIM) || \\r
+ ((EXTRIG) == ADC2_EXTTRIG_GPIO))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different alignement modes.\r
+ */\r
+#define IS_ADC2_ALIGN_OK(ALIGN) (((ALIGN) == ADC2_ALIGN_LEFT) || \\r
+ ((ALIGN) == ADC2_ALIGN_RIGHT))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different schmitt trigger values.\r
+ */\r
+#define IS_ADC2_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL0) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL1) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL2) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL3) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL4) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL5) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL6) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL7) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL8) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL9) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL10) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL11) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL12) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL13) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL14) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_CHANNEL15) || \\r
+ ((SCHMITTTRIG) == ADC2_SCHMITTTRIG_ALL))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different conversion modes.\r
+ */\r
+#define IS_ADC2_CONVERSIONMODE_OK(MODE) (((MODE) == ADC2_CONVERSIONMODE_SINGLE) || \\r
+ ((MODE) == ADC2_CONVERSIONMODE_CONTINUOUS))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different channels values.\r
+ */\r
+#define IS_ADC2_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC2_CHANNEL_0) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_1) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_2) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_3) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_4) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_5) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_6) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_7) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_8) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_9) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_10) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_11) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_12) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_13) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_14) || \\r
+ ((CHANNEL) == ADC2_CHANNEL_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup ADC2_Exported_Functions\r
+ * @{\r
+ */\r
+void ADC2_DeInit(void);\r
+void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode, \r
+ ADC2_Channel_TypeDef ADC2_Channel, \r
+ ADC2_PresSel_TypeDef ADC2_PrescalerSelection, \r
+ ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, \r
+ FunctionalState ADC2_ExtTriggerState, \r
+ ADC2_Align_TypeDef ADC2_Align, \r
+ ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, \r
+ FunctionalState ADC2_SchmittTriggerState);\r
+void ADC2_Cmd(FunctionalState NewState);\r
+void ADC2_ITConfig(FunctionalState NewState);\r
+void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler);\r
+void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, \r
+ FunctionalState NewState);\r
+void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode, \r
+ ADC2_Channel_TypeDef ADC2_Channel, \r
+ ADC2_Align_TypeDef ADC2_Align);\r
+void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState);\r
+void ADC2_StartConversion(void);\r
+uint16_t ADC2_GetConversionValue(void);\r
+FlagStatus ADC2_GetFlagStatus(void);\r
+void ADC2_ClearFlag(void);\r
+ITStatus ADC2_GetITStatus(void);\r
+void ADC2_ClearITPendingBit(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_ADC2_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_awu.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the AWU peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_AWU_H\r
+#define __STM8S_AWU_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup AWU_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief AWU TimeBase selection\r
+ */\r
+\r
+typedef enum\r
+{\r
+ AWU_TIMEBASE_NO_IT = (uint8_t)0, /*!< No AWU interrupt selected */\r
+ AWU_TIMEBASE_250US = (uint8_t)1, /*!< AWU Timebase equals 0.25 ms */\r
+ AWU_TIMEBASE_500US = (uint8_t)2, /*!< AWU Timebase equals 0.5 ms */\r
+ AWU_TIMEBASE_1MS = (uint8_t)3, /*!< AWU Timebase equals 1 ms */\r
+ AWU_TIMEBASE_2MS = (uint8_t)4, /*!< AWU Timebase equals 2 ms */\r
+ AWU_TIMEBASE_4MS = (uint8_t)5, /*!< AWU Timebase equals 4 ms */\r
+ AWU_TIMEBASE_8MS = (uint8_t)6, /*!< AWU Timebase equals 8 ms */\r
+ AWU_TIMEBASE_16MS = (uint8_t)7, /*!< AWU Timebase equals 16 ms */\r
+ AWU_TIMEBASE_32MS = (uint8_t)8, /*!< AWU Timebase equals 32 ms */\r
+ AWU_TIMEBASE_64MS = (uint8_t)9, /*!< AWU Timebase equals 64 ms */\r
+ AWU_TIMEBASE_128MS = (uint8_t)10, /*!< AWU Timebase equals 128 ms */\r
+ AWU_TIMEBASE_256MS = (uint8_t)11, /*!< AWU Timebase equals 256 ms */\r
+ AWU_TIMEBASE_512MS = (uint8_t)12, /*!< AWU Timebase equals 512 ms */\r
+ AWU_TIMEBASE_1S = (uint8_t)13, /*!< AWU Timebase equals 1 s */\r
+ AWU_TIMEBASE_2S = (uint8_t)14, /*!< AWU Timebase equals 2 s */\r
+ AWU_TIMEBASE_12S = (uint8_t)15, /*!< AWU Timebase equals 12 s */\r
+ AWU_TIMEBASE_30S = (uint8_t)16 /*!< AWU Timebase equals 30 s */\r
+} AWU_Timebase_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup AWU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */\r
+#define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup AWU_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the AWU timebases\r
+ */\r
+#define IS_AWU_TIMEBASE_OK(TB) \\r
+ (((TB) == AWU_TIMEBASE_NO_IT) || \\r
+ ((TB) == AWU_TIMEBASE_250US) || \\r
+ ((TB) == AWU_TIMEBASE_500US) || \\r
+ ((TB) == AWU_TIMEBASE_1MS) || \\r
+ ((TB) == AWU_TIMEBASE_2MS) || \\r
+ ((TB) == AWU_TIMEBASE_4MS) || \\r
+ ((TB) == AWU_TIMEBASE_8MS) || \\r
+ ((TB) == AWU_TIMEBASE_16MS) || \\r
+ ((TB) == AWU_TIMEBASE_32MS) || \\r
+ ((TB) == AWU_TIMEBASE_64MS) || \\r
+ ((TB) == AWU_TIMEBASE_128MS) || \\r
+ ((TB) == AWU_TIMEBASE_256MS) || \\r
+ ((TB) == AWU_TIMEBASE_512MS) || \\r
+ ((TB) == AWU_TIMEBASE_1S) || \\r
+ ((TB) == AWU_TIMEBASE_2S) || \\r
+ ((TB) == AWU_TIMEBASE_12S) || \\r
+ ((TB) == AWU_TIMEBASE_30S))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the LSI frequency (in Hz)\r
+ */\r
+#define IS_LSI_FREQUENCY_OK(FREQ) \\r
+ (((FREQ) >= LSI_FREQUENCY_MIN) && \\r
+ ((FREQ) <= LSI_FREQUENCY_MAX))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup AWU_Exported_Functions\r
+ * @{\r
+ */\r
+void AWU_DeInit(void);\r
+void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase);\r
+void AWU_Cmd(FunctionalState NewState);\r
+void AWU_LSICalibrationConfig(uint32_t LSIFreqHz);\r
+void AWU_IdleModeEnable(void);\r
+FlagStatus AWU_GetFlagStatus(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_AWU_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_beep.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the BEEP peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_BEEP_H\r
+#define __STM8S_BEEP_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup BEEP_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief BEEP Frequency selection\r
+ */\r
+typedef enum {\r
+ BEEP_FREQUENCY_1KHZ = (uint8_t)0x00, /*!< Beep signal output frequency equals to 1 KHz */\r
+ BEEP_FREQUENCY_2KHZ = (uint8_t)0x40, /*!< Beep signal output frequency equals to 2 KHz */\r
+ BEEP_FREQUENCY_4KHZ = (uint8_t)0x80 /*!< Beep signal output frequency equals to 4 KHz */\r
+} BEEP_Frequency_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup BEEP_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B) /*!< Default value when calibration is not done */\r
+\r
+#define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */\r
+#define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup BEEP_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the BEEP frequencies.\r
+ */\r
+#define IS_BEEP_FREQUENCY_OK(FREQ) \\r
+ (((FREQ) == BEEP_FREQUENCY_1KHZ) || \\r
+ ((FREQ) == BEEP_FREQUENCY_2KHZ) || \\r
+ ((FREQ) == BEEP_FREQUENCY_4KHZ))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the LSI frequency (in Hz).\r
+ */\r
+#define IS_LSI_FREQUENCY_OK(FREQ) \\r
+ (((FREQ) >= LSI_FREQUENCY_MIN) && \\r
+ ((FREQ) <= LSI_FREQUENCY_MAX))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup BEEP_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void BEEP_DeInit(void);\r
+void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);\r
+void BEEP_Cmd(FunctionalState NewState);\r
+void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_BEEP_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_can.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the CAN peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_CAN_H\r
+#define __STM8S_CAN_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+#define CAN_STDID_SIZE ((uint16_t)0x07FF)\r
+#define CAN_EXTID_SIZE ((uint32_t)0x1FFFFFFF)\r
+#define CAN_DLC_MAX ((uint8_t)0x08)\r
+\r
+\r
+/** @addtogroup CAN_Exported_Types\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief CAN Page Mapping\r
+ */\r
+typedef enum\r
+{\r
+ CAN_Page_TxMailBox0 = ((uint8_t) 0), /*!< CAN TX mailbox 0 reg page */\r
+ CAN_Page_TxMailBox1 = ((uint8_t) 1), /*!< CAN TX mailbox 1 reg page */\r
+ CAN_Page_TxMailBox2 = ((uint8_t) 5), /*!< CAN TX mailbox 2 reg page */\r
+ CAN_Page_Filter01 = ((uint8_t) 2), /*!< CAN Filters 0 & 1 reg page*/\r
+ CAN_Page_Filter23 = ((uint8_t) 3), /*!< CAN Filters 2 & 3 reg page*/\r
+ CAN_Page_Filter45 = ((uint8_t) 4), /*!< CAN Filters 4 & 5 reg page*/\r
+ CAN_Page_Config = ((uint8_t) 6), /*!< CAN Configuration control/status reg page*/\r
+ CAN_Page_RxFifo = ((uint8_t) 7) /*!< CAN RX FIFO registers page */\r
+}CAN_Page_TypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief CAN sleep constants \r
+ */\r
+typedef enum {\r
+ CAN_InitStatus_Failed =0, /*!< CAN initialization failed */\r
+ CAN_InitStatus_Success =! CAN_InitStatus_Failed /*!< CAN initialization OK*/\r
+} CAN_InitStatus_TypeDef;\r
+\r
+ \r
+ /**\r
+ * @brief CAN operating mode */\r
+ typedef enum\r
+{\r
+ CAN_OperatingMode_Initialization =((uint8_t)0x00), /*!< Initialization mode */\r
+ CAN_OperatingMode_Normal =((uint8_t)0x01), /*!< Normal mode */\r
+ CAN_OperatingMode_Sleep =((uint8_t)0x02) /*!< sleep mode */\r
+}CAN_OperatingMode_TypeDef;\r
+\r
+ /**\r
+ * @brief CAN operating mode status */\r
+ typedef enum\r
+{\r
+ CAN_ModeStatus_Failed = ((uint8_t)0x00), /*!< CAN entring the specific mode failed */\r
+ CAN_ModeStatus_Success =! CAN_ModeStatus_Failed /*!< CAN entring the specific mode Succeed */\r
+}CAN_ModeStatus_TypeDef;\r
+\r
+ /**\r
+ * @brief CAN Time Triggered Communication mode \r
+ */\r
+typedef enum\r
+{\r
+ CAN_MasterCtrl_AllDisabled =((uint8_t)0x00), /*!< CAN ALL Master Control Option are DISABLED */\r
+ CAN_MasterCtrl_AllEnabled =((uint8_t)0xFC), /*!< CAN ALL Master Control Option are DISABLED */\r
+ CAN_MasterCtrl_TimeTriggerCOMMode =((uint8_t)0x80), /*!< CAN Time Triggered Communication mode ENABLED */\r
+ CAN_MasterCtrl_AutoBusOffManagement =((uint8_t)0x40), /*!< CAN Auto Bus Off Management ENABLED */\r
+ CAN_MasterCtrl_AutoWakeUpMode =((uint8_t)0x20), /*!< CAN Automatic WakeUp Mode ENABLED , sleep mode is left automatically by hardware */\r
+ CAN_MasterCtrl_NoAutoReTx =((uint8_t)0x10), /*!< CAN Non Automatic Retransmission ENABLED, MSG will be transmitted only once */\r
+ CAN_MasterCtrl_RxFifoLockedMode =((uint8_t)0x08), /*!< CAN Recieve FIFO Locked against overrun ENABLED */\r
+ CAN_MasterCtrl_TxFifoPriority =((uint8_t)0x04) /*!< CAN Transmit FIFO Priority driven by the request order (not by the identifier of the MSG) */\r
+ }CAN_MasterCtrl_TypeDef;\r
+\r
+/**\r
+ * @brief CAN mode options */\r
+typedef enum\r
+{\r
+ CAN_Mode_Normal =((uint8_t)0x00), /*!< normal mode */\r
+ CAN_Mode_LoopBack =((uint8_t)0x01), /*!< loopback mode */\r
+ CAN_Mode_Silent =((uint8_t)0x02), /*!< silent mode */\r
+ CAN_Mode_Silent_LoopBack =((uint8_t)0x03) /*!< loopback combined with silent mode */\r
+}CAN_Mode_TypeDef;\r
+\r
+/**\r
+ * @brief CAN synchronisation jump width (SJW)*/\r
+typedef enum\r
+{\r
+ CAN_SynJumpWidth_1TimeQuantum =((uint8_t)0x00), /*!< 1 time quantum */\r
+ CAN_SynJumpWidth_2TimeQuantum =((uint8_t)0x40), /*!< 2 time quantum */\r
+ CAN_SynJumpWidth_3TimeQuantum =((uint8_t)0x80), /*!< 3 time quantum */\r
+ CAN_SynJumpWidth_4TimeQuantum =((uint8_t)0xC0) /*!< 4 time quantum */\r
+}CAN_SynJumpWidth_TypeDef;\r
+\r
+/**\r
+ * @brief time quantum in bit segment 1 */\r
+typedef enum\r
+{\r
+ CAN_BitSeg1_1TimeQuantum =((uint8_t)0x00), /*!< 1 time quantum */\r
+ CAN_BitSeg1_2TimeQuantum =((uint8_t)0x01), /*!< 2 time quantum */\r
+ CAN_BitSeg1_3TimeQuantum =((uint8_t)0x02), /*!< 3 time quantum */\r
+ CAN_BitSeg1_4TimeQuantum =((uint8_t)0x03) , /*!< 4 time quantum */\r
+ CAN_BitSeg1_5TimeQuantum =((uint8_t)0x04) , /*!< 5 time quantum */\r
+ CAN_BitSeg1_6TimeQuantum =((uint8_t)0x05) , /*!< 6 time quantum */\r
+ CAN_BitSeg1_7TimeQuantum =((uint8_t)0x06) , /*!< 7 time quantum */\r
+ CAN_BitSeg1_8TimeQuantum =((uint8_t)0x07), /*!< 8 time quantum */\r
+ CAN_BitSeg1_9TimeQuantum =((uint8_t)0x08), /*!< 9 time quantum */\r
+ CAN_BitSeg1_10TimeQuantum =((uint8_t)0x09), /*!< 10 time quantum */\r
+ CAN_BitSeg1_11TimeQuantum =((uint8_t)0x0A), /*!< 11 time quantum */\r
+ CAN_BitSeg1_12TimeQuantum =((uint8_t)0x0B), /*!< 12 time quantum */\r
+ CAN_BitSeg1_13TimeQuantum =((uint8_t)0x0C), /*!< 13 time quantum */\r
+ CAN_BitSeg1_14TimeQuantum =((uint8_t)0x0D), /*!< 14 time quantum */\r
+ CAN_BitSeg1_15TimeQuantum =((uint8_t)0x0E), /*!< 15 time quantum */\r
+ CAN_BitSeg1_16TimeQuantum =((uint8_t)0x0F) /*!< 16 time quantum */\r
+}CAN_BitSeg1_TypeDef;\r
+\r
+/**\r
+ * @brief time quantum in bit segment 2 */\r
+typedef enum\r
+{\r
+ CAN_BitSeg2_1TimeQuantum = ((uint8_t)0x00), /*!< 1 time quantum */\r
+ CAN_BitSeg2_2TimeQuantum = ((uint8_t)0x10), /*!< 2 time quantum */\r
+ CAN_BitSeg2_3TimeQuantum = ((uint8_t)0x20), /*!< 3 time quantum */\r
+ CAN_BitSeg2_4TimeQuantum = ((uint8_t)0x30), /*!< 4 time quantum */\r
+ CAN_BitSeg2_5TimeQuantum = ((uint8_t)0x40), /*!< 5 time quantum */\r
+ CAN_BitSeg2_6TimeQuantum = ((uint8_t)0x50), /*!< 6 time quantum */\r
+ CAN_BitSeg2_7TimeQuantum = ((uint8_t)0x60), /*!< 7 time quantum */\r
+ CAN_BitSeg2_8TimeQuantum = ((uint8_t)0x70) /*!< 8 time quantum */\r
+}CAN_BitSeg2_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief CAN filter number */\r
+typedef enum\r
+{ \r
+ CAN_FilterNumber_0 = ((uint8_t)0x00), /*!< Filter number 0 */ \r
+ CAN_FilterNumber_1 = ((uint8_t)0x01), /*!< Filter number 1 */ \r
+ CAN_FilterNumber_2 = ((uint8_t)0x02), /*!< Filter number 2 */\r
+ CAN_FilterNumber_3 = ((uint8_t)0x03), /*!< Filter number 3 */\r
+ CAN_FilterNumber_4 = ((uint8_t)0x04), /*!< Filter number 4 */ \r
+ CAN_FilterNumber_5 = ((uint8_t)0x05) /*!< Filter number 5 */ \r
+}CAN_FilterNumber_TypeDef;\r
+\r
+/**\r
+ * @brief CAN filter mode */\r
+typedef enum\r
+{\r
+ CAN_FilterMode_IdMask = ((uint8_t)0x00), /*!< id/mask mode */\r
+ CAN_FilterMode_IdMask_IdList = ((uint8_t)0x10), /*!< Id/Mask mode First and IdList mode second */\r
+ CAN_FilterMode_IdList_IdMask = ((uint8_t)0x11), /*!< IdList mode First and IdMask mode second */\r
+ CAN_FilterMode_IdList = ((uint8_t)0x01) /*!< identifier list mode */\r
+}CAN_FilterMode_TypeDef;\r
+\r
+/**\r
+ * @brief CAN filter scale */\r
+typedef enum\r
+{\r
+ CAN_FilterScale_8Bit =((uint8_t)0x00), /*!< 8-bit filter scale */\r
+ CAN_FilterScale_16_8Bit =((uint8_t)0x02), /*!< 16/8-bit filter scale */\r
+ CAN_FilterScale_16Bit =((uint8_t)0x04), /*!< 16-bit filter scale */\r
+ CAN_FilterScale_32Bit =((uint8_t)0x06) /*!< 32-bit filter scale */\r
+}CAN_FilterScale_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief CAN Tx mailboxes*/\r
+typedef enum\r
+{\r
+ CAN_TransmitMailBox_0 = ((uint8_t) 0x00), /*!< CAN TX mailbox 0 reg page */\r
+ CAN_TransmitMailBox_1 = ((uint8_t) 0x01), /*!< CAN TX mailbox 1 reg page */\r
+ CAN_TransmitMailBox_2 = ((uint8_t) 0x05) /*!< CAN TX mailbox 2 reg page */\r
+}CAN_TransmitMailBox_TypeDef;\r
+\r
+/**\r
+ * @brief CAN Pending Messages number*/\r
+typedef enum\r
+{\r
+ CAN_NbrPendingMessage_0 = ((uint8_t)0x00), /*!< No Msg Pending */\r
+ CAN_NbrPendingMessage_1 = ((uint8_t)0x01), /*!< 1 Msg Pending */\r
+ CAN_NbrPendingMessage_2 = ((uint8_t)0x02), /*!< 2 Msg Pending */\r
+ CAN_NbrPendingMessage_3 = ((uint8_t)0x03) /*!< 3 Msg Pending */\r
+}CAN_NbrPendingMessage_TypeDef;\r
+\r
+/**\r
+ * @brief CAN identifier type */\r
+typedef enum\r
+{\r
+ CAN_Id_Standard =((uint8_t)0x00), /*!< Standard Id */\r
+ CAN_Id_Extended =((uint8_t)0x40) /*!< Extended Id */\r
+}CAN_Id_TypeDef;\r
+\r
+/**\r
+ * @brief CAN remote transmission request */\r
+typedef enum\r
+{\r
+ CAN_RTR_Data = ((uint8_t)0x00), /*!< Data frame */\r
+ CAN_RTR_Remote = ((uint8_t)0x20) /*!< Remote frame */\r
+}CAN_RTR_TypeDef;\r
+\r
+/**\r
+ * @brief CAN transmit Status */\r
+typedef enum\r
+{\r
+ CAN_TxStatus_Failed =((uint8_t)0xF0), /*!< CAN transmission failed */\r
+ CAN_TxStatus_Ok =((uint8_t)0xF1), /*!< CAN transmission succeeded */\r
+ CAN_TxStatus_Pending =((uint8_t)0xF2), /*!< CAN transmission pending */\r
+ CAN_TxStatus_NoMailBox =((uint8_t)0xF4), /*!< CAN cell did not provide an empty mailbox */\r
+ CAN_TxStatus_MailBoxEmpty =((uint8_t)0xF5), /*!< CAN Tx mailbox is Empty */\r
+ CAN_TxStatus_MailBox0Ok =((uint8_t)0x00), /*!< CAN transmission succeeded by mail box 1*/\r
+ CAN_TxStatus_MailBox1Ok =((uint8_t)0x01), /*!< CAN transmission succeeded by mail box 2*/\r
+ CAN_TxStatus_MailBox2Ok =((uint8_t)0x05) /*!< CAN transmission succeeded by mail box 3*/\r
+}CAN_TxStatus_TypeDef;\r
+\r
+/**\r
+ * @brief CAN sleep Status */\r
+typedef enum\r
+{\r
+ CAN_Sleep_Failed = ((uint8_t)0x00), /*!< CAN did not enter the sleep mode */\r
+ CAN_Sleep_Ok = ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
+}CAN_Sleep_TypeDef;\r
+/**\r
+ * @brief CAN wake up status */\r
+typedef enum\r
+{\r
+ CAN_WakeUp_Failed = ((uint8_t)0x00), /*!< CAN did not leave the sleep mode */\r
+ CAN_WakeUp_Ok = ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
+}CAN_WakeUp_TypeDef;\r
+\r
+/**\r
+ * @brief CAN flags */\r
+typedef enum\r
+{\r
+ /* if the flag is 0x3XXX, it means that it can be got (CAN_GetFlagStatus) and Cleared (CAN_ClearFlag) */\r
+ /* if the flag is 0x1XXX, it means that it can only be got (CAN_GetFlagStatus) */\r
+ /*Transmit Flags*/\r
+ CAN_FLAG_RQCP0 =((uint16_t)0x3401), /*!< Request MailBox0 Flag */\r
+ CAN_FLAG_RQCP1 =((uint16_t)0x3402), /*!< Request MailBox1 Flag */\r
+ CAN_FLAG_RQCP2 =((uint16_t)0x3404), /*!< Request MailBox2 Flag */\r
+ /*Receive Flags*/\r
+ CAN_FLAG_FMP =((uint16_t)0x1203), /*!< FIFO Message Pending Flag */\r
+ CAN_FLAG_FF =((uint16_t)0x3208), /*!< FIFO Full Flag */\r
+ CAN_FLAG_FOV =((uint16_t)0x3210), /*!< FIFO Overrun Flag */\r
+ /*Wake up Flag*/\r
+ CAN_FLAG_WKU =((uint16_t)0x3108), /*!< wake up Flag */\r
+ /*Error Flags*/\r
+ CAN_FLAG_EWG =((uint16_t)0x1001), /*!< Error Warning Flag */\r
+ CAN_FLAG_EPV =((uint16_t)0x1002), /*!< Error Passive Flag */\r
+ CAN_FLAG_BOF =((uint16_t)0x1004), /*!< Bus-Off Flag */\r
+ CAN_FLAG_LEC =((uint16_t)0x3070) /*!< Last error code Flag */\r
+}CAN_FLAG_TypeDef;\r
+\r
+/**\r
+ * @brief CAN interrupts */\r
+typedef enum\r
+{\r
+ /*Transmit Interruption*/\r
+ CAN_IT_TME =((uint16_t)0x0001), /*!< Transmit mailbox empty interrupt */\r
+ /*Receive Interruptions*/\r
+ CAN_IT_FMP =((uint16_t)0x0002), /*!< FIFO message pending interrupt */ \r
+ CAN_IT_FF =((uint16_t)0x0004), /*!< FIFO full interrupt */\r
+ CAN_IT_FOV =((uint16_t)0x0008), /*!< FIFO overrun interrupt */\r
+ /*Wake Up Interruption*/\r
+ CAN_IT_WKU =((uint16_t)0x0080), /*!< Wake-up interrupt */\r
+ /*Error Interruptions*/\r
+ CAN_IT_ERR =((uint16_t)0x4000), /*!< Genaral Error interrupt */\r
+ CAN_IT_EWG =((uint16_t)0x0100), /*!< Error warning interrupt */\r
+ CAN_IT_EPV =((uint16_t)0x0200), /*!< Error passive interrupt */\r
+ CAN_IT_BOF =((uint16_t)0x0400), /*!< Bus-off interrupt */\r
+ CAN_IT_LEC =((uint16_t)0x0800) /*!< Last error code interrupt */\r
+} CAN_IT_TypeDef;\r
+\r
+/**\r
+ * @brief CAN ST7 Compatibility*/\r
+typedef enum\r
+{\r
+ CAN_ST7Compatibility_Enable = ((uint8_t)0x00), /*!< CAN is compatible with ST7 beCAN (only 2 mailboxes are availble)*/\r
+ CAN_ST7Compatibility_Disable = ((uint8_t)0x10) /*!< CAN is not compatible with ST7 beCAN ( 3 mailboxes are availble)*/\r
+}CAN_ST7Compatibility_TypeDef;\r
+\r
+/**\r
+ * @brief CAN Error Code description */\r
+typedef enum\r
+{ \r
+ CAN_ErrorCode_NoErr = ((uint8_t)0x00), /*!< No Error */ \r
+ CAN_ErrorCode_StuffErr = ((uint8_t)0x10), /*!< Stuff Error */ \r
+ CAN_ErrorCode_FormErr = ((uint8_t)0x20), /*!< Form Error */ \r
+ CAN_ErrorCode_ACKErr = ((uint8_t)0x30), /*!< Acknowledgment Error */ \r
+ CAN_ErrorCode_BitRecessiveErr = ((uint8_t)0x40), /*!< Bit Recessive Error */ \r
+ CAN_ErrorCode_BitDominantErr = ((uint8_t)0x50), /*!< Bit Dominant Error */ \r
+ CAN_ErrorCode_CRCErr = ((uint8_t)0x60), /*!< CRC Error */ \r
+ CAN_ErrorCode_SoftwareSetErr = ((uint8_t)0x70) /*!< Software Set Error */ \r
+}CAN_ErrorCode_TypeDef;\r
+/**\r
+ * @}\r
+ */\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup CAN_Private_Macros\r
+ * @{\r
+ */\r
+/**\r
+ * @brief Macro used by the assert function in order to check the CAN ST7 Compatibility parameters.\r
+ */\r
+#define IS_CAN_ST7_COMPATIBILITY_OK(STATE) (((STATE) == CAN_ST7Compatibility_Enable) || ((STATE) == CAN_ST7Compatibility_Disable))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN operating mode.\r
+ */\r
+#define IS_CAN_OPERATINGMODE_OK(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\\r
+ ((MODE) == CAN_OperatingMode_Normal)|| \\r
+ ((MODE) == CAN_OperatingMode_Sleep))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN Time Triggered Communication mode.\r
+ */\r
+#define IS_CAN_MASTERCTRL_OK(MODE) (((MODE) == CAN_MasterCtrl_AllDisabled) || \\r
+ (((MODE) <= CAN_MasterCtrl_AllEnabled) && ((MODE) >= CAN_MasterCtrl_TxFifoPriority)))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN mode options .\r
+ */\r
+#define IS_CAN_MODE_OK(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the CAN synchronisation jump width (SJW).\r
+ */\r
+#define IS_CAN_SYNJUMPWIDTH_OK(SJW) (((SJW) == CAN_SynJumpWidth_1TimeQuantum) || ((SJW) == CAN_SynJumpWidth_2TimeQuantum)|| \\r
+ ((SJW) == CAN_SynJumpWidth_3TimeQuantum) || ((SJW) == CAN_SynJumpWidth_4TimeQuantum))\r
+/**\r
+ * @brief Macro used by the assert function in order to check time quantum in bit segment 1 .\r
+ */\r
+#define IS_CAN_BITSEG1_OK(BS1) ((BS1) <= CAN_BitSeg1_16TimeQuantum)\r
+/**\r
+ * @brief Macro used by the assert function in order to check time quantum in bit segment 2.\r
+ */\r
+#define IS_CAN_BITSEG2_OK(BS2) ((((BS2) >= CAN_BitSeg2_2TimeQuantum) && ((BS2) <= CAN_BitSeg2_8TimeQuantum))|| ((BS2) == CAN_BitSeg2_1TimeQuantum))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN clock prescaler.\r
+ */\r
+#define IS_CAN_PRESCALER_OK(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 64))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN filter number.\r
+ */\r
+#define IS_CAN_FILTER_NUMBER_OK(NUMBER) (((NUMBER) == CAN_FilterNumber_0) || \\r
+ ((NUMBER) == CAN_FilterNumber_1) || \\r
+ ((NUMBER) == CAN_FilterNumber_2) || \\r
+ ((NUMBER) == CAN_FilterNumber_3) || \\r
+ ((NUMBER) == CAN_FilterNumber_4) || \\r
+ ((NUMBER) == CAN_FilterNumber_5))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN filter mode.\r
+ */\r
+#define IS_CAN_FILTER_MODE_OK(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdMask_IdList) || \\r
+ ((MODE) == CAN_FilterMode_IdList_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdList))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN filter scale.\r
+ */\r
+#define IS_CAN_FILTER_SCALE_OK(SCALE) (((SCALE) == CAN_FilterScale_8Bit)|| \\r
+ ((SCALE) == CAN_FilterScale_16_8Bit) ||\\r
+ ((SCALE) == CAN_FilterScale_16Bit )||\\r
+ ((SCALE) == CAN_FilterScale_32Bit))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN Tx mailboxes.\r
+ */\r
+#define IS_CAN_TRANSMITMAILBOX_OK(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TransmitMailBox_0) || \\r
+ ((TRANSMITMAILBOX) == CAN_TransmitMailBox_1) || \\r
+ ((TRANSMITMAILBOX) == CAN_TransmitMailBox_2))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the Standard ID to be sent.\r
+ */\r
+#define IS_CAN_STDID_OK(STDID) ((STDID) <= ((uint16_t)CAN_STDID_SIZE))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the Extended ID to be sent.\r
+ */\r
+#define IS_CAN_EXTID_OK(EXTID) ((EXTID) <= ((uint32_t)CAN_EXTID_SIZE))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the DLC to be sent.\r
+ */\r
+#define IS_CAN_DLC_OK(DLC) ((DLC) <= CAN_DLC_MAX)\r
+/**\r
+ * @brief Macro used by the assert function in order to check the type of the ID to be sent.\r
+ */\r
+#define IS_CAN_IDTYPE_OK(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN transmission Frame Type.\r
+ */\r
+#define IS_CAN_RTR_OK(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN flags which can be got by @ref CAN_GetFlagStatus\r
+ */\r
+#define IS_CAN_FLAG_STATUS_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\\r
+ ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FMP) ||\\r
+ ((FLAG) == CAN_FLAG_FF) || ((FLAG) == CAN_FLAG_FOV) ||\\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_EWG) ||\\r
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_BOF) ||\\r
+ ((FLAG) == CAN_FLAG_LEC))\r
+/**\r
+ * @brief Macro used by the assert function in order to check CAN flags which can be cleared by @ref CAN_ClearFlag\r
+ */\r
+#define IS_CAN_FLAG_CLEAR_OK(FLAG) (((FLAG) == CAN_FLAG_RQCP0) || ((FLAG) == CAN_FLAG_RQCP1) ||\\r
+ ((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_FF) ||\\r
+ ((FLAG) == CAN_FLAG_FOV) || ((FLAG) == CAN_FLAG_WKU) ||\\r
+ ((FLAG) == CAN_FLAG_LEC))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the CAN Configuration interrupts.\r
+ */\r
+#define CAN_IT_CONFIG_MASK ~(uint16_t)(CAN_IT_TME|CAN_IT_FMP|CAN_IT_FF|CAN_IT_FOV|CAN_IT_WKU|CAN_IT_EWG|CAN_IT_EPV|CAN_IT_BOF|CAN_IT_LEC|CAN_IT_ERR)\r
+#define IS_CAN_IT_CONFIG_OK(IT) (((IT) != 0x0000) && ((uint16_t)((uint16_t)(IT) & (uint16_t)CAN_IT_CONFIG_MASK) == 0x0000))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the CAN status interrupts.\r
+ */\r
+#define IS_CAN_IT_STATUS_OK(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP) ||\\r
+ ((IT) == CAN_IT_FF) || ((IT) == CAN_IT_FOV) || \\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_ERR) || \\r
+ ((IT) == CAN_IT_EWG) || ((IT) == CAN_IT_EPV) || \\r
+ ((IT) == CAN_IT_BOF) || ((IT) == CAN_IT_LEC) )\r
+/**\r
+ * @brief Macro used by the assert function in order to check the CAN Pending bit interrupts.\r
+ */\r
+#define IS_CAN_IT_PENDING_BIT_OK(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF) ||\\r
+ ((IT) == CAN_IT_FOV) || ((IT) == CAN_IT_WKU) ||\\r
+ ((IT) == CAN_IT_ERR) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)||\\r
+ ((IT) == CAN_IT_LEC))\r
+/**\r
+ * @brief Macro used by the assert function in order to check the Last Error Code.\r
+ */\r
+#define IS_CAN_LAST_ERROR_CODE_OK(CODE) (((CODE) & 0x8F) == 0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported function protypes ----------------------------------------------- */\r
+/** @addtogroup CAN_Exported_Functions\r
+ * @{\r
+ */\r
+void CAN_DeInit(void);\r
+CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,\r
+ CAN_Mode_TypeDef CAN_Mode,\r
+ CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,\r
+ CAN_BitSeg1_TypeDef CAN_BitSeg1,\r
+ CAN_BitSeg2_TypeDef CAN_BitSeg2,\r
+ uint8_t CAN_Prescaler);\r
+\r
+void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,\r
+ FunctionalState CAN_FilterActivation,\r
+ CAN_FilterMode_TypeDef CAN_FilterMode,\r
+ CAN_FilterScale_TypeDef CAN_FilterScale,\r
+ uint8_t CAN_FilterID1, \r
+ uint8_t CAN_FilterID2,\r
+ uint8_t CAN_FilterID3,\r
+ uint8_t CAN_FilterID4,\r
+ uint8_t CAN_FilterIDMask1,\r
+ uint8_t CAN_FilterIDMask2,\r
+ uint8_t CAN_FilterIDMask3,\r
+ uint8_t CAN_FilterIDMask4);\r
+void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState);\r
+void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility);\r
+CAN_TxStatus_TypeDef CAN_Transmit( uint32_t CAN_Id,\r
+ CAN_Id_TypeDef CAN_IDE,\r
+ CAN_RTR_TypeDef CAN_RTR,\r
+ uint8_t CAN_DLC,\r
+ uint8_t *CAN_Data);\r
+void CAN_TTComModeCmd(FunctionalState NewState);\r
+CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);\r
+void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox);\r
+void CAN_FIFORelease(void);\r
+CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void);\r
+void CAN_Receive(void);\r
+uint32_t CAN_GetReceivedId(void);\r
+CAN_Id_TypeDef CAN_GetReceivedIDE(void);\r
+CAN_RTR_TypeDef CAN_GetReceivedRTR(void);\r
+uint8_t CAN_GetReceivedDLC(void);\r
+uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex);\r
+uint8_t CAN_GetReceivedFMI(void);\r
+uint16_t CAN_GetMessageTimeStamp(void);\r
+CAN_Sleep_TypeDef CAN_Sleep(void);\r
+CAN_WakeUp_TypeDef CAN_WakeUp(void);\r
+CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode);\r
+CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void);\r
+CAN_Page_TypeDef CAN_GetSelectedPage(void);\r
+void CAN_SelectPage(CAN_Page_TypeDef CAN_Page);\r
+FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag);\r
+void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag);\r
+ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT);\r
+void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT);\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __STM8S_CAN_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_clk.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the CLK peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_CLK_H\r
+#define __STM8S_CLK_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Contains the description of all STM8 hardware registers */\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/** @addtogroup CLK_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Switch Mode Auto, Manual.\r
+ */\r
+typedef enum {\r
+ CLK_SWITCHMODE_MANUAL = (uint8_t)0x00, /*!< Enable the manual clock switching mode */\r
+ CLK_SWITCHMODE_AUTO = (uint8_t)0x01 /*!< Enable the automatic clock switching mode */\r
+} CLK_SwitchMode_TypeDef;\r
+\r
+/**\r
+ * @brief Current Clock State.\r
+ */\r
+typedef enum {\r
+ CLK_CURRENTCLOCKSTATE_DISABLE = (uint8_t)0x00, /*!< Current clock disable */\r
+ CLK_CURRENTCLOCKSTATE_ENABLE = (uint8_t)0x01 /*!< Current clock enable */\r
+} CLK_CurrentClockState_TypeDef;\r
+\r
+/**\r
+ * @brief Clock security system configuration.\r
+ */\r
+typedef enum {\r
+ CLK_CSSCONFIG_ENABLEWITHIT = (uint8_t)0x05, /*!< Enable CSS with detection interrupt */\r
+ CLK_CSSCONFIG_ENABLE = (uint8_t)0x01, /*!< Enable CSS without detection interrupt */\r
+ CLK_CSSCONFIG_DISABLE = (uint8_t)0x00 /*!< Leave CSS desactivated (to be used in CLK_Init() function) */\r
+} CLK_CSSConfig_TypeDef;\r
+\r
+/**\r
+ * @brief CLK Clock Source.\r
+ */\r
+typedef enum {\r
+ CLK_SOURCE_HSI = (uint8_t)0xE1, /*!< Clock Source HSI. */\r
+ CLK_SOURCE_LSI = (uint8_t)0xD2, /*!< Clock Source LSI. */\r
+ CLK_SOURCE_HSE = (uint8_t)0xB4 /*!< Clock Source HSE. */\r
+} CLK_Source_TypeDef;\r
+\r
+/**\r
+ * @brief CLK HSI Calibration Value.\r
+ */\r
+typedef enum {\r
+ CLK_HSITRIMVALUE_0 = (uint8_t)0x00, /*!< HSI Calibtation Value 0 */\r
+ CLK_HSITRIMVALUE_1 = (uint8_t)0x01, /*!< HSI Calibtation Value 1 */\r
+ CLK_HSITRIMVALUE_2 = (uint8_t)0x02, /*!< HSI Calibtation Value 2 */\r
+ CLK_HSITRIMVALUE_3 = (uint8_t)0x03, /*!< HSI Calibtation Value 3 */\r
+ CLK_HSITRIMVALUE_4 = (uint8_t)0x04, /*!< HSI Calibtation Value 4 */\r
+ CLK_HSITRIMVALUE_5 = (uint8_t)0x05, /*!< HSI Calibtation Value 5 */\r
+ CLK_HSITRIMVALUE_6 = (uint8_t)0x06, /*!< HSI Calibtation Value 6 */\r
+ CLK_HSITRIMVALUE_7 = (uint8_t)0x07 /*!< HSI Calibtation Value 7 */\r
+} CLK_HSITrimValue_TypeDef;\r
+\r
+/**\r
+ * @brief CLK Clock Output\r
+ */\r
+typedef enum {\r
+ CLK_OUTPUT_HSI = (uint8_t)0x00, /*!< Clock Output HSI */\r
+ CLK_OUTPUT_LSI = (uint8_t)0x02, /*!< Clock Output LSI */\r
+ CLK_OUTPUT_HSE = (uint8_t)0x04, /*!< Clock Output HSE */\r
+ CLK_OUTPUT_CPU = (uint8_t)0x08, /*!< Clock Output CPU */\r
+ CLK_OUTPUT_CPUDIV2 = (uint8_t)0x0A, /*!< Clock Output CPU/2 */\r
+ CLK_OUTPUT_CPUDIV4 = (uint8_t)0x0C, /*!< Clock Output CPU/4 */\r
+ CLK_OUTPUT_CPUDIV8 = (uint8_t)0x0E, /*!< Clock Output CPU/8 */\r
+ CLK_OUTPUT_CPUDIV16 = (uint8_t)0x10, /*!< Clock Output CPU/16 */\r
+ CLK_OUTPUT_CPUDIV32 = (uint8_t)0x12, /*!< Clock Output CPU/32 */\r
+ CLK_OUTPUT_CPUDIV64 = (uint8_t)0x14, /*!< Clock Output CPU/64 */\r
+ CLK_OUTPUT_HSIRC = (uint8_t)0x16, /*!< Clock Output HSI RC */\r
+ CLK_OUTPUT_MASTER = (uint8_t)0x18, /*!< Clock Output Master */\r
+ CLK_OUTPUT_OTHERS = (uint8_t)0x1A /*!< Clock Output OTHER */\r
+} CLK_Output_TypeDef;\r
+\r
+/**\r
+ * @brief CLK Enable peripheral\r
+ */\r
+/* Elements values convention: 0xXY\r
+ X = choice between the peripheral registers\r
+ X = 0 : PCKENR1\r
+ X = 1 : PCKENR2\r
+ Y = Peripheral position in the register\r
+*/\r
+typedef enum {\r
+ CLK_PERIPHERAL_I2C = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, I2C */\r
+ CLK_PERIPHERAL_SPI = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, SPI */\r
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)\r
+ CLK_PERIPHERAL_UART1 = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, UART1 */\r
+#else\r
+ CLK_PERIPHERAL_UART1 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART1 */\r
+#endif\r
+ CLK_PERIPHERAL_UART2 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART2 */\r
+ CLK_PERIPHERAL_UART3 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, UART3 */\r
+ CLK_PERIPHERAL_TIMER6 = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer6 */\r
+ CLK_PERIPHERAL_TIMER4 = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, Timer4 */\r
+ CLK_PERIPHERAL_TIMER5 = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer5 */\r
+ CLK_PERIPHERAL_TIMER2 = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, Timer2 */\r
+ CLK_PERIPHERAL_TIMER3 = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, Timer3 */\r
+ CLK_PERIPHERAL_TIMER1 = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, Timer1 */\r
+ CLK_PERIPHERAL_AWU = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, AWU */\r
+ CLK_PERIPHERAL_ADC = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, ADC */\r
+ CLK_PERIPHERAL_CAN = (uint8_t)0x17 /*!< Peripheral Clock Enable 2, CAN */\r
+} CLK_Peripheral_TypeDef;\r
+\r
+/**\r
+ * @brief CLK Flags.\r
+ */\r
+/* Elements values convention: 0xXZZ\r
+ X = choice between the flags registers\r
+ X = 1 : ICKR\r
+ X = 2 : ECKR\r
+ X = 3 : SWCR\r
+ X = 4 : CSSR\r
+ X = 5 : CCOR\r
+ ZZ = flag mask in the register (same as map file)\r
+*/\r
+typedef enum {\r
+ CLK_FLAG_LSIRDY = (uint16_t)0x0110, /*!< Low speed internal oscillator ready Flag */\r
+ CLK_FLAG_HSIRDY = (uint16_t)0x0102, /*!< High speed internal oscillator ready Flag */\r
+ CLK_FLAG_HSERDY = (uint16_t)0x0202, /*!< High speed external oscillator ready Flag */\r
+ CLK_FLAG_SWIF = (uint16_t)0x0308, /*!< Clock switch interrupt Flag */\r
+ CLK_FLAG_SWBSY = (uint16_t)0x0301, /*!< Switch busy Flag */\r
+ CLK_FLAG_CSSD = (uint16_t)0x0408, /*!< Clock security system detection Flag */\r
+ CLK_FLAG_AUX = (uint16_t)0x0402, /*!< Auxiliary oscillator connected to master clock */\r
+ CLK_FLAG_CCOBSY = (uint16_t)0x0504, /*!< Configurable clock output busy */\r
+ CLK_FLAG_CCORDY = (uint16_t)0x0502 /*!< Configurable clock output ready */\r
+\r
+}CLK_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief CLK interrupt configuration and Flags cleared by software.\r
+ */\r
+typedef enum {\r
+ CLK_IT_CSSD = (uint8_t)0x0C, /*!< Clock security system detection Flag */\r
+ CLK_IT_SWIF = (uint8_t)0x1C /*!< Clock switch interrupt Flag */\r
+}CLK_IT_TypeDef;\r
+\r
+/**\r
+ * @brief CLK Clock Divisor.\r
+ */\r
+/* Warning:\r
+ 0xxxxxx = HSI divider\r
+ 1xxxxxx = CPU divider\r
+ Other bits correspond to the divider's bits mapping\r
+*/\r
+typedef enum {\r
+ CLK_PRESCALER_HSIDIV1 = (uint8_t)0x00, /*!< High speed internal clock prescaler: 1 */\r
+ CLK_PRESCALER_HSIDIV2 = (uint8_t)0x08, /*!< High speed internal clock prescaler: 2 */\r
+ CLK_PRESCALER_HSIDIV4 = (uint8_t)0x10, /*!< High speed internal clock prescaler: 4 */\r
+ CLK_PRESCALER_HSIDIV8 = (uint8_t)0x18, /*!< High speed internal clock prescaler: 8 */\r
+ CLK_PRESCALER_CPUDIV1 = (uint8_t)0x80, /*!< CPU clock division factors 1 */\r
+ CLK_PRESCALER_CPUDIV2 = (uint8_t)0x81, /*!< CPU clock division factors 2 */\r
+ CLK_PRESCALER_CPUDIV4 = (uint8_t)0x82, /*!< CPU clock division factors 4 */\r
+ CLK_PRESCALER_CPUDIV8 = (uint8_t)0x83, /*!< CPU clock division factors 8 */\r
+ CLK_PRESCALER_CPUDIV16 = (uint8_t)0x84, /*!< CPU clock division factors 16 */\r
+ CLK_PRESCALER_CPUDIV32 = (uint8_t)0x85, /*!< CPU clock division factors 32 */\r
+ CLK_PRESCALER_CPUDIV64 = (uint8_t)0x86, /*!< CPU clock division factors 64 */\r
+ CLK_PRESCALER_CPUDIV128 = (uint8_t)0x87 /*!< CPU clock division factors 128 */\r
+} CLK_Prescaler_TypeDef;\r
+\r
+/**\r
+ * @brief SWIM Clock divider.\r
+ */\r
+typedef enum {\r
+ CLK_SWIMDIVIDER_2 = (uint8_t)0x00, /*!< SWIM clock is divided by 2 */\r
+ CLK_SWIMDIVIDER_OTHER = (uint8_t)0x01 /*!< SWIM clock is not divided by 2 */\r
+}CLK_SWIMDivider_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup CLK_Exported_Constants\r
+ * @{\r
+ */\r
+#define CLK_TIMEOUT ((uint16_t)0x491) /*!< Timeout for the clock switch operation. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+/** @addtogroup CLK_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the clock switching modes.\r
+ */\r
+#define IS_CLK_SWITCHMODE_OK(MODE) (((MODE) == CLK_SWITCHMODE_MANUAL) || ((MODE) == CLK_SWITCHMODE_AUTO))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the current clock state.\r
+ */\r
+#define IS_CLK_CURRENTCLOCKSTATE_OK(STATE) (((STATE) == CLK_CURRENTCLOCKSTATE_DISABLE) ||\\r
+ ((STATE) == CLK_CURRENTCLOCKSTATE_ENABLE))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the CSS configuration.\r
+ */\r
+#define IS_CLK_CSSCONFIG_OK(CSSVALUE) (((CSSVALUE) == CLK_CSSCONFIG_ENABLEWITHIT) ||\\r
+ ((CSSVALUE) == CLK_CSSCONFIG_ENABLE) ||\\r
+ ((CSSVALUE) == CLK_CSSCONFIG_DISABLE))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different clock sources.\r
+ */\r
+#define IS_CLK_SOURCE_OK(SOURCE) (((SOURCE) == CLK_SOURCE_HSI) ||\\r
+ ((SOURCE) == CLK_SOURCE_LSI) ||\\r
+ ((SOURCE) == CLK_SOURCE_HSE))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different HSI trimming values.\r
+ */\r
+#define IS_CLK_HSITRIMVALUE_OK(TRIMVALUE) (((TRIMVALUE) == CLK_HSITRIMVALUE_0) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_1) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_2) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_3) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_4) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_5) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_6) ||\\r
+ ((TRIMVALUE) == CLK_HSITRIMVALUE_7))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different clocks to output.\r
+ */\r
+#define IS_CLK_OUTPUT_OK(OUTPUT) (((OUTPUT) == CLK_OUTPUT_HSI) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_HSE) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_LSI) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPU) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV2) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV4) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV8) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV16) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV32) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_CPUDIV64) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_HSIRC) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_MASTER) ||\\r
+ ((OUTPUT) == CLK_OUTPUT_OTHERS))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different peripheral's clock.\r
+ */\r
+#define IS_CLK_PERIPHERAL_OK(PERIPHERAL) (((PERIPHERAL) == CLK_PERIPHERAL_I2C) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_SPI) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_UART3) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_UART2) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_UART1) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER4) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER2) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER5) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER6) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER3) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_TIMER1) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_CAN) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_ADC) ||\\r
+ ((PERIPHERAL) == CLK_PERIPHERAL_AWU))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different clock flags.\r
+ */\r
+#define IS_CLK_FLAG_OK(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\\r
+ ((FLAG) == CLK_FLAG_HSIRDY) ||\\r
+ ((FLAG) == CLK_FLAG_HSERDY) ||\\r
+ ((FLAG) == CLK_FLAG_SWIF) ||\\r
+ ((FLAG) == CLK_FLAG_SWBSY) ||\\r
+ ((FLAG) == CLK_FLAG_CSSD) ||\\r
+ ((FLAG) == CLK_FLAG_AUX) ||\\r
+ ((FLAG) == CLK_FLAG_CCOBSY) ||\\r
+ ((FLAG) == CLK_FLAG_CCORDY))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different clock IT pending bits.\r
+ */\r
+#define IS_CLK_IT_OK(IT) (((IT) == CLK_IT_CSSD) || ((IT) == CLK_IT_SWIF))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different HSI prescaler values.\r
+ */\r
+#define IS_CLK_HSIPRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV8))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different clock prescaler values.\r
+ */\r
+#define IS_CLK_PRESCALER_OK(PRESCALER) (((PRESCALER) == CLK_PRESCALER_HSIDIV1) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV2) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV4) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_HSIDIV8) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV1) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV2) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV4) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV8) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV16) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV32) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV64) ||\\r
+ ((PRESCALER) == CLK_PRESCALER_CPUDIV128))\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different SWIM dividers values.\r
+ */\r
+#define IS_CLK_SWIMDIVIDER_OK(SWIMDIVIDER) (((SWIMDIVIDER) == CLK_SWIMDIVIDER_2) || ((SWIMDIVIDER) == CLK_SWIMDIVIDER_OTHER))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CLK_Exported_functions\r
+ * @{\r
+ */\r
+void CLK_DeInit(void);\r
+void CLK_HSECmd(FunctionalState NewState);\r
+void CLK_HSICmd(FunctionalState NewState);\r
+void CLK_LSICmd(FunctionalState NewState);\r
+void CLK_CCOCmd(FunctionalState NewState);\r
+void CLK_ClockSwitchCmd(FunctionalState NewState);\r
+void CLK_FastHaltWakeUpCmd(FunctionalState NewState);\r
+void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState);\r
+void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);\r
+ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState);\r
+void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler);\r
+void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO);\r
+void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);\r
+void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler);\r
+void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider);\r
+void CLK_ClockSecuritySystemEnable(void);\r
+void CLK_SYSCLKEmergencyClear(void);\r
+void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue);\r
+uint32_t CLK_GetClockFreq(void);\r
+CLK_Source_TypeDef CLK_GetSYSCLKSource(void);\r
+FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG);\r
+ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);\r
+void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif /* __STM8S_CLK_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**
+ ******************************************************************************
+ * @file stm8s_conf.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 18-November-2011
+ * @brief This file is used to configure the Library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8S_CONF_H
+#define __STM8S_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8s.h"
+
+/* Uncomment the line below to enable peripheral header file inclusion */
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) ||\
+ defined(STM8S903) || defined (STM8AF626x)
+#include "stm8s_adc1.h"
+#endif /* (STM8S105) ||(STM8S103) || (STM8S903) || STM8AF626x*/
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF52Ax) ||\
+ defined (STM8AF62Ax)
+ #include "stm8s_adc2.h"
+#endif /* (STM8S208) || (STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
+#include "stm8s_awu.h"
+#include "stm8s_beep.h"
+#if defined (STM8S208) || defined (STM8AF52Ax)
+ #include "stm8s_can.h"
+#endif /* STM8S208 || STM8AF52Ax */
+#include "stm8s_clk.h"
+#include "stm8s_exti.h"
+#include "stm8s_flash.h"
+#include "stm8s_gpio.h"
+#include "stm8s_i2c.h"
+#include "stm8s_itc.h"
+#include "stm8s_iwdg.h"
+#include "stm8s_rst.h"
+#include "stm8s_spi.h"
+#include "stm8s_tim1.h"
+#ifndef STM8S903
+ #include "stm8s_tim2.h"
+#endif /* STM8S903 */
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) ||defined(STM8S105) ||\
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)
+ #include "stm8s_tim3.h"
+#endif /* (STM8S208) ||defined(STM8S207) || defined(STM8S007) ||defined(STM8S105) */
+#ifndef STM8S903
+ #include "stm8s_tim4.h"
+#endif /* STM8S903 */
+#ifdef STM8S903
+ #include "stm8s_tim5.h"
+ #include "stm8s_tim6.h"
+#endif /* STM8S903 */
+#if defined(STM8S208) ||defined(STM8S207) || defined(STM8S007) ||defined(STM8S103) ||\
+ defined(STM8S003) || defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
+ #include "stm8s_uart1.h"
+#endif /* STM8S208 || STM8S207 || STM8S103 ||STM8S903 || STM8AF52Ax || STM8AF62Ax */
+#if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x)
+ #include "stm8s_uart2.h"
+#endif /* STM8S105 || STM8AF626x */
+#if defined(STM8S208) ||defined(STM8S207) || defined(STM8S007) || defined (STM8AF52Ax) ||\
+ defined (STM8AF62Ax)
+ #include "stm8s_uart3.h"
+#endif /* STM8S208 || STM8S207 || STM8AF52Ax || STM8AF62Ax */
+#include "stm8s_wwdg.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+ Standard Peripheral Library drivers code */
+//#define USE_FULL_ASSERT (1)
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval : None
+ */
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM8S_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_exti.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the EXTI peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_EXTI_H__\r
+#define __STM8S_EXTI_H__\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup EXTI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief EXTI Sensitivity values for PORTA to PORTE\r
+ */\r
+typedef enum {\r
+ EXTI_SENSITIVITY_FALL_LOW = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */\r
+ EXTI_SENSITIVITY_RISE_ONLY = (uint8_t)0x01, /*!< Interrupt on Rising edge only */\r
+ EXTI_SENSITIVITY_FALL_ONLY = (uint8_t)0x02, /*!< Interrupt on Falling edge only */\r
+ EXTI_SENSITIVITY_RISE_FALL = (uint8_t)0x03 /*!< Interrupt on Rising and Falling edges */\r
+} EXTI_Sensitivity_TypeDef;\r
+\r
+/**\r
+ * @brief EXTI Sensitivity values for TLI\r
+ */\r
+typedef enum {\r
+ EXTI_TLISENSITIVITY_FALL_ONLY = (uint8_t)0x00, /*!< Top Level Interrupt on Falling edge only */\r
+ EXTI_TLISENSITIVITY_RISE_ONLY = (uint8_t)0x04 /*!< Top Level Interrupt on Rising edge only */\r
+} EXTI_TLISensitivity_TypeDef;\r
+\r
+/**\r
+ * @brief EXTI PortNum possible values\r
+ */\r
+typedef enum {\r
+ EXTI_PORT_GPIOA = (uint8_t)0x00, /*!< GPIO Port A */\r
+ EXTI_PORT_GPIOB = (uint8_t)0x01, /*!< GPIO Port B */\r
+ EXTI_PORT_GPIOC = (uint8_t)0x02, /*!< GPIO Port C */\r
+ EXTI_PORT_GPIOD = (uint8_t)0x03, /*!< GPIO Port D */\r
+ EXTI_PORT_GPIOE = (uint8_t)0x04 /*!< GPIO Port E */\r
+} EXTI_Port_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup EXTI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for PORTA to PORTE.\r
+ */\r
+#define IS_EXTI_SENSITIVITY_OK(SensitivityValue) \\r
+ (((SensitivityValue) == EXTI_SENSITIVITY_FALL_LOW) || \\r
+ ((SensitivityValue) == EXTI_SENSITIVITY_RISE_ONLY) || \\r
+ ((SensitivityValue) == EXTI_SENSITIVITY_FALL_ONLY) || \\r
+ ((SensitivityValue) == EXTI_SENSITIVITY_RISE_FALL))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for TLI.\r
+ */\r
+#define IS_EXTI_TLISENSITIVITY_OK(SensitivityValue) \\r
+ (((SensitivityValue) == EXTI_TLISENSITIVITY_FALL_ONLY) || \\r
+ ((SensitivityValue) == EXTI_TLISENSITIVITY_RISE_ONLY))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different Port values\r
+ */\r
+#define IS_EXTI_PORT_OK(PORT) \\r
+ (((PORT) == EXTI_PORT_GPIOA) ||\\r
+ ((PORT) == EXTI_PORT_GPIOB) ||\\r
+ ((PORT) == EXTI_PORT_GPIOC) ||\\r
+ ((PORT) == EXTI_PORT_GPIOD) ||\\r
+ ((PORT) == EXTI_PORT_GPIOE))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different values of the EXTI PinMask\r
+ */\r
+#define IS_EXTI_PINMASK_OK(PinMask) ((((PinMask) & (uint8_t)0x00) == (uint8_t)0x00) && ((PinMask) != (uint8_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup EXTI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void EXTI_DeInit(void);\r
+void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue);\r
+void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue);\r
+EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port);\r
+EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_EXTI_H__ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_flash.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the FLASH peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_FLASH_H\r
+#define __STM8S_FLASH_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASH_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define FLASH_PROG_START_PHYSICAL_ADDRESS ((uint32_t)0x008000) /*!< Program memory: start address */\r
+\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)\r
+ #define FLASH_PROG_END_PHYSICAL_ADDRESS ((uint32_t)0x027FFF) /*!< Program memory: end address */\r
+ #define FLASH_PROG_BLOCKS_NUMBER ((uint16_t)1024) /*!< Program memory: total number of blocks */\r
+ #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */\r
+ #define FLASH_DATA_END_PHYSICAL_ADDRESS ((uint32_t)0x0047FF) /*!< Data EEPROM memory: end address */\r
+ #define FLASH_DATA_BLOCKS_NUMBER ((uint16_t)16) /*!< Data EEPROM memory: total number of blocks */\r
+ #define FLASH_BLOCK_SIZE ((uint8_t)128) /*!< Number of bytes in a block (common for Program and Data memories) */\r
+#endif /* STM8S208, STM8S207, STM8S007, STM8AF52Ax, STM8AF62Ax */\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)\r
+ #define FLASH_PROG_END_PHYSICAL_ADDRESS ((uint32_t)0xFFFF) /*!< Program memory: end address */\r
+ #define FLASH_PROG_BLOCKS_NUMBER ((uint16_t)256) /*!< Program memory: total number of blocks */\r
+ #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */\r
+ #define FLASH_DATA_END_PHYSICAL_ADDRESS ((uint32_t)0x0043FF) /*!< Data EEPROM memory: end address */\r
+ #define FLASH_DATA_BLOCKS_NUMBER ((uint16_t)8) /*!< Data EEPROM memory: total number of blocks */\r
+ #define FLASH_BLOCK_SIZE ((uint8_t)128) /*!< Number of bytes in a block (common for Program and Data memories) */\r
+#endif /* STM8S105 or STM8AF626x */\r
+\r
+#if defined(STM8S103) || defined(STM8S003) || defined(STM8S903)\r
+ #define FLASH_PROG_END_PHYSICAL_ADDRESS ((uint32_t)0x9FFF) /*!< Program memory: end address */\r
+ #define FLASH_PROG_BLOCKS_NUMBER ((uint16_t)128) /*!< Program memory: total number of blocks */\r
+ #define FLASH_DATA_START_PHYSICAL_ADDRESS ((uint32_t)0x004000) /*!< Data EEPROM memory: start address */\r
+ #define FLASH_DATA_END_PHYSICAL_ADDRESS ((uint32_t)0x00427F) /*!< Data EEPROM memory: end address */\r
+ #define FLASH_DATA_BLOCKS_NUMBER ((uint16_t)10) /*!< Data EEPROM memory: total number of blocks */\r
+ #define FLASH_BLOCK_SIZE ((uint8_t)64) /*!< Number of bytes in a block (common for Program and Data memories) */\r
+#endif /* STM8S103, STM8S903 */\r
+\r
+#define FLASH_RASS_KEY1 ((uint8_t)0x56) /*!< First RASS key */\r
+#define FLASH_RASS_KEY2 ((uint8_t)0xAE) /*!< Second RASS key */\r
+\r
+#define OPTION_BYTE_START_PHYSICAL_ADDRESS ((uint16_t)0x4800)\r
+#define OPTION_BYTE_END_PHYSICAL_ADDRESS ((uint16_t)0x487F)\r
+#define FLASH_OPTIONBYTE_ERROR ((uint16_t)0x5555) /*!< Error code option byte \r
+ (if value read is not equal to complement value read) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief FLASH Memory types\r
+ */\r
+typedef enum {\r
+ FLASH_MEMTYPE_PROG = (uint8_t)0xFD, /*!< Program memory */\r
+ FLASH_MEMTYPE_DATA = (uint8_t)0xF7 /*!< Data EEPROM memory */\r
+} FLASH_MemType_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH programming modes\r
+ */\r
+typedef enum {\r
+ FLASH_PROGRAMMODE_STANDARD = (uint8_t)0x00, /*!< Standard programming mode */\r
+ FLASH_PROGRAMMODE_FAST = (uint8_t)0x10 /*!< Fast programming mode */\r
+} FLASH_ProgramMode_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH fixed programming time\r
+ */\r
+typedef enum {\r
+ FLASH_PROGRAMTIME_STANDARD = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */\r
+ FLASH_PROGRAMTIME_TPROG = (uint8_t)0x01 /*!< Programming time fixed at tprog */\r
+} FLASH_ProgramTime_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH Low Power mode select\r
+ */\r
+typedef enum {\r
+ FLASH_LPMODE_POWERDOWN = (uint8_t)0x04, /*!< HALT: Power-Down / ACTIVE-HALT: Power-Down */\r
+ FLASH_LPMODE_STANDBY = (uint8_t)0x08, /*!< HALT: Standby / ACTIVE-HALT: Standby */\r
+ FLASH_LPMODE_POWERDOWN_STANDBY = (uint8_t)0x00, /*!< HALT: Power-Down / ACTIVE-HALT: Standby */\r
+ FLASH_LPMODE_STANDBY_POWERDOWN = (uint8_t)0x0C /*!< HALT: Standby / ACTIVE-HALT: Power-Down */\r
+}\r
+FLASH_LPMode_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH status of the last operation\r
+ */\r
+typedef enum {\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x) \r
+ FLASH_STATUS_END_HIGH_VOLTAGE = (uint8_t)0x40, /*!< End of high voltage */\r
+#endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */\r
+ FLASH_STATUS_SUCCESSFUL_OPERATION = (uint8_t)0x04, /*!< End of operation flag */\r
+ FLASH_STATUS_TIMEOUT = (uint8_t)0x02, /*!< Time out error */\r
+ FLASH_STATUS_WRITE_PROTECTION_ERROR = (uint8_t)0x01 /*!< Write attempted to protected page */\r
+} FLASH_Status_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH flags definition\r
+ * - Warning : FLAG value = mapping position register\r
+ */\r
+typedef enum {\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)\r
+ FLASH_FLAG_HVOFF = (uint8_t)0x40, /*!< End of high voltage flag */\r
+#endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */\r
+ FLASH_FLAG_DUL = (uint8_t)0x08, /*!< Data EEPROM unlocked flag */\r
+ FLASH_FLAG_EOP = (uint8_t)0x04, /*!< End of programming (write or erase operation) flag */\r
+ FLASH_FLAG_PUL = (uint8_t)0x02, /*!< Flash Program memory unlocked flag */\r
+ FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 /*!< Write attempted to protected page flag */\r
+} FLASH_Flag_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different functions parameters.\r
+ * @addtogroup FLASH_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the flash program Address\r
+ */\r
+\r
+#define IS_FLASH_PROG_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && \\r
+ ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the data eeprom Address\r
+ */\r
+\r
+#define IS_FLASH_DATA_ADDRESS_OK(ADDRESS) (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && \\r
+ ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the data eeprom and flash program Address\r
+ */\r
+#define IS_FLASH_ADDRESS_OK(ADDRESS)((((ADDRESS) >= FLASH_PROG_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_PROG_END_PHYSICAL_ADDRESS)) || \\r
+ (((ADDRESS) >= FLASH_DATA_START_PHYSICAL_ADDRESS) && ((ADDRESS) <= FLASH_DATA_END_PHYSICAL_ADDRESS)))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the flash program Block number\r
+ */\r
+#define IS_FLASH_PROG_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_PROG_BLOCKS_NUMBER)\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the data eeprom Block number\r
+ */\r
+#define IS_FLASH_DATA_BLOCK_NUMBER_OK(BLOCKNUM) ((BLOCKNUM) < FLASH_DATA_BLOCKS_NUMBER)\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the flash memory type\r
+ */\r
+\r
+#define IS_MEMORY_TYPE_OK(MEMTYPE) (((MEMTYPE) == FLASH_MEMTYPE_PROG) || \\r
+ ((MEMTYPE) == FLASH_MEMTYPE_DATA))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different sensitivity values for the flash program mode\r
+ */\r
+\r
+#define IS_FLASH_PROGRAM_MODE_OK(MODE) (((MODE) == FLASH_PROGRAMMODE_STANDARD) || \\r
+ ((MODE) == FLASH_PROGRAMMODE_FAST))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the program time mode\r
+ */\r
+\r
+#define IS_FLASH_PROGRAM_TIME_OK(TIME) (((TIME) == FLASH_PROGRAMTIME_STANDARD) || \\r
+ ((TIME) == FLASH_PROGRAMTIME_TPROG))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the low power mode\r
+ */\r
+\r
+#define IS_FLASH_LOW_POWER_MODE_OK(LPMODE) (((LPMODE) == FLASH_LPMODE_POWERDOWN) || \\r
+ ((LPMODE) == FLASH_LPMODE_STANDBY) || \\r
+ ((LPMODE) == FLASH_LPMODE_POWERDOWN_STANDBY) || \\r
+ ((LPMODE) == FLASH_LPMODE_STANDBY_POWERDOWN))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the option bytes Address\r
+ */\r
+#define IS_OPTION_BYTE_ADDRESS_OK(ADDRESS) (((ADDRESS) >= OPTION_BYTE_START_PHYSICAL_ADDRESS) && \\r
+ ((ADDRESS) <= OPTION_BYTE_END_PHYSICAL_ADDRESS))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different flags values\r
+ */\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined(STM8AF626x)\r
+ #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \\r
+ ((FLAG) == FLASH_FLAG_DUL) || \\r
+ ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PUL) || \\r
+ ((FLAG) == FLASH_FLAG_WR_PG_DIS))\r
+#else /* STM8S103, STM8S903 */\r
+ #define IS_FLASH_FLAGS_OK(FLAG) (((FLAG) == FLASH_FLAG_DUL) || \\r
+ ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PUL) || \\r
+ ((FLAG) == FLASH_FLAG_WR_PG_DIS))\r
+#endif /* STM8S208, STM8S207, STM8S105, STM8AF62Ax, STM8AF52Ax, STM8AF626x */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);\r
+void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);\r
+void FLASH_DeInit(void);\r
+void FLASH_ITConfig(FunctionalState NewState);\r
+void FLASH_EraseByte(uint32_t Address);\r
+void FLASH_ProgramByte(uint32_t Address, uint8_t Data);\r
+uint8_t FLASH_ReadByte(uint32_t Address);\r
+void FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+uint16_t FLASH_ReadOptionByte(uint16_t Address);\r
+void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);\r
+void FLASH_EraseOptionByte(uint16_t Address);\r
+void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode);\r
+void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);\r
+FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void);\r
+FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);\r
+uint32_t FLASH_GetBootSize(void);\r
+FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG);\r
+\r
+/**\r
+@code\r
+ All the functions declared below must be executed from RAM exclusively, except \r
+ for the FLASH_WaitForLastOperation function which can be executed from Flash.\r
+ \r
+ Steps of the execution from RAM differs from one toolchain to another.\r
+ for more details refer to stm8s_flash.c file.\r
+ \r
+ To enable execution from RAM you can either uncomment the following define \r
+ in the stm8s.h file or define it in your toolchain compiler preprocessor\r
+ - #define RAM_EXECUTION (1) \r
+\r
+@endcode\r
+*/\r
+IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));\r
+IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, \r
+ FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));\r
+IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /*__STM8S_FLASH_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the GPIO peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_GPIO_H\r
+#define __STM8S_GPIO_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported variables ------------------------------------------------------- */\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup GPIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief GPIO modes\r
+ *\r
+ * Bits definitions:\r
+ * - Bit 7: 0 = INPUT mode\r
+ * 1 = OUTPUT mode\r
+ * 1 = PULL-UP (input) or PUSH-PULL (output)\r
+ * - Bit 5: 0 = No external interrupt (input) or No slope control (output)\r
+ * 1 = External interrupt (input) or Slow control enabled (output)\r
+ * - Bit 4: 0 = Low level (output)\r
+ * 1 = High level (output push-pull) or HI-Z (output open-drain)\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_MODE_IN_FL_NO_IT = (uint8_t)0x00, /*!< Input floating, no external interrupt */\r
+ GPIO_MODE_IN_PU_NO_IT = (uint8_t)0x40, /*!< Input pull-up, no external interrupt */\r
+ GPIO_MODE_IN_FL_IT = (uint8_t)0x20, /*!< Input floating, external interrupt */\r
+ GPIO_MODE_IN_PU_IT = (uint8_t)0x60, /*!< Input pull-up, external interrupt */\r
+ GPIO_MODE_OUT_OD_LOW_FAST = (uint8_t)0xA0, /*!< Output open-drain, low level, 10MHz */\r
+ GPIO_MODE_OUT_PP_LOW_FAST = (uint8_t)0xE0, /*!< Output push-pull, low level, 10MHz */\r
+ GPIO_MODE_OUT_OD_LOW_SLOW = (uint8_t)0x80, /*!< Output open-drain, low level, 2MHz */\r
+ GPIO_MODE_OUT_PP_LOW_SLOW = (uint8_t)0xC0, /*!< Output push-pull, low level, 2MHz */\r
+ GPIO_MODE_OUT_OD_HIZ_FAST = (uint8_t)0xB0, /*!< Output open-drain, high-impedance level,10MHz */\r
+ GPIO_MODE_OUT_PP_HIGH_FAST = (uint8_t)0xF0, /*!< Output push-pull, high level, 10MHz */\r
+ GPIO_MODE_OUT_OD_HIZ_SLOW = (uint8_t)0x90, /*!< Output open-drain, high-impedance level, 2MHz */\r
+ GPIO_MODE_OUT_PP_HIGH_SLOW = (uint8_t)0xD0 /*!< Output push-pull, high level, 2MHz */\r
+}GPIO_Mode_TypeDef;\r
+\r
+/**\r
+ * @brief Definition of the GPIO pins. Used by the @ref GPIO_Init function in\r
+ * order to select the pins to be initialized.\r
+ */\r
+\r
+typedef enum\r
+{\r
+ GPIO_PIN_0 = ((uint8_t)0x01), /*!< Pin 0 selected */\r
+ GPIO_PIN_1 = ((uint8_t)0x02), /*!< Pin 1 selected */\r
+ GPIO_PIN_2 = ((uint8_t)0x04), /*!< Pin 2 selected */\r
+ GPIO_PIN_3 = ((uint8_t)0x08), /*!< Pin 3 selected */\r
+ GPIO_PIN_4 = ((uint8_t)0x10), /*!< Pin 4 selected */\r
+ GPIO_PIN_5 = ((uint8_t)0x20), /*!< Pin 5 selected */\r
+ GPIO_PIN_6 = ((uint8_t)0x40), /*!< Pin 6 selected */\r
+ GPIO_PIN_7 = ((uint8_t)0x80), /*!< Pin 7 selected */\r
+ GPIO_PIN_LNIB = ((uint8_t)0x0F), /*!< Low nibble pins selected */\r
+ GPIO_PIN_HNIB = ((uint8_t)0xF0), /*!< High nibble pins selected */\r
+ GPIO_PIN_ALL = ((uint8_t)0xFF) /*!< All pins selected */\r
+}GPIO_Pin_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup GPIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different\r
+ * values of GPIOMode_TypeDef.\r
+ */\r
+#define IS_GPIO_MODE_OK(MODE) \\r
+ (((MODE) == GPIO_MODE_IN_FL_NO_IT) || \\r
+ ((MODE) == GPIO_MODE_IN_PU_NO_IT) || \\r
+ ((MODE) == GPIO_MODE_IN_FL_IT) || \\r
+ ((MODE) == GPIO_MODE_IN_PU_IT) || \\r
+ ((MODE) == GPIO_MODE_OUT_OD_LOW_FAST) || \\r
+ ((MODE) == GPIO_MODE_OUT_PP_LOW_FAST) || \\r
+ ((MODE) == GPIO_MODE_OUT_OD_LOW_SLOW) || \\r
+ ((MODE) == GPIO_MODE_OUT_PP_LOW_SLOW) || \\r
+ ((MODE) == GPIO_MODE_OUT_OD_HIZ_FAST) || \\r
+ ((MODE) == GPIO_MODE_OUT_PP_HIGH_FAST) || \\r
+ ((MODE) == GPIO_MODE_OUT_OD_HIZ_SLOW) || \\r
+ ((MODE) == GPIO_MODE_OUT_PP_HIGH_SLOW))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different\r
+ * values of GPIO_Pins.\r
+ */\r
+#define IS_GPIO_PIN_OK(PIN) ((PIN) != (uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+/** @addtogroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal);\r
+void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);\r
+void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);\r
+void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins);\r
+uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);\r
+void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8L_GPIO_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the I2C peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_I2C_H\r
+#define __STM8S_I2C_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup I2C_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief I2C duty cycle (fast mode only)\r
+ */\r
+typedef enum\r
+{\r
+ I2C_DUTYCYCLE_2 = (uint8_t)0x00, /*!< Fast mode Tlow/THigh = 2 */\r
+ I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 /*!< Fast mode Tlow/Thigh = 16/9 */\r
+} I2C_DutyCycle_TypeDef;\r
+\r
+/**\r
+ * @brief I2C Acknowledgement configuration\r
+ */\r
+typedef enum\r
+{\r
+ I2C_ACK_NONE = (uint8_t)0x00, /*!< No acknowledge */\r
+ I2C_ACK_CURR = (uint8_t)0x01, /*!< Acknowledge on the current byte */\r
+ I2C_ACK_NEXT = (uint8_t)0x02 /*!< Acknowledge on the next byte */\r
+} I2C_Ack_TypeDef;\r
+\r
+/**\r
+ * @brief I2C Addressing Mode (slave mode only)\r
+ */\r
+typedef enum\r
+{\r
+ I2C_ADDMODE_7BIT = (uint8_t)0x00, /*!< 7-bit slave address (10-bit address not acknowledged) */\r
+ I2C_ADDMODE_10BIT = (uint8_t)0x80 /*!< 10-bit slave address (7-bit address not acknowledged) */\r
+} I2C_AddMode_TypeDef;\r
+\r
+/**\r
+ * @brief I2C Interrupt sources\r
+ * Warning: the values correspond to the bit position in the ITR register\r
+ */\r
+typedef enum\r
+{\r
+ I2C_IT_ERR = (uint8_t)0x01, /*!< Error Interruption */\r
+ I2C_IT_EVT = (uint8_t)0x02, /*!< Event Interruption */\r
+ I2C_IT_BUF = (uint8_t)0x04 /*!< Buffer Interruption */\r
+} I2C_IT_TypeDef;\r
+\r
+/**\r
+ * @brief I2C transfer direction\r
+ * Warning: the values correspond to the ADD0 bit position in the OARL register\r
+ */\r
+typedef enum\r
+{\r
+ I2C_DIRECTION_TX = (uint8_t)0x00, /*!< Transmission direction */\r
+ I2C_DIRECTION_RX = (uint8_t)0x01 /*!< Reception direction */\r
+} I2C_Direction_TypeDef;\r
+\r
+/**\r
+ * @brief I2C Flags\r
+ * @brief Elements values convention: 0xXXYY\r
+ * X = SRx registers index\r
+ * X = 1 : SR1\r
+ * X = 2 : SR2\r
+ * X = 3 : SR3\r
+ * Y = Flag mask in the register\r
+ */\r
+\r
+typedef enum\r
+{\r
+ /* SR1 register flags */\r
+ I2C_FLAG_TXEMPTY = (uint16_t)0x0180, /*!< Transmit Data Register Empty flag */\r
+ I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, /*!< Read Data Register Not Empty flag */\r
+ I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, /*!< Stop detected flag */\r
+ I2C_FLAG_HEADERSENT = (uint16_t)0x0108, /*!< 10-bit Header sent flag */\r
+ I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, /*!< Data Byte Transfer Finished flag */\r
+ I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, /*!< Address Sent/Matched (master/slave) flag */\r
+ I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, /*!< Start bit sent flag */\r
+\r
+ /* SR2 register flags */\r
+ I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220, /*!< Wake Up From Halt Flag */\r
+ I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, /*!< Overrun/Underrun flag */\r
+ I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, /*!< Acknowledge Failure Flag */\r
+ I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, /*!< Arbitration Loss Flag */\r
+ I2C_FLAG_BUSERROR = (uint16_t)0x0201, /*!< Misplaced Start or Stop condition */\r
+\r
+ /* SR3 register flags */\r
+ I2C_FLAG_GENERALCALL = (uint16_t)0x0310, /*!< General Call header received Flag */\r
+ I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, /*!< Transmitter Receiver Flag */\r
+ I2C_FLAG_BUSBUSY = (uint16_t)0x0302, /*!< Bus Busy Flag */\r
+ I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301 /*!< Master Slave Flag */\r
+} I2C_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief I2C Pending bits\r
+ * Elements values convention: 0xXYZZ\r
+ * X = SRx registers index\r
+ * X = 1 : SR1\r
+ * X = 2 : SR2\r
+ * Y = Position of the corresponding Interrupt\r
+ * ZZ = flag mask in the dedicated register(X register)\r
+ */\r
+\r
+typedef enum\r
+{\r
+ /* SR1 register flags */\r
+ I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, /*!< Transmit Data Register Empty */\r
+ I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, /*!< Read Data Register Not Empty */\r
+ I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, /*!< Stop detected */\r
+ I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208, /*!< 10-bit Header sent */\r
+ I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, /*!< Data Byte Transfer Finished */\r
+ I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, /*!< Address Sent/Matched (master/slave) */\r
+ I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, /*!< Start bit sent */\r
+\r
+ /* SR2 register flags */\r
+ I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220, /*!< Wake Up From Halt */\r
+ I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, /*!< Overrun/Underrun */\r
+ I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, /*!< Acknowledge Failure */\r
+ I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, /*!< Arbitration Loss */\r
+ I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101 /*!< Misplaced Start or Stop condition */\r
+} I2C_ITPendingBit_TypeDef;\r
+\r
+/**\r
+ * @brief I2C possible events\r
+ * Values convention: 0xXXYY\r
+ * XX = Event SR3 corresponding value\r
+ * YY = Event SR1 corresponding value\r
+ * @note if Event = EV3_2 the rule above does not apply\r
+ * YY = Event SR2 corresponding value\r
+ */\r
+\r
+typedef enum\r
+{\r
+ /*========================================\r
+\r
+ I2C Master Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+ /**\r
+ * @brief Communication start\r
+ *\r
+ * After sending the START condition (I2C_GenerateSTART() function) the master\r
+ * has to wait for this event. It means that the Start condition has been correctly\r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ *\r
+ */\r
+ /* --EV5 */\r
+ I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, /*!< BUSY, MSL and SB flag */\r
+\r
+ /**\r
+ * @brief Address Acknowledge\r
+ *\r
+ * After checking on EV5 (start condition correctly released on the bus), the\r
+ * master sends the address of the slave(s) with which it will communicate\r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication:\r
+ * Master transmitter or Receiver).\r
+ * Then the master has to wait that a slave acknowledges his address.\r
+ * If an acknowledge is sent on the bus, one of the following events will\r
+ * be set:\r
+ *\r
+ * 1) In case of Master Receiver (7-bit addressing):\r
+ * the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.\r
+ *\r
+ * 2) In case of Master Transmitter (7-bit addressing):\r
+ * the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set\r
+ *\r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START\r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()\r
+ * function).\r
+ * Then master should wait on EV9. It means that the 10-bit addressing\r
+ * header has been correctly sent on the bus.\r
+ * Then master should send the second part of the 10-bit address (LSB) using\r
+ * the function I2C_Send7bitAddress(). Then master should wait for event EV6.\r
+ *\r
+ */\r
+ /* --EV6 */\r
+ I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, /*!< BUSY, MSL, ADDR, TXE and TRA flags */\r
+ I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, /*!< BUSY, MSL and ADDR flags */\r
+ /* --EV9 */\r
+ I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308, /*!< BUSY, MSL and ADD10 flags */\r
+\r
+ /**\r
+ * @brief Communication events\r
+ *\r
+ * If a communication is established (START condition generated and slave address\r
+ * acknowledged) then the master has to check on one of the following events for\r
+ * communication procedures:\r
+ *\r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read\r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ *\r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()\r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar:\r
+ * - EV8 means that the data has been written in the data register and is\r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output\r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensures more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission\r
+ * (before Stop condition generation).\r
+ *\r
+ * @note In case the user software does not guarantee that this event EV7 is\r
+ * managed before the current byte end of transfer, then user may check on EV7\r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+ /* Master RECEIVER mode -----------------------------*/\r
+ /* --EV7 */\r
+ I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, /*!< BUSY, MSL and RXNE flags */\r
+\r
+ /* Master TRANSMITTER mode --------------------------*/\r
+ /* --EV8 */\r
+ I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, /*!< TRA, BUSY, MSL, TXE flags */\r
+ /* --EV8_2 */\r
+\r
+ I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+ /*========================================\r
+\r
+ I2C Slave Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+\r
+ /**\r
+ * @brief Communication start events\r
+ *\r
+ * Wait on one of these events at the start of the communication. It means that\r
+ * the I2C peripheral detected a Start condition on the bus (generated by master\r
+ * device) followed by the peripheral address.\r
+ * The peripheral generates an ACK condition on the bus (if the acknowledge\r
+ * feature is enabled through function I2C_AcknowledgeConfig()) and the events\r
+ * listed above are set :\r
+ *\r
+ * 1) In normal case (only one address managed by the slave), when the address\r
+ * sent by the master matches the own address of the peripheral (configured by\r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set\r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ *\r
+ * 2) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+ /* --EV1 (all the events below are variants of EV1) */\r
+ /* 1) Case of One Single Address managed by the slave */\r
+ I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202, /*!< BUSY and ADDR flags */\r
+ I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, /*!< TRA, BUSY, TXE and ADDR flags */\r
+\r
+ /* 2) Case of General Call enabled for the slave */\r
+ I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, /*!< EV2: GENCALL and BUSY flags */\r
+\r
+ /**\r
+ * @brief Communication events\r
+ *\r
+ * Wait on one of these events when EV1 has already been checked :\r
+ *\r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received.\r
+ * - EV4: When the application is expecting the end of the communication:\r
+ * master sends a stop condition and data transmission is stopped.\r
+ *\r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application\r
+ * is expecting the end of the byte transmission.\r
+ * The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING\r
+ * are similar. The second one can optionally be used when the user software\r
+ * doesn't guarantee the EV3 is managed before the current byte end of tranfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission\r
+ * shall end (before sending the STOP condition).\r
+ * In this case slave has to stop sending data bytes and expect a Stop\r
+ * condition on the bus.\r
+ *\r
+ * @note In case the user software does not guarantee that the event EV2 is\r
+ * managed before the current byte end of transfer, then user may check on EV2\r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+ /* Slave RECEIVER mode --------------------------*/\r
+ /* --EV2 */\r
+ I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, /*!< BUSY and RXNE flags */\r
+ /* --EV4 */\r
+ I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010, /*!< STOPF flag */\r
+\r
+ /* Slave TRANSMITTER mode -----------------------*/\r
+ /* --EV3 */\r
+ I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, /*!< TRA, BUSY, TXE and BTF flags */\r
+ I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, /*!< TRA, BUSY and TXE flags */\r
+ /* --EV3_2 */\r
+ I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 /*!< AF flag */\r
+} I2C_Event_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/** @addtogroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)\r
+#define I2C_MAX_FAST_FREQ ((uint32_t)400000)\r
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) \r
+ #define I2C_MAX_INPUT_FREQ ((uint8_t)24)\r
+#else\r
+ #define I2C_MAX_INPUT_FREQ ((uint8_t)16)\r
+#endif\r
+\r
+/**\r
+ *@}\r
+ */\r
+\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup I2C_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C duty cycles.\r
+ */\r
+#define IS_I2C_DUTYCYCLE_OK(DUTY) \\r
+ (((DUTY) == I2C_DUTYCYCLE_2) || \\r
+ ((DUTY) == I2C_DUTYCYCLE_16_9))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different acknowledgement configuration\r
+ */\r
+#define IS_I2C_ACK_OK(ACK) \\r
+ (((ACK) == I2C_ACK_NONE) || \\r
+ ((ACK) == I2C_ACK_CURR) || \\r
+ ((ACK) == I2C_ACK_NEXT))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C addressing modes.\r
+ */\r
+#define IS_I2C_ADDMODE_OK(ADDMODE) \\r
+ (((ADDMODE) == I2C_ADDMODE_7BIT) || \\r
+ ((ADDMODE) == I2C_ADDMODE_10BIT))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C interrupt types.\r
+ */\r
+#define IS_I2C_INTERRUPT_OK(IT) \\r
+ (((IT) == I2C_IT_ERR) || \\r
+ ((IT) == I2C_IT_EVT) || \\r
+ ((IT) == I2C_IT_BUF) || \\r
+ ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \\r
+ ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \\r
+ ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \\r
+ ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C communcation direction.\r
+ */\r
+#define IS_I2C_DIRECTION_OK(DIR) \\r
+ (((DIR) == I2C_DIRECTION_TX) || \\r
+ ((DIR) == I2C_DIRECTION_RX))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C flags.\r
+ */\r
+#define IS_I2C_FLAG_OK(FLAG) \\r
+ (((FLAG) == I2C_FLAG_TXEMPTY) || \\r
+ ((FLAG) == I2C_FLAG_RXNOTEMPTY) || \\r
+ ((FLAG) == I2C_FLAG_STOPDETECTION) || \\r
+ ((FLAG) == I2C_FLAG_HEADERSENT) || \\r
+ ((FLAG) == I2C_FLAG_TRANSFERFINISHED) || \\r
+ ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED) || \\r
+ ((FLAG) == I2C_FLAG_STARTDETECTION) || \\r
+ ((FLAG) == I2C_FLAG_WAKEUPFROMHALT) || \\r
+ ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN) || \\r
+ ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE) || \\r
+ ((FLAG) == I2C_FLAG_ARBITRATIONLOSS) || \\r
+ ((FLAG) == I2C_FLAG_BUSERROR) || \\r
+ ((FLAG) == I2C_FLAG_GENERALCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \\r
+ ((FLAG) == I2C_FLAG_BUSBUSY) || \\r
+ ((FLAG) == I2C_FLAG_MASTERSLAVE))\r
+/**\r
+ * @brief Macro used by the assert function to check the I2C flags to clear.\r
+ */\r
+\r
+#define IS_I2C_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \\r
+ && ((uint16_t)(FLAG) != 0x00))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C possible pending bits.\r
+ */\r
+#define IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT) \\r
+ (((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))\r
+ \r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C possible\r
+ * pending bits to clear by writing 0.\r
+ */\r
+#define IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT) \\r
+ (((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS) || \\r
+ ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))\r
+ \r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C possible events.\r
+ */\r
+#define IS_I2C_EVENT_OK(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different I2C possible own address.\r
+ */\r
+#define IS_I2C_OWN_ADDRESS_OK(ADDRESS) \\r
+ ((ADDRESS) <= (uint16_t)0x03FF)\r
+\r
+/* The address must be even */\r
+#define IS_I2C_ADDRESS_OK(ADD) \\r
+ (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.\r
+ */\r
+#define IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) \\r
+ (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.\r
+ */\r
+#define IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) \\r
+ (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+/** @addtogroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void I2C_DeInit(void);\r
+void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, \r
+ I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, \r
+ I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz );\r
+void I2C_Cmd(FunctionalState NewState);\r
+void I2C_GeneralCallCmd(FunctionalState NewState);\r
+void I2C_GenerateSTART(FunctionalState NewState);\r
+void I2C_GenerateSTOP(FunctionalState NewState);\r
+void I2C_SoftwareResetCmd(FunctionalState NewState);\r
+void I2C_StretchClockCmd(FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack);\r
+void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle);\r
+void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState);\r
+uint8_t I2C_ReceiveData(void);\r
+void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction);\r
+void I2C_SendData(uint8_t Data);\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ *\r
+ ****************************************************************************************\r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ *\r
+ *\r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1, SR2 and SR3) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags\r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applications as well as for startup\r
+ * activity since the events are fully described in the product reference manual\r
+ * (RM0016).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state.\r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ *\r
+ * @note\r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2C_IRQHandler() which is called when the I2C interurpts occur.\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the\r
+ * I2Cx_IRQHandler() function in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and\r
+ * source and return to correct communication status.\r
+ *\r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both SR1\r
+ * & SR3 status registers in a single word (uint16_t) (Status Register 3 value\r
+ * is shifted left by 8 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
+ * The returned value could be compared to events already defined in the\r
+ * library (stm8s_i2c.h) or to custom values defined by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no\r
+ * other flags are set or just when the needed flags are set like\r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this\r
+ * function if user decides to check only regular communication flags (and\r
+ * ignores error flags).\r
+ *\r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of\r
+ * one single flag (ie. I2C_FLAG_RXNE ...).\r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events\r
+ * are monitored through multiple flags).\r
+ * - Limitations:\r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one\r
+ * single event.\r
+ *\r
+ */\r
+\r
+/**\r
+ *\r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event);\r
+/**\r
+ *\r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+I2C_Event_TypeDef I2C_GetLastEvent(void);\r
+/**\r
+ *\r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag);\r
+/**\r
+ *\r
+ *******************************************************************************\r
+ */\r
+void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);\r
+void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_I2C_H */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_itc.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the ITC peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_ITC_H__\r
+#define __STM8S_ITC_H__\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup ITC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief ITC Interrupt Lines selection\r
+ */\r
+typedef enum {\r
+ ITC_IRQ_TLI = (uint8_t)0, /*!< Software interrupt */\r
+ ITC_IRQ_AWU = (uint8_t)1, /*!< Auto wake up from halt interrupt */\r
+ ITC_IRQ_CLK = (uint8_t)2, /*!< Clock controller interrupt */\r
+ ITC_IRQ_PORTA = (uint8_t)3, /*!< Port A external interrupts */\r
+ ITC_IRQ_PORTB = (uint8_t)4, /*!< Port B external interrupts */\r
+ ITC_IRQ_PORTC = (uint8_t)5, /*!< Port C external interrupts */\r
+ ITC_IRQ_PORTD = (uint8_t)6, /*!< Port D external interrupts */\r
+ ITC_IRQ_PORTE = (uint8_t)7, /*!< Port E external interrupts */\r
+ \r
+#if defined(STM8S208) || defined(STM8AF52Ax)\r
+ ITC_IRQ_CAN_RX = (uint8_t)8, /*!< beCAN RX interrupt */\r
+ ITC_IRQ_CAN_TX = (uint8_t)9, /*!< beCAN TX/ER/SC interrupt */\r
+#endif /*STM8S208 or STM8AF52Ax */\r
+\r
+#ifdef STM8S903\r
+ ITC_IRQ_PORTF = (uint8_t)8, /*!< Port F external interrupts */\r
+#endif /*STM8S903*/\r
+\r
+ ITC_IRQ_SPI = (uint8_t)10, /*!< SPI interrupt */\r
+ ITC_IRQ_TIM1_OVF = (uint8_t)11, /*!< TIM1 update/overflow/underflow/trigger/\r
+ break interrupt*/\r
+ ITC_IRQ_TIM1_CAPCOM = (uint8_t)12, /*!< TIM1 capture/compare interrupt */\r
+ \r
+#ifdef STM8S903\r
+ ITC_IRQ_TIM5_OVFTRI = (uint8_t)13, /*!< TIM5 update/overflow/underflow/trigger/\r
+ interrupt */\r
+ ITC_IRQ_TIM5_CAPCOM = (uint8_t)14, /*!< TIM5 capture/compare interrupt */\r
+#else \r
+ ITC_IRQ_TIM2_OVF = (uint8_t)13, /*!< TIM2 update /overflow interrupt */\r
+ ITC_IRQ_TIM2_CAPCOM = (uint8_t)14, /*!< TIM2 capture/compare interrupt */\r
+#endif /*STM8S903*/\r
+\r
+ ITC_IRQ_TIM3_OVF = (uint8_t)15, /*!< TIM3 update /overflow interrupt*/\r
+ ITC_IRQ_TIM3_CAPCOM = (uint8_t)16, /*!< TIM3 update /overflow interrupt */\r
+ ITC_IRQ_UART1_TX = (uint8_t)17, /*!< USART1 TX interrupt */\r
+ ITC_IRQ_UART1_RX = (uint8_t)18, /*!< USART1 RX interrupt */\r
+ ITC_IRQ_I2C = (uint8_t)19, /*!< I2C interrupt */\r
+ \r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)\r
+ ITC_IRQ_UART2_TX = (uint8_t)20, /*!< USART2 TX interrupt */\r
+ ITC_IRQ_UART2_RX = (uint8_t)21, /*!< USART2 RX interrupt */\r
+#endif /*STM8S105 or STM8AF626x */\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || defined(STM8AF62Ax)\r
+ ITC_IRQ_UART3_TX = (uint8_t)20, /*!< USART3 TX interrupt */\r
+ ITC_IRQ_UART3_RX = (uint8_t)21, /*!< USART3 RX interrupt */\r
+ ITC_IRQ_ADC2 = (uint8_t)22, /*!< ADC2 interrupt */\r
+#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || defined(STM8S903) || defined(STM8AF626x) \r
+ ITC_IRQ_ADC1 = (uint8_t)22, /*!< ADC2 interrupt */\r
+#endif /*STM8S105, STM8S103 or STM8S903 or STM8AF626x */\r
+\r
+#ifdef STM8S903\r
+ ITC_IRQ_TIM6_OVFTRI = (uint8_t)23, /*!< TIM6 update/overflow/underflow/trigger/\r
+ interrupt */\r
+#else\r
+ ITC_IRQ_TIM4_OVF = (uint8_t)23, /*!< TIM4 update /overflow interrupt */\r
+#endif /*STM8S903*/\r
+\r
+ ITC_IRQ_EEPROM_EEC = (uint8_t)24 /*!< Flash interrupt */\r
+} ITC_Irq_TypeDef;\r
+\r
+/**\r
+ * @brief ITC Priority Levels selection\r
+ */\r
+typedef enum {\r
+ ITC_PRIORITYLEVEL_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */\r
+ ITC_PRIORITYLEVEL_1 = (uint8_t)0x01, /*!< Software priority level 1 */\r
+ ITC_PRIORITYLEVEL_2 = (uint8_t)0x00, /*!< Software priority level 2 */\r
+ ITC_PRIORITYLEVEL_3 = (uint8_t)0x03 /*!< Software priority level 3 */\r
+} ITC_PriorityLevel_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+\r
+/** @addtogroup ITC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Macros used by the assert function in order to check the different functions parameters.\r
+ * @addtogroup ITC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/* Used by assert function */\r
+#define IS_ITC_IRQ_OK(IRQ) ((IRQ) <= (uint8_t)24)\r
+\r
+/* Used by assert function */\r
+#define IS_ITC_PRIORITY_OK(PriorityValue) \\r
+ (((PriorityValue) == ITC_PRIORITYLEVEL_0) || \\r
+ ((PriorityValue) == ITC_PRIORITYLEVEL_1) || \\r
+ ((PriorityValue) == ITC_PRIORITYLEVEL_2) || \\r
+ ((PriorityValue) == ITC_PRIORITYLEVEL_3))\r
+\r
+/* Used by assert function */\r
+#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup ITC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+uint8_t ITC_GetCPUCC(void);\r
+void ITC_DeInit(void);\r
+uint8_t ITC_GetSoftIntStatus(void);\r
+void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue);\r
+ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_ITC_H__ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototypes and macros for the IWDG peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_IWDG_H\r
+#define __STM8S_IWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG_Private_Define\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Define used to prevent watchdog reset\r
+ */\r
+#define IWDG_KEY_REFRESH ((uint8_t)0xAA) /*!< This value written in the Key register prevent the watchdog reset */\r
+\r
+/**\r
+ * @brief Define used to start the watchdog counter down\r
+ */\r
+#define IWDG_KEY_ENABLE ((uint8_t)0xCC) /*!< This value written in the Key register start the watchdog counting down*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different\r
+ * values of the prescaler.\r
+ */\r
+#define IS_IWDG_PRESCALER_OK(VALUE) (((VALUE) == IWDG_Prescaler_4 ) || \\r
+ ((VALUE) == IWDG_Prescaler_8 ) || \\r
+ ((VALUE) == IWDG_Prescaler_16 ) || \\r
+ ((VALUE) == IWDG_Prescaler_32 ) || \\r
+ ((VALUE) == IWDG_Prescaler_64 ) || \\r
+ ((VALUE) == IWDG_Prescaler_128 ) || \\r
+ ((VALUE) == IWDG_Prescaler_256))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different\r
+ * values of the counter register.\r
+ */\r
+#define IS_IWDG_WRITEACCESS_MODE_OK(MODE) (((MODE) == IWDG_WriteAccess_Enable) || ((MODE) == IWDG_WriteAccess_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** IWDG write acces enumeration */\r
+typedef enum\r
+{\r
+ IWDG_WriteAccess_Enable = (uint8_t)0x55, /*!< Code 0x55 in Key register, allow write access to Prescaler and Reload registers */\r
+ IWDG_WriteAccess_Disable = (uint8_t)0x00 /*!< Code 0x00 in Key register, not allow write access to Prescaler and Reload registers */\r
+} IWDG_WriteAccess_TypeDef;\r
+\r
+/** IWDG prescaler enumaration */\r
+typedef enum\r
+{\r
+ IWDG_Prescaler_4 = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */\r
+ IWDG_Prescaler_8 = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */\r
+ IWDG_Prescaler_16 = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */\r
+ IWDG_Prescaler_32 = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */\r
+ IWDG_Prescaler_64 = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */\r
+ IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */\r
+ IWDG_Prescaler_256 = (uint8_t)0x06 /*!< Used to set prescaler register to 256 */\r
+} IWDG_Prescaler_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup IWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);\r
+void IWDG_SetReload(uint8_t IWDG_Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_Enable(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_IWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_rst.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the RST peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_RST_H\r
+#define __STM8S_RST_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RST_Exported_Types\r
+ * @{\r
+ */\r
+typedef enum {\r
+ RST_FLAG_EMCF = (uint8_t)0x10, /*!< EMC reset flag */\r
+ RST_FLAG_SWIMF = (uint8_t)0x08, /*!< SWIM reset flag */\r
+ RST_FLAG_ILLOPF = (uint8_t)0x04, /*!< Illigal opcode reset flag */\r
+ RST_FLAG_IWDGF = (uint8_t)0x02, /*!< Independent watchdog reset flag */\r
+ RST_FLAG_WWDGF = (uint8_t)0x01 /*!< Window watchdog reset flag */\r
+}RST_Flag_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+\r
+/** @addtogroup RST_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+/**\r
+ * @brief Macro used by the assert function to check the different RST flags.\r
+ */\r
+#define IS_RST_FLAG_OK(FLAG) (((FLAG) == RST_FLAG_EMCF) || \\r
+ ((FLAG) == RST_FLAG_SWIMF) ||\\r
+ ((FLAG) == RST_FLAG_ILLOPF) ||\\r
+ ((FLAG) == RST_FLAG_IWDGF) ||\\r
+ ((FLAG) == RST_FLAG_WWDGF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup RST_Exported_functions\r
+ * @{\r
+ */\r
+FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag);\r
+void RST_ClearFlag(RST_Flag_TypeDef RST_Flag);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_RST_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_spi.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the SPI peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_SPI_H\r
+#define __STM8S_SPI_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief SPI data direction mode\r
+ * Warning: element values correspond to BDM, BDOE, RXONLY bits position\r
+ */\r
+typedef enum {\r
+ SPI_DATADIRECTION_2LINES_FULLDUPLEX = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */\r
+ SPI_DATADIRECTION_2LINES_RXONLY = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */\r
+ SPI_DATADIRECTION_1LINE_RX = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */\r
+ SPI_DATADIRECTION_1LINE_TX = (uint8_t)0xC0 /*!< Transmit only in 1 line bi-directional data mode */\r
+} SPI_DataDirection_TypeDef;\r
+\r
+/**\r
+ * @brief SPI Slave Select management\r
+ * Warning: element values correspond to LSBFIRST bit position\r
+ */\r
+typedef enum\r
+{\r
+ SPI_NSS_SOFT = (uint8_t)0x02, /*!< Software slave management disabled */\r
+ SPI_NSS_HARD = (uint8_t)0x00 /*!< Software slave management enabled */\r
+} SPI_NSS_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief SPI direction transmit/receive\r
+ */\r
+\r
+typedef enum {\r
+ SPI_DIRECTION_RX = (uint8_t)0x00, /*!< Selects Rx receive direction in bi-directional mode */\r
+ SPI_DIRECTION_TX = (uint8_t)0x01 /*!< Selects Tx transmission direction in bi-directional mode */\r
+} SPI_Direction_TypeDef;\r
+\r
+/**\r
+ * @brief SPI master/slave mode\r
+ * Warning: element values correspond to MSTR bit position\r
+ */\r
+typedef enum {\r
+ SPI_MODE_MASTER = (uint8_t)0x04, /*!< SPI Master configuration */\r
+ SPI_MODE_SLAVE = (uint8_t)0x00 /*!< SPI Slave configuration */\r
+} SPI_Mode_TypeDef;\r
+\r
+/**\r
+ * @brief SPI BaudRate Prescaler\r
+ * Warning: element values correspond to BR bits position\r
+ */\r
+typedef enum {\r
+ SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */\r
+ SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */\r
+ SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */\r
+ SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */\r
+ SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */\r
+ SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */\r
+ SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */\r
+ SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x38 /*!< SPI frequency = frequency(CPU)/256 */\r
+} SPI_BaudRatePrescaler_TypeDef;\r
+\r
+/**\r
+ * @brief SPI Clock Polarity\r
+ * Warning: element values correspond to CPOL bit position\r
+ */\r
+typedef enum {\r
+ SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, /*!< Clock to 0 when idle */\r
+ SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x02 /*!< Clock to 1 when idle */\r
+} SPI_ClockPolarity_TypeDef;\r
+\r
+/**\r
+ * @brief SPI Clock Phase\r
+ * Warning: element values correspond to CPHA bit position\r
+ */\r
+typedef enum {\r
+ SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */\r
+ SPI_CLOCKPHASE_2EDGE = (uint8_t)0x01 /*!< The second clock transition is the first data capture edge */\r
+} SPI_ClockPhase_TypeDef;\r
+\r
+/**\r
+ * @brief SPI Frame Format: MSB or LSB transmitted first\r
+ * Warning: element values correspond to LSBFIRST bit position\r
+ */\r
+typedef enum {\r
+ SPI_FIRSTBIT_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */\r
+ SPI_FIRSTBIT_LSB = (uint8_t)0x80 /*!< LSB bit will be transmitted first */\r
+} SPI_FirstBit_TypeDef;\r
+\r
+/**\r
+ * @brief SPI CRC Transmit/Receive\r
+ */\r
+typedef enum {\r
+ SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */\r
+ SPI_CRC_TX = (uint8_t)0x01 /*!< Select Rx CRC register */\r
+} SPI_CRC_TypeDef;\r
+\r
+/**\r
+ * @brief SPI flags definition - Warning : FLAG value = mapping position register\r
+ */\r
+typedef enum {\r
+ SPI_FLAG_BSY = (uint8_t)0x80, /*!< Busy flag */\r
+ SPI_FLAG_OVR = (uint8_t)0x40, /*!< Overrun flag */\r
+ SPI_FLAG_MODF = (uint8_t)0x20, /*!< Mode fault */\r
+ SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */\r
+ SPI_FLAG_WKUP = (uint8_t)0x08, /*!< Wake-up flag */\r
+ SPI_FLAG_TXE = (uint8_t)0x02, /*!< Transmit buffer empty */\r
+ SPI_FLAG_RXNE = (uint8_t)0x01 /*!< Receive buffer empty */\r
+} SPI_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief SPI_IT possible values\r
+ * Elements values convention: 0xYX\r
+ * X: Position of the corresponding Interrupt\r
+ * Y: ITPENDINGBIT position\r
+ */\r
+typedef enum\r
+{\r
+ SPI_IT_WKUP = (uint8_t)0x34, /*!< Wake-up interrupt*/\r
+ SPI_IT_OVR = (uint8_t)0x65, /*!< Overrun interrupt*/\r
+ SPI_IT_MODF = (uint8_t)0x55, /*!< Mode fault interrupt*/\r
+ SPI_IT_CRCERR = (uint8_t)0x45, /*!< CRC error interrupt*/\r
+ SPI_IT_TXE = (uint8_t)0x17, /*!< Transmit buffer empty interrupt*/\r
+ SPI_IT_RXNE = (uint8_t)0x06, /*!< Receive buffer not empty interrupt*/\r
+ SPI_IT_ERR = (uint8_t)0x05 /*!< Error interrupt*/\r
+} SPI_IT_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+/** @addtogroup SPI_Private_Macros\r
+ * @brief Macros used by the assert_param function to check the different functions parameters.\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the data direction mode values\r
+ */\r
+#define IS_SPI_DATA_DIRECTION_OK(MODE) (((MODE) == SPI_DATADIRECTION_2LINES_FULLDUPLEX) || \\r
+ ((MODE) == SPI_DATADIRECTION_2LINES_RXONLY) || \\r
+ ((MODE) == SPI_DATADIRECTION_1LINE_RX) || \\r
+ ((MODE) == SPI_DATADIRECTION_1LINE_TX))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the mode \r
+ * half duplex data direction values\r
+ */\r
+#define IS_SPI_DIRECTION_OK(DIRECTION) (((DIRECTION) == SPI_DIRECTION_RX) || \\r
+ ((DIRECTION) == SPI_DIRECTION_TX))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the NSS \r
+ * management values\r
+ */\r
+#define IS_SPI_SLAVEMANAGEMENT_OK(NSS) (((NSS) == SPI_NSS_SOFT) || \\r
+ ((NSS) == SPI_NSS_HARD))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the CRC polynomial\r
+ */\r
+#define IS_SPI_CRC_POLYNOMIAL_OK(POLYNOMIAL) ((POLYNOMIAL) > (uint8_t)0x00)\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the SPI Mode values\r
+ */\r
+#define IS_SPI_MODE_OK(MODE) (((MODE) == SPI_MODE_MASTER) || \\r
+ ((MODE) == SPI_MODE_SLAVE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the baudrate values\r
+ */\r
+#define IS_SPI_BAUDRATE_PRESCALER_OK(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\r
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the polarity values\r
+ */\r
+#define IS_SPI_POLARITY_OK(CLKPOL) (((CLKPOL) == SPI_CLOCKPOLARITY_LOW) || \\r
+ ((CLKPOL) == SPI_CLOCKPOLARITY_HIGH))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the phase values\r
+ */\r
+#define IS_SPI_PHASE_OK(CLKPHA) (((CLKPHA) == SPI_CLOCKPHASE_1EDGE) || \\r
+ ((CLKPHA) == SPI_CLOCKPHASE_2EDGE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the first \r
+ * bit to be transmited values\r
+ */\r
+#define IS_SPI_FIRSTBIT_OK(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\r
+ ((BIT) == SPI_FIRSTBIT_LSB))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the CRC \r
+ * Transmit/Receive\r
+ */\r
+#define IS_SPI_CRC_OK(CRC) (((CRC) == SPI_CRC_TX) || \\r
+ ((CRC) == SPI_CRC_RX))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different flags values\r
+ */\r
+#define IS_SPI_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || \\r
+ ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == SPI_FLAG_WKUP) || \\r
+ ((FLAG) == SPI_FLAG_TXE) || \\r
+ ((FLAG) == SPI_FLAG_RXNE) || \\r
+ ((FLAG) == SPI_FLAG_BSY))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the flag that can be cleared \r
+ * by writing 0\r
+ */\r
+#define IS_SPI_CLEAR_FLAGS_OK(FLAG) (((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == SPI_FLAG_WKUP))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the Interrupts\r
+ */\r
+#define IS_SPI_CONFIG_IT_OK(Interrupt) (((Interrupt) == SPI_IT_TXE) || \\r
+ ((Interrupt) == SPI_IT_RXNE) || \\r
+ ((Interrupt) == SPI_IT_ERR) || \\r
+ ((Interrupt) == SPI_IT_WKUP))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the pending bit\r
+ */\r
+#define IS_SPI_GET_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR) || \\r
+ ((ITPendingBit) == SPI_IT_MODF) || \\r
+ ((ITPendingBit) == SPI_IT_CRCERR) || \\r
+ ((ITPendingBit) == SPI_IT_WKUP) || \\r
+ ((ITPendingBit) == SPI_IT_TXE) || \\r
+ ((ITPendingBit) == SPI_IT_RXNE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the pending bit that can be cleared\r
+ * by writing 0\r
+ */\r
+#define IS_SPI_CLEAR_IT_OK(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \\r
+ ((ITPendingBit) == SPI_IT_WKUP))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Exported_Functions\r
+ * @{\r
+ */\r
+void SPI_DeInit(void);\r
+void SPI_Init(SPI_FirstBit_TypeDef FirstBit, \r
+ SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, \r
+ SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, \r
+ SPI_ClockPhase_TypeDef ClockPhase, \r
+ SPI_DataDirection_TypeDef Data_Direction, \r
+ SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial);\r
+void SPI_Cmd(FunctionalState NewState);\r
+void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState);\r
+void SPI_SendData(uint8_t Data);\r
+uint8_t SPI_ReceiveData(void);\r
+void SPI_NSSInternalSoftwareCmd(FunctionalState NewState);\r
+void SPI_TransmitCRC(void);\r
+void SPI_CalculateCRCCmd(FunctionalState NewState);\r
+uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC);\r
+void SPI_ResetCRC(void);\r
+uint8_t SPI_GetCRCPolynomial(void);\r
+void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction);\r
+FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG);\r
+void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG);\r
+ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT);\r
+void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_SPI_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim1.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM1_H\r
+#define __STM8S_TIM1_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup TIM1_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** TIM1 Output Compare and PWM modes */\r
+\r
+typedef enum\r
+{\r
+ TIM1_OCMODE_TIMING = ((uint8_t)0x00),\r
+ TIM1_OCMODE_ACTIVE = ((uint8_t)0x10),\r
+ TIM1_OCMODE_INACTIVE = ((uint8_t)0x20),\r
+ TIM1_OCMODE_TOGGLE = ((uint8_t)0x30),\r
+ TIM1_OCMODE_PWM1 = ((uint8_t)0x60),\r
+ TIM1_OCMODE_PWM2 = ((uint8_t)0x70)\r
+}TIM1_OCMode_TypeDef;\r
+\r
+#define IS_TIM1_OC_MODE_OK(MODE) (((MODE) == TIM1_OCMODE_TIMING) || \\r
+ ((MODE) == TIM1_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM1_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM1_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM1_OCMODE_PWM1) || \\r
+ ((MODE) == TIM1_OCMODE_PWM2))\r
+\r
+#define IS_TIM1_OCM_OK(MODE)(((MODE) == TIM1_OCMODE_TIMING) || \\r
+ ((MODE) == TIM1_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM1_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM1_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM1_OCMODE_PWM1) || \\r
+ ((MODE) == TIM1_OCMODE_PWM2) || \\r
+ ((MODE) == (uint8_t)TIM1_FORCEDACTION_ACTIVE) || \\r
+ ((MODE) == (uint8_t)TIM1_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM1 One Pulse Mode */\r
+typedef enum\r
+{\r
+ TIM1_OPMODE_SINGLE = ((uint8_t)0x01),\r
+ TIM1_OPMODE_REPETITIVE = ((uint8_t)0x00)\r
+}TIM1_OPMode_TypeDef;\r
+\r
+#define IS_TIM1_OPM_MODE_OK(MODE) (((MODE) == TIM1_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM1_OPMODE_REPETITIVE))\r
+\r
+/** TIM1 Channel */\r
+\r
+typedef enum\r
+{\r
+ TIM1_CHANNEL_1 = ((uint8_t)0x00),\r
+ TIM1_CHANNEL_2 = ((uint8_t)0x01),\r
+ TIM1_CHANNEL_3 = ((uint8_t)0x02),\r
+ TIM1_CHANNEL_4 = ((uint8_t)0x03)\r
+}TIM1_Channel_TypeDef;\r
+\r
+\r
+#define IS_TIM1_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_3) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_4))\r
+\r
+#define IS_TIM1_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_2))\r
+\r
+#define IS_TIM1_COMPLEMENTARY_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM1_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM1_CHANNEL_3))\r
+\r
+\r
+/** TIM1 Counter Mode */\r
+typedef enum\r
+{\r
+ TIM1_COUNTERMODE_UP = ((uint8_t)0x00),\r
+ TIM1_COUNTERMODE_DOWN = ((uint8_t)0x10),\r
+ TIM1_COUNTERMODE_CENTERALIGNED1 = ((uint8_t)0x20),\r
+ TIM1_COUNTERMODE_CENTERALIGNED2 = ((uint8_t)0x40),\r
+ TIM1_COUNTERMODE_CENTERALIGNED3 = ((uint8_t)0x60)\r
+}TIM1_CounterMode_TypeDef;\r
+\r
+#define IS_TIM1_COUNTER_MODE_OK(MODE) (((MODE) == TIM1_COUNTERMODE_UP) || \\r
+ ((MODE) == TIM1_COUNTERMODE_DOWN) || \\r
+ ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED1) || \\r
+ ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED2) || \\r
+ ((MODE) == TIM1_COUNTERMODE_CENTERALIGNED3))\r
+\r
+/** TIM1 Output Compare Polarity */\r
+typedef enum\r
+{\r
+ TIM1_OCPOLARITY_HIGH = ((uint8_t)0x00),\r
+ TIM1_OCPOLARITY_LOW = ((uint8_t)0x22)\r
+}TIM1_OCPolarity_TypeDef;\r
+\r
+#define IS_TIM1_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCPOLARITY_HIGH) || \\r
+ ((POLARITY) == TIM1_OCPOLARITY_LOW))\r
+\r
+/** TIM1 Output Compare N Polarity */\r
+typedef enum\r
+{\r
+ TIM1_OCNPOLARITY_HIGH = ((uint8_t)0x00),\r
+ TIM1_OCNPOLARITY_LOW = ((uint8_t)0x88)\r
+}TIM1_OCNPolarity_TypeDef;\r
+\r
+#define IS_TIM1_OCN_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_OCNPOLARITY_HIGH) || \\r
+ ((POLARITY) == TIM1_OCNPOLARITY_LOW))\r
+\r
+/** TIM1 Output Compare states */\r
+typedef enum\r
+{\r
+ TIM1_OUTPUTSTATE_DISABLE = ((uint8_t)0x00),\r
+ TIM1_OUTPUTSTATE_ENABLE = ((uint8_t)0x11)\r
+}TIM1_OutputState_TypeDef;\r
+\r
+#define IS_TIM1_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM1_OUTPUTSTATE_ENABLE))\r
+\r
+/** TIM1 Output Compare N States */\r
+typedef enum\r
+{\r
+ TIM1_OUTPUTNSTATE_DISABLE = ((uint8_t)0x00),\r
+ TIM1_OUTPUTNSTATE_ENABLE = ((uint8_t)0x44)\r
+} TIM1_OutputNState_TypeDef;\r
+\r
+#define IS_TIM1_OUTPUTN_STATE_OK(STATE) (((STATE) == TIM1_OUTPUTNSTATE_DISABLE) ||\\r
+ ((STATE) == TIM1_OUTPUTNSTATE_ENABLE))\r
+\r
+/** TIM1 Break Input enable/disable */\r
+typedef enum\r
+{\r
+ TIM1_BREAK_ENABLE = ((uint8_t)0x10),\r
+ TIM1_BREAK_DISABLE = ((uint8_t)0x00)\r
+}TIM1_BreakState_TypeDef;\r
+#define IS_TIM1_BREAK_STATE_OK(STATE) (((STATE) == TIM1_BREAK_ENABLE) || \\r
+ ((STATE) == TIM1_BREAK_DISABLE))\r
+\r
+/** TIM1 Break Polarity */\r
+typedef enum\r
+{\r
+ TIM1_BREAKPOLARITY_LOW = ((uint8_t)0x00),\r
+ TIM1_BREAKPOLARITY_HIGH = ((uint8_t)0x20)\r
+}TIM1_BreakPolarity_TypeDef;\r
+#define IS_TIM1_BREAK_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_BREAKPOLARITY_LOW) || \\r
+ ((POLARITY) == TIM1_BREAKPOLARITY_HIGH))\r
+\r
+/** TIM1 AOE Bit Set/Reset */\r
+typedef enum\r
+{\r
+ TIM1_AUTOMATICOUTPUT_ENABLE = ((uint8_t)0x40),\r
+ TIM1_AUTOMATICOUTPUT_DISABLE = ((uint8_t)0x00)\r
+}TIM1_AutomaticOutput_TypeDef;\r
+\r
+#define IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(STATE) (((STATE) == TIM1_AUTOMATICOUTPUT_ENABLE) || \\r
+ ((STATE) == TIM1_AUTOMATICOUTPUT_DISABLE))\r
+\r
+/** TIM1 Lock levels */\r
+typedef enum\r
+{\r
+ TIM1_LOCKLEVEL_OFF = ((uint8_t)0x00),\r
+ TIM1_LOCKLEVEL_1 = ((uint8_t)0x01),\r
+ TIM1_LOCKLEVEL_2 = ((uint8_t)0x02),\r
+ TIM1_LOCKLEVEL_3 = ((uint8_t)0x03)\r
+}TIM1_LockLevel_TypeDef;\r
+\r
+#define IS_TIM1_LOCK_LEVEL_OK(LEVEL) (((LEVEL) == TIM1_LOCKLEVEL_OFF) || \\r
+ ((LEVEL) == TIM1_LOCKLEVEL_1) || \\r
+ ((LEVEL) == TIM1_LOCKLEVEL_2) || \\r
+ ((LEVEL) == TIM1_LOCKLEVEL_3))\r
+\r
+/** TIM1 OSSI: Off-State Selection for Idle mode states */\r
+typedef enum\r
+{\r
+ TIM1_OSSISTATE_ENABLE = ((uint8_t)0x04),\r
+ TIM1_OSSISTATE_DISABLE = ((uint8_t)0x00)\r
+}TIM1_OSSIState_TypeDef;\r
+\r
+#define IS_TIM1_OSSI_STATE_OK(STATE) (((STATE) == TIM1_OSSISTATE_ENABLE) || \\r
+ ((STATE) == TIM1_OSSISTATE_DISABLE))\r
+\r
+/** TIM1 Output Compare Idle State */\r
+typedef enum\r
+{\r
+ TIM1_OCIDLESTATE_SET = ((uint8_t)0x55),\r
+ TIM1_OCIDLESTATE_RESET = ((uint8_t)0x00)\r
+}TIM1_OCIdleState_TypeDef;\r
+\r
+#define IS_TIM1_OCIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCIDLESTATE_SET) || \\r
+ ((STATE) == TIM1_OCIDLESTATE_RESET))\r
+\r
+/** TIM1 Output Compare N Idle State */\r
+typedef enum\r
+{\r
+ TIM1_OCNIDLESTATE_SET = ((uint8_t)0x2A),\r
+ TIM1_OCNIDLESTATE_RESET = ((uint8_t)0x00)\r
+}TIM1_OCNIdleState_TypeDef;\r
+\r
+#define IS_TIM1_OCNIDLE_STATE_OK(STATE) (((STATE) == TIM1_OCNIDLESTATE_SET) || \\r
+ ((STATE) == TIM1_OCNIDLESTATE_RESET))\r
+\r
+/** TIM1 Input Capture Polarity */\r
+typedef enum\r
+{\r
+ TIM1_ICPOLARITY_RISING = ((uint8_t)0x00),\r
+ TIM1_ICPOLARITY_FALLING = ((uint8_t)0x01)\r
+}TIM1_ICPolarity_TypeDef;\r
+\r
+#define IS_TIM1_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_ICPOLARITY_RISING) || \\r
+ ((POLARITY) == TIM1_ICPOLARITY_FALLING))\r
+\r
+/** TIM1 Input Capture Selection */\r
+typedef enum\r
+{\r
+ TIM1_ICSELECTION_DIRECTTI = ((uint8_t)0x01),\r
+ TIM1_ICSELECTION_INDIRECTTI = ((uint8_t)0x02),\r
+ TIM1_ICSELECTION_TRGI = ((uint8_t)0x03)\r
+}TIM1_ICSelection_TypeDef;\r
+\r
+#define IS_TIM1_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM1_ICSELECTION_INDIRECTTI) || \\r
+ ((SELECTION) == TIM1_ICSELECTION_TRGI))\r
+\r
+/** TIM1 Input Capture Prescaler */\r
+typedef enum\r
+{\r
+ TIM1_ICPSC_DIV1 = ((uint8_t)0x00),\r
+ TIM1_ICPSC_DIV2 = ((uint8_t)0x04),\r
+ TIM1_ICPSC_DIV4 = ((uint8_t)0x08),\r
+ TIM1_ICPSC_DIV8 = ((uint8_t)0x0C)\r
+}TIM1_ICPSC_TypeDef;\r
+\r
+#define IS_TIM1_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM1_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM1_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM1_ICPSC_DIV8))\r
+\r
+/** TIM1 Input Capture Filer Value */\r
+\r
+#define IS_TIM1_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)\r
+\r
+/** TIM1 External Trigger Filer Value */\r
+#define IS_TIM1_EXT_TRG_FILTER_OK(FILTER) ((FILTER) <= 0x0F)\r
+\r
+/** TIM1 interrupt sources */\r
+typedef enum\r
+{\r
+ TIM1_IT_UPDATE = ((uint8_t)0x01),\r
+ TIM1_IT_CC1 = ((uint8_t)0x02),\r
+ TIM1_IT_CC2 = ((uint8_t)0x04),\r
+ TIM1_IT_CC3 = ((uint8_t)0x08),\r
+ TIM1_IT_CC4 = ((uint8_t)0x10),\r
+ TIM1_IT_COM = ((uint8_t)0x20),\r
+ TIM1_IT_TRIGGER = ((uint8_t)0x40),\r
+ TIM1_IT_BREAK = ((uint8_t)0x80)\r
+}TIM1_IT_TypeDef;\r
+\r
+#define IS_TIM1_IT_OK(IT) ((IT) != 0x00)\r
+\r
+#define IS_TIM1_GET_IT_OK(IT) (((IT) == TIM1_IT_UPDATE) || \\r
+ ((IT) == TIM1_IT_CC1) || \\r
+ ((IT) == TIM1_IT_CC2) || \\r
+ ((IT) == TIM1_IT_CC3) || \\r
+ ((IT) == TIM1_IT_CC4) || \\r
+ ((IT) == TIM1_IT_COM) || \\r
+ ((IT) == TIM1_IT_TRIGGER) || \\r
+ ((IT) == TIM1_IT_BREAK))\r
+\r
+\r
+/** TIM1 External Trigger Prescaler */\r
+typedef enum\r
+{\r
+ TIM1_EXTTRGPSC_OFF = ((uint8_t)0x00),\r
+ TIM1_EXTTRGPSC_DIV2 = ((uint8_t)0x10),\r
+ TIM1_EXTTRGPSC_DIV4 = ((uint8_t)0x20),\r
+ TIM1_EXTTRGPSC_DIV8 = ((uint8_t)0x30)\r
+}TIM1_ExtTRGPSC_TypeDef;\r
+\r
+#define IS_TIM1_EXT_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM1_EXTTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM1_EXTTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM1_EXTTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM1_EXTTRGPSC_DIV8))\r
+\r
+/** TIM1 Internal Trigger Selection */\r
+typedef enum\r
+{\r
+ TIM1_TS_TIM6 = ((uint8_t)0x00), /*!< TRIG Input source = TIM6 TRIG Output */\r
+ TIM1_TS_TIM5 = ((uint8_t)0x30), /*!< TRIG Input source = TIM5 TRIG Output */\r
+ TIM1_TS_TI1F_ED = ((uint8_t)0x40),\r
+ TIM1_TS_TI1FP1 = ((uint8_t)0x50),\r
+ TIM1_TS_TI2FP2 = ((uint8_t)0x60),\r
+ TIM1_TS_ETRF = ((uint8_t)0x70)\r
+}TIM1_TS_TypeDef;\r
+\r
+#define IS_TIM1_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM1_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM1_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM1_TS_ETRF) || \\r
+ ((SELECTION) == TIM1_TS_TIM5) || \\r
+ ((SELECTION) == TIM1_TS_TIM6))\r
+\r
+\r
+#define IS_TIM1_TIX_TRIGGER_SELECTION_OK(SELECTION) (((SELECTION) == TIM1_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM1_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM1_TS_TI2FP2))\r
+\r
+/** TIM1 TIx External Clock Source */\r
+typedef enum\r
+{\r
+ TIM1_TIXEXTERNALCLK1SOURCE_TI1ED = ((uint8_t)0x40),\r
+ TIM1_TIXEXTERNALCLK1SOURCE_TI1 = ((uint8_t)0x50),\r
+ TIM1_TIXEXTERNALCLK1SOURCE_TI2 = ((uint8_t)0x60)\r
+}TIM1_TIxExternalCLK1Source_TypeDef;\r
+\r
+#define IS_TIM1_TIXCLK_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1ED) || \\r
+ ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI2) || \\r
+ ((SOURCE) == TIM1_TIXEXTERNALCLK1SOURCE_TI1))\r
+\r
+/** TIM1 External Trigger Polarity */\r
+typedef enum\r
+{\r
+ TIM1_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80),\r
+ TIM1_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00)\r
+}TIM1_ExtTRGPolarity_TypeDef;\r
+\r
+#define IS_TIM1_EXT_POLARITY_OK(POLARITY) (((POLARITY) == TIM1_EXTTRGPOLARITY_INVERTED) || \\r
+ ((POLARITY) == TIM1_EXTTRGPOLARITY_NONINVERTED))\r
+\r
+/** TIM1 Prescaler Reload Mode */\r
+typedef enum\r
+{\r
+ TIM1_PSCRELOADMODE_UPDATE = ((uint8_t)0x00),\r
+ TIM1_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01)\r
+}TIM1_PSCReloadMode_TypeDef;\r
+\r
+#define IS_TIM1_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM1_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM1_PSCRELOADMODE_IMMEDIATE))\r
+\r
+/** TIM1 Encoder Mode */\r
+typedef enum\r
+{\r
+ TIM1_ENCODERMODE_TI1 = ((uint8_t)0x01),\r
+ TIM1_ENCODERMODE_TI2 = ((uint8_t)0x02),\r
+ TIM1_ENCODERMODE_TI12 = ((uint8_t)0x03)\r
+}TIM1_EncoderMode_TypeDef;\r
+\r
+#define IS_TIM1_ENCODER_MODE_OK(MODE) (((MODE) == TIM1_ENCODERMODE_TI1) || \\r
+ ((MODE) == TIM1_ENCODERMODE_TI2) || \\r
+ ((MODE) == TIM1_ENCODERMODE_TI12))\r
+\r
+/** TIM1 Event Source */\r
+typedef enum\r
+{\r
+ TIM1_EVENTSOURCE_UPDATE = ((uint8_t)0x01),\r
+ TIM1_EVENTSOURCE_CC1 = ((uint8_t)0x02),\r
+ TIM1_EVENTSOURCE_CC2 = ((uint8_t)0x04),\r
+ TIM1_EVENTSOURCE_CC3 = ((uint8_t)0x08),\r
+ TIM1_EVENTSOURCE_CC4 = ((uint8_t)0x10),\r
+ TIM1_EVENTSOURCE_COM = ((uint8_t)0x20),\r
+ TIM1_EVENTSOURCE_TRIGGER = ((uint8_t)0x40),\r
+ TIM1_EVENTSOURCE_BREAK = ((uint8_t)0x80)\r
+}TIM1_EventSource_TypeDef;\r
+\r
+#define IS_TIM1_EVENT_SOURCE_OK(SOURCE) ((SOURCE) != 0x00)\r
+\r
+/** TIM1 Update Source */\r
+typedef enum\r
+{\r
+ TIM1_UPDATESOURCE_GLOBAL = ((uint8_t)0x00),\r
+ TIM1_UPDATESOURCE_REGULAR = ((uint8_t)0x01)\r
+}TIM1_UpdateSource_TypeDef;\r
+\r
+#define IS_TIM1_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM1_UPDATESOURCE_REGULAR))\r
+\r
+/** TIM1 Trigger Output Source */\r
+typedef enum\r
+{\r
+ TIM1_TRGOSOURCE_RESET = ((uint8_t)0x00),\r
+ TIM1_TRGOSOURCE_ENABLE = ((uint8_t)0x10),\r
+ TIM1_TRGOSOURCE_UPDATE = ((uint8_t)0x20),\r
+ TIM1_TRGOSource_OC1 = ((uint8_t)0x30),\r
+ TIM1_TRGOSOURCE_OC1REF = ((uint8_t)0x40),\r
+ TIM1_TRGOSOURCE_OC2REF = ((uint8_t)0x50),\r
+ TIM1_TRGOSOURCE_OC3REF = ((uint8_t)0x60)\r
+}TIM1_TRGOSource_TypeDef;\r
+\r
+#define IS_TIM1_TRGO_SOURCE_OK(SOURCE) (((SOURCE) == TIM1_TRGOSOURCE_RESET) || \\r
+ ((SOURCE) == TIM1_TRGOSOURCE_ENABLE) || \\r
+ ((SOURCE) == TIM1_TRGOSOURCE_UPDATE) || \\r
+ ((SOURCE) == TIM1_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM1_TRGOSOURCE_OC1REF) || \\r
+ ((SOURCE) == TIM1_TRGOSOURCE_OC2REF) || \\r
+ ((SOURCE) == TIM1_TRGOSOURCE_OC3REF))\r
+\r
+/** TIM1 Slave Mode */\r
+typedef enum\r
+{\r
+ TIM1_SLAVEMODE_RESET = ((uint8_t)0x04),\r
+ TIM1_SLAVEMODE_GATED = ((uint8_t)0x05),\r
+ TIM1_SLAVEMODE_TRIGGER = ((uint8_t)0x06),\r
+ TIM1_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07)\r
+}TIM1_SlaveMode_TypeDef;\r
+\r
+#define IS_TIM1_SLAVE_MODE_OK(MODE) (((MODE) == TIM1_SLAVEMODE_RESET) || \\r
+ ((MODE) == TIM1_SLAVEMODE_GATED) || \\r
+ ((MODE) == TIM1_SLAVEMODE_TRIGGER) || \\r
+ ((MODE) == TIM1_SLAVEMODE_EXTERNAL1))\r
+\r
+/** TIM1 Flags */\r
+typedef enum\r
+{\r
+ TIM1_FLAG_UPDATE = ((uint16_t)0x0001),\r
+ TIM1_FLAG_CC1 = ((uint16_t)0x0002),\r
+ TIM1_FLAG_CC2 = ((uint16_t)0x0004),\r
+ TIM1_FLAG_CC3 = ((uint16_t)0x0008),\r
+ TIM1_FLAG_CC4 = ((uint16_t)0x0010),\r
+ TIM1_FLAG_COM = ((uint16_t)0x0020),\r
+ TIM1_FLAG_TRIGGER = ((uint16_t)0x0040),\r
+ TIM1_FLAG_BREAK = ((uint16_t)0x0080),\r
+ TIM1_FLAG_CC1OF = ((uint16_t)0x0200),\r
+ TIM1_FLAG_CC2OF = ((uint16_t)0x0400),\r
+ TIM1_FLAG_CC3OF = ((uint16_t)0x0800),\r
+ TIM1_FLAG_CC4OF = ((uint16_t)0x1000)\r
+}TIM1_FLAG_TypeDef;\r
+\r
+#define IS_TIM1_GET_FLAG_OK(FLAG) (((FLAG) == TIM1_FLAG_UPDATE) || \\r
+ ((FLAG) == TIM1_FLAG_CC1) || \\r
+ ((FLAG) == TIM1_FLAG_CC2) || \\r
+ ((FLAG) == TIM1_FLAG_CC3) || \\r
+ ((FLAG) == TIM1_FLAG_CC4) || \\r
+ ((FLAG) == TIM1_FLAG_COM) || \\r
+ ((FLAG) == TIM1_FLAG_TRIGGER) || \\r
+ ((FLAG) == TIM1_FLAG_BREAK) || \\r
+ ((FLAG) == TIM1_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM1_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM1_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM1_FLAG_CC4OF))\r
+\r
+#define IS_TIM1_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))\r
+\r
+/** TIM1 Forced Action */\r
+typedef enum\r
+{\r
+ TIM1_FORCEDACTION_ACTIVE = ((uint8_t)0x50),\r
+ TIM1_FORCEDACTION_INACTIVE = ((uint8_t)0x40)\r
+}TIM1_ForcedAction_TypeDef;\r
+\r
+#define IS_TIM1_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM1_FORCEDACTION_ACTIVE) || \\r
+ ((ACTION) == TIM1_FORCEDACTION_INACTIVE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM1_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM1_DeInit(void);\r
+void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler, \r
+ TIM1_CounterMode_TypeDef TIM1_CounterMode,\r
+ uint16_t TIM1_Period, uint8_t TIM1_RepetitionCounter);\r
+void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, \r
+ TIM1_OutputState_TypeDef TIM1_OutputState, \r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState, \r
+ uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, \r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, \r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState, \r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);\r
+void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode, \r
+ TIM1_OutputState_TypeDef TIM1_OutputState, \r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState, \r
+ uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, \r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, \r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState, \r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);\r
+void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode, \r
+ TIM1_OutputState_TypeDef TIM1_OutputState, \r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState, \r
+ uint16_t TIM1_Pulse, TIM1_OCPolarity_TypeDef TIM1_OCPolarity, \r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, \r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState, \r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState);\r
+void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode, \r
+ TIM1_OutputState_TypeDef TIM1_OutputState, uint16_t TIM1_Pulse,\r
+ TIM1_OCPolarity_TypeDef TIM1_OCPolarity, \r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState);\r
+void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState, \r
+ TIM1_LockLevel_TypeDef TIM1_LockLevel, uint8_t TIM1_DeadTime,\r
+ TIM1_BreakState_TypeDef TIM1_Break, \r
+ TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, \r
+ TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput);\r
+void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel, \r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity, \r
+ TIM1_ICSelection_TypeDef TIM1_ICSelection, \r
+ TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);\r
+void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel, \r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity, \r
+ TIM1_ICSelection_TypeDef TIM1_ICSelection, \r
+ TIM1_ICPSC_TypeDef TIM1_ICPrescaler, uint8_t TIM1_ICFilter);\r
+void TIM1_Cmd(FunctionalState NewState);\r
+void TIM1_CtrlPWMOutputs(FunctionalState NewState);\r
+void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState);\r
+void TIM1_InternalClockConfig(void);\r
+void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, \r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, \r
+ uint8_t ExtTRGFilter);\r
+void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, \r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, \r
+ uint8_t ExtTRGFilter);\r
+void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, \r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, \r
+ uint8_t ExtTRGFilter);\r
+void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, \r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity, \r
+ uint8_t ICFilter);\r
+void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource);\r
+void TIM1_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource);\r
+void TIM1_SelectHallSensor(FunctionalState NewState);\r
+void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode);\r
+void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource);\r
+void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode);\r
+void TIM1_SelectMasterSlaveMode(FunctionalState NewState);\r
+void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode, \r
+ TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, \r
+ TIM1_ICPolarity_TypeDef TIM1_IC2Polarity);\r
+void TIM1_PrescalerConfig(uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode);\r
+void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode);\r
+void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);\r
+void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);\r
+void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);\r
+void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction);\r
+void TIM1_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM1_SelectCOM(FunctionalState NewState);\r
+void TIM1_CCPreloadControl(FunctionalState NewState);\r
+void TIM1_OC1PreloadConfig(FunctionalState NewState);\r
+void TIM1_OC2PreloadConfig(FunctionalState NewState);\r
+void TIM1_OC3PreloadConfig(FunctionalState NewState);\r
+void TIM1_OC4PreloadConfig(FunctionalState NewState);\r
+void TIM1_OC1FastConfig(FunctionalState NewState);\r
+void TIM1_OC2FastConfig(FunctionalState NewState);\r
+void TIM1_OC3FastConfig(FunctionalState NewState);\r
+void TIM1_OC4FastConfig(FunctionalState NewState);\r
+void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource);\r
+void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);\r
+void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);\r
+void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);\r
+void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);\r
+void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);\r
+void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity);\r
+void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity);\r
+void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);\r
+void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState);\r
+void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode);\r
+void TIM1_SetCounter(uint16_t Counter);\r
+void TIM1_SetAutoreload(uint16_t Autoreload);\r
+void TIM1_SetCompare1(uint16_t Compare1);\r
+void TIM1_SetCompare2(uint16_t Compare2);\r
+void TIM1_SetCompare3(uint16_t Compare3);\r
+void TIM1_SetCompare4(uint16_t Compare4);\r
+void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler);\r
+void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler);\r
+void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler);\r
+void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler);\r
+uint16_t TIM1_GetCapture1(void);\r
+uint16_t TIM1_GetCapture2(void);\r
+uint16_t TIM1_GetCapture3(void);\r
+uint16_t TIM1_GetCapture4(void);\r
+uint16_t TIM1_GetCounter(void);\r
+uint16_t TIM1_GetPrescaler(void);\r
+FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG);\r
+void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG);\r
+ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT);\r
+void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM1_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim2.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM2_H\r
+#define __STM8S_TIM2_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+\r
+/** TIM2 Forced Action */\r
+typedef enum\r
+{\r
+ TIM2_FORCEDACTION_ACTIVE = ((uint8_t)0x50),\r
+ TIM2_FORCEDACTION_INACTIVE = ((uint8_t)0x40)\r
+}TIM2_ForcedAction_TypeDef;\r
+\r
+#define IS_TIM2_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM2_FORCEDACTION_ACTIVE) || \\r
+ ((ACTION) == TIM2_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM2 Prescaler */\r
+typedef enum\r
+{\r
+ TIM2_PRESCALER_1 = ((uint8_t)0x00),\r
+ TIM2_PRESCALER_2 = ((uint8_t)0x01),\r
+ TIM2_PRESCALER_4 = ((uint8_t)0x02),\r
+ TIM2_PRESCALER_8 = ((uint8_t)0x03),\r
+ TIM2_PRESCALER_16 = ((uint8_t)0x04),\r
+ TIM2_PRESCALER_32 = ((uint8_t)0x05),\r
+ TIM2_PRESCALER_64 = ((uint8_t)0x06),\r
+ TIM2_PRESCALER_128 = ((uint8_t)0x07),\r
+ TIM2_PRESCALER_256 = ((uint8_t)0x08),\r
+ TIM2_PRESCALER_512 = ((uint8_t)0x09),\r
+ TIM2_PRESCALER_1024 = ((uint8_t)0x0A),\r
+ TIM2_PRESCALER_2048 = ((uint8_t)0x0B),\r
+ TIM2_PRESCALER_4096 = ((uint8_t)0x0C),\r
+ TIM2_PRESCALER_8192 = ((uint8_t)0x0D),\r
+ TIM2_PRESCALER_16384 = ((uint8_t)0x0E),\r
+ TIM2_PRESCALER_32768 = ((uint8_t)0x0F)\r
+}TIM2_Prescaler_TypeDef;\r
+\r
+#define IS_TIM2_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_PRESCALER_1 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_2 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_4 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_8 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_16 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_32 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_64 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_128 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_256 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_512 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_1024 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_2048 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_4096 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_8192 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_16384 ) || \\r
+ ((PRESCALER) == TIM2_PRESCALER_32768 ))\r
+\r
+/** TIM2 Output Compare and PWM modes */\r
+typedef enum\r
+{\r
+ TIM2_OCMODE_TIMING = ((uint8_t)0x00),\r
+ TIM2_OCMODE_ACTIVE = ((uint8_t)0x10),\r
+ TIM2_OCMODE_INACTIVE = ((uint8_t)0x20),\r
+ TIM2_OCMODE_TOGGLE = ((uint8_t)0x30),\r
+ TIM2_OCMODE_PWM1 = ((uint8_t)0x60),\r
+ TIM2_OCMODE_PWM2 = ((uint8_t)0x70)\r
+}TIM2_OCMode_TypeDef;\r
+\r
+#define IS_TIM2_OC_MODE_OK(MODE) (((MODE) == TIM2_OCMODE_TIMING) || \\r
+ ((MODE) == TIM2_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM2_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM2_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM2_OCMODE_PWM1) || \\r
+ ((MODE) == TIM2_OCMODE_PWM2))\r
+\r
+#define IS_TIM2_OCM_OK(MODE)(((MODE) == TIM2_OCMODE_TIMING) || \\r
+ ((MODE) == TIM2_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM2_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM2_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM2_OCMODE_PWM1) || \\r
+ ((MODE) == TIM2_OCMODE_PWM2) || \\r
+ ((MODE) == (uint8_t)TIM2_FORCEDACTION_ACTIVE) || \\r
+ ((MODE) == (uint8_t)TIM2_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM2 One Pulse Mode */\r
+typedef enum\r
+{\r
+ TIM2_OPMODE_SINGLE = ((uint8_t)0x01),\r
+ TIM2_OPMODE_REPETITIVE = ((uint8_t)0x00)\r
+}TIM2_OPMode_TypeDef;\r
+\r
+#define IS_TIM2_OPM_MODE_OK(MODE) (((MODE) == TIM2_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM2_OPMODE_REPETITIVE))\r
+\r
+/** TIM2 Channel */\r
+typedef enum\r
+{\r
+ TIM2_CHANNEL_1 = ((uint8_t)0x00),\r
+ TIM2_CHANNEL_2 = ((uint8_t)0x01),\r
+ TIM2_CHANNEL_3 = ((uint8_t)0x02)\r
+}TIM2_Channel_TypeDef;\r
+\r
+#define IS_TIM2_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM2_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM2_CHANNEL_3))\r
+\r
+#define IS_TIM2_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM2_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM2_CHANNEL_2))\r
+\r
+/** TIM2 Output Compare Polarity */\r
+typedef enum\r
+{\r
+ TIM2_OCPOLARITY_HIGH = ((uint8_t)0x00),\r
+ TIM2_OCPOLARITY_LOW = ((uint8_t)0x22)\r
+}TIM2_OCPolarity_TypeDef;\r
+\r
+#define IS_TIM2_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_OCPOLARITY_HIGH) || \\r
+ ((POLARITY) == TIM2_OCPOLARITY_LOW))\r
+\r
+/** TIM2 Output Compare states */\r
+typedef enum\r
+{\r
+ TIM2_OUTPUTSTATE_DISABLE = ((uint8_t)0x00),\r
+ TIM2_OUTPUTSTATE_ENABLE = ((uint8_t)0x11)\r
+}TIM2_OutputState_TypeDef;\r
+\r
+#define IS_TIM2_OUTPUT_STATE_OK(STATE) (((STATE) == TIM2_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM2_OUTPUTSTATE_ENABLE))\r
+\r
+/** TIM2 Input Capture Polarity */\r
+typedef enum\r
+{\r
+ TIM2_ICPOLARITY_RISING = ((uint8_t)0x00),\r
+ TIM2_ICPOLARITY_FALLING = ((uint8_t)0x44)\r
+}TIM2_ICPolarity_TypeDef;\r
+\r
+#define IS_TIM2_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM2_ICPOLARITY_RISING) || \\r
+ ((POLARITY) == TIM2_ICPOLARITY_FALLING))\r
+\r
+/** TIM2 Input Capture Selection */\r
+typedef enum\r
+{\r
+ TIM2_ICSELECTION_DIRECTTI = ((uint8_t)0x01),\r
+ TIM2_ICSELECTION_INDIRECTTI = ((uint8_t)0x02),\r
+ TIM2_ICSELECTION_TRGI = ((uint8_t)0x03)\r
+}TIM2_ICSelection_TypeDef;\r
+\r
+#define IS_TIM2_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM2_ICSELECTION_INDIRECTTI) || \\r
+ ((SELECTION) == TIM2_ICSELECTION_TRGI))\r
+\r
+#define IS_TIM2_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM2_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM2_ICSELECTION_TRGI))\r
+\r
+/** TIM2 Input Capture Prescaler */\r
+typedef enum\r
+{\r
+ TIM2_ICPSC_DIV1 = ((uint8_t)0x00),\r
+ TIM2_ICPSC_DIV2 = ((uint8_t)0x04),\r
+ TIM2_ICPSC_DIV4 = ((uint8_t)0x08),\r
+ TIM2_ICPSC_DIV8 = ((uint8_t)0x0C)\r
+}TIM2_ICPSC_TypeDef;\r
+\r
+#define IS_TIM2_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM2_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM2_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM2_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM2_ICPSC_DIV8))\r
+\r
+/** TIM2 Input Capture Filer Value */\r
+#define IS_TIM2_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)\r
+\r
+/** TIM2 interrupt sources */\r
+typedef enum\r
+{\r
+ TIM2_IT_UPDATE = ((uint8_t)0x01),\r
+ TIM2_IT_CC1 = ((uint8_t)0x02),\r
+ TIM2_IT_CC2 = ((uint8_t)0x04),\r
+ TIM2_IT_CC3 = ((uint8_t)0x08)\r
+}TIM2_IT_TypeDef;\r
+\r
+#define IS_TIM2_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x0F))\r
+\r
+#define IS_TIM2_GET_IT_OK(IT) (((IT) == TIM2_IT_UPDATE) || \\r
+ ((IT) == TIM2_IT_CC1) || \\r
+ ((IT) == TIM2_IT_CC2) || \\r
+ ((IT) == TIM2_IT_CC3))\r
+\r
+/** TIM2 Prescaler Reload Mode */\r
+typedef enum\r
+{\r
+ TIM2_PSCRELOADMODE_UPDATE = ((uint8_t)0x00),\r
+ TIM2_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01)\r
+}TIM2_PSCReloadMode_TypeDef;\r
+\r
+#define IS_TIM2_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM2_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM2_PSCRELOADMODE_IMMEDIATE))\r
+\r
+/** TIM2 Event Source */\r
+typedef enum\r
+{\r
+ TIM2_EVENTSOURCE_UPDATE = ((uint8_t)0x01),\r
+ TIM2_EVENTSOURCE_CC1 = ((uint8_t)0x02),\r
+ TIM2_EVENTSOURCE_CC2 = ((uint8_t)0x04),\r
+ TIM2_EVENTSOURCE_CC3 = ((uint8_t)0x08)\r
+}TIM2_EventSource_TypeDef;\r
+\r
+#define IS_TIM2_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))\r
+\r
+/** TIM2 Update Source */\r
+typedef enum\r
+{\r
+ TIM2_UPDATESOURCE_GLOBAL = ((uint8_t)0x00),\r
+ TIM2_UPDATESOURCE_REGULAR = ((uint8_t)0x01)\r
+}TIM2_UpdateSource_TypeDef;\r
+\r
+#define IS_TIM2_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM2_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM2_UPDATESOURCE_REGULAR))\r
+\r
+/** TIM2 Flags */\r
+typedef enum\r
+{\r
+ TIM2_FLAG_UPDATE = ((uint16_t)0x0001),\r
+ TIM2_FLAG_CC1 = ((uint16_t)0x0002),\r
+ TIM2_FLAG_CC2 = ((uint16_t)0x0004),\r
+ TIM2_FLAG_CC3 = ((uint16_t)0x0008),\r
+ TIM2_FLAG_CC1OF = ((uint16_t)0x0200),\r
+ TIM2_FLAG_CC2OF = ((uint16_t)0x0400),\r
+ TIM2_FLAG_CC3OF = ((uint16_t)0x0800)\r
+}TIM2_FLAG_TypeDef;\r
+\r
+#define IS_TIM2_GET_FLAG_OK(FLAG) (((FLAG) == TIM2_FLAG_UPDATE) || \\r
+ ((FLAG) == TIM2_FLAG_CC1) || \\r
+ ((FLAG) == TIM2_FLAG_CC2) || \\r
+ ((FLAG) == TIM2_FLAG_CC3) || \\r
+ ((FLAG) == TIM2_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM2_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM2_FLAG_CC3OF))\r
+\r
+#define IS_TIM2_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM2_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM2_DeInit(void);\r
+void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler, uint16_t TIM2_Period);\r
+void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode, TIM2_OutputState_TypeDef TIM2_OutputState, uint16_t TIM2_Pulse, TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);\r
+void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel, TIM2_ICPolarity_TypeDef TIM2_ICPolarity, TIM2_ICSelection_TypeDef TIM2_ICSelection, TIM2_ICPSC_TypeDef TIM2_ICPrescaler, uint8_t TIM2_ICFilter);\r
+void TIM2_Cmd(FunctionalState NewState);\r
+void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);\r
+void TIM2_InternalClockConfig(void);\r
+void TIM2_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);\r
+void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);\r
+void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler, TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);\r
+void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);\r
+void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);\r
+void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);\r
+void TIM2_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM2_CCPreloadControl(FunctionalState NewState);\r
+void TIM2_OC1PreloadConfig(FunctionalState NewState);\r
+void TIM2_OC2PreloadConfig(FunctionalState NewState);\r
+void TIM2_OC3PreloadConfig(FunctionalState NewState);\r
+void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);\r
+void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);\r
+void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);\r
+void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);\r
+void TIM2_SetCounter(uint16_t Counter);\r
+void TIM2_SetAutoreload(uint16_t Autoreload);\r
+void TIM2_SetCompare1(uint16_t Compare1);\r
+void TIM2_SetCompare2(uint16_t Compare2);\r
+void TIM2_SetCompare3(uint16_t Compare3);\r
+void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);\r
+void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);\r
+void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler);\r
+uint16_t TIM2_GetCapture1(void);\r
+uint16_t TIM2_GetCapture2(void);\r
+uint16_t TIM2_GetCapture3(void);\r
+uint16_t TIM2_GetCounter(void);\r
+TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);\r
+FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);\r
+void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);\r
+ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);\r
+void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM2_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim3.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM3 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM3_H\r
+#define __STM8S_TIM3_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM3_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** TIM3 Forced Action */\r
+typedef enum\r
+{\r
+ TIM3_FORCEDACTION_ACTIVE = ((uint8_t)0x50),\r
+ TIM3_FORCEDACTION_INACTIVE = ((uint8_t)0x40)\r
+} TIM3_ForcedAction_TypeDef;\r
+\r
+#define IS_TIM3_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM3_FORCEDACTION_ACTIVE) || \\r
+ ((ACTION) == TIM3_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM3 Prescaler */\r
+typedef enum\r
+{\r
+ TIM3_PRESCALER_1 = ((uint8_t)0x00),\r
+ TIM3_PRESCALER_2 = ((uint8_t)0x01),\r
+ TIM3_PRESCALER_4 = ((uint8_t)0x02),\r
+ TIM3_PRESCALER_8 = ((uint8_t)0x03),\r
+ TIM3_PRESCALER_16 = ((uint8_t)0x04),\r
+ TIM3_PRESCALER_32 = ((uint8_t)0x05),\r
+ TIM3_PRESCALER_64 = ((uint8_t)0x06),\r
+ TIM3_PRESCALER_128 = ((uint8_t)0x07),\r
+ TIM3_PRESCALER_256 = ((uint8_t)0x08),\r
+ TIM3_PRESCALER_512 = ((uint8_t)0x09),\r
+ TIM3_PRESCALER_1024 = ((uint8_t)0x0A),\r
+ TIM3_PRESCALER_2048 = ((uint8_t)0x0B),\r
+ TIM3_PRESCALER_4096 = ((uint8_t)0x0C),\r
+ TIM3_PRESCALER_8192 = ((uint8_t)0x0D),\r
+ TIM3_PRESCALER_16384 = ((uint8_t)0x0E),\r
+ TIM3_PRESCALER_32768 = ((uint8_t)0x0F)\r
+} TIM3_Prescaler_TypeDef;\r
+\r
+#define IS_TIM3_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_PRESCALER_1 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_2 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_4 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_8 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_16 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_32 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_64 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_128 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_256 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_512 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_1024 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_2048 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_4096 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_8192 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_16384 ) || \\r
+ ((PRESCALER) == TIM3_PRESCALER_32768 ))\r
+\r
+/** TIM3 Output Compare and PWM modes */\r
+typedef enum\r
+{\r
+ TIM3_OCMODE_TIMING = ((uint8_t)0x00),\r
+ TIM3_OCMODE_ACTIVE = ((uint8_t)0x10),\r
+ TIM3_OCMODE_INACTIVE = ((uint8_t)0x20),\r
+ TIM3_OCMODE_TOGGLE = ((uint8_t)0x30),\r
+ TIM3_OCMODE_PWM1 = ((uint8_t)0x60),\r
+ TIM3_OCMODE_PWM2 = ((uint8_t)0x70)\r
+} TIM3_OCMode_TypeDef;\r
+\r
+#define IS_TIM3_OC_MODE_OK(MODE) (((MODE) == TIM3_OCMODE_TIMING) || \\r
+ ((MODE) == TIM3_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM3_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM3_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM3_OCMODE_PWM1) || \\r
+ ((MODE) == TIM3_OCMODE_PWM2))\r
+\r
+#define IS_TIM3_OCM_OK(MODE)(((MODE) == TIM3_OCMODE_TIMING) || \\r
+ ((MODE) == TIM3_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM3_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM3_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM3_OCMODE_PWM1) || \\r
+ ((MODE) == TIM3_OCMODE_PWM2) || \\r
+ ((MODE) == (uint8_t)TIM3_FORCEDACTION_ACTIVE) || \\r
+ ((MODE) == (uint8_t)TIM3_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM3 One Pulse Mode */\r
+typedef enum\r
+{\r
+ TIM3_OPMODE_SINGLE = ((uint8_t)0x01),\r
+ TIM3_OPMODE_REPETITIVE = ((uint8_t)0x00)\r
+} TIM3_OPMode_TypeDef;\r
+\r
+#define IS_TIM3_OPM_MODE_OK(MODE) (((MODE) == TIM3_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM3_OPMODE_REPETITIVE))\r
+\r
+/** TIM3 Channel */\r
+\r
+typedef enum\r
+{\r
+ TIM3_CHANNEL_1 = ((uint8_t)0x00),\r
+ TIM3_CHANNEL_2 = ((uint8_t)0x01)\r
+} TIM3_Channel_TypeDef;\r
+\r
+#define IS_TIM3_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM3_CHANNEL_2))\r
+\r
+#define IS_TIM3_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM3_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM3_CHANNEL_2))\r
+\r
+/** TIM3 Output Compare Polarity */\r
+typedef enum\r
+{\r
+ TIM3_OCPOLARITY_HIGH = ((uint8_t)0x00),\r
+ TIM3_OCPOLARITY_LOW = ((uint8_t)0x22)\r
+} TIM3_OCPolarity_TypeDef;\r
+\r
+#define IS_TIM3_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_OCPOLARITY_HIGH) || \\r
+ ((POLARITY) == TIM3_OCPOLARITY_LOW))\r
+\r
+/** TIM3 Output Compare states */\r
+typedef enum\r
+{\r
+ TIM3_OUTPUTSTATE_DISABLE = ((uint8_t)0x00),\r
+ TIM3_OUTPUTSTATE_ENABLE = ((uint8_t)0x11)\r
+} TIM3_OutputState_TypeDef;\r
+\r
+#define IS_TIM3_OUTPUT_STATE_OK(STATE) (((STATE) == TIM3_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM3_OUTPUTSTATE_ENABLE))\r
+\r
+/** TIM3 Input Capture Polarity */\r
+typedef enum\r
+{\r
+ TIM3_ICPOLARITY_RISING = ((uint8_t)0x00),\r
+ TIM3_ICPOLARITY_FALLING = ((uint8_t)0x44)\r
+} TIM3_ICPolarity_TypeDef;\r
+\r
+#define IS_TIM3_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM3_ICPOLARITY_RISING) || \\r
+ ((POLARITY) == TIM3_ICPOLARITY_FALLING))\r
+\r
+/** TIM3 Input Capture Selection */\r
+typedef enum\r
+{\r
+ TIM3_ICSELECTION_DIRECTTI = ((uint8_t)0x01),\r
+ TIM3_ICSELECTION_INDIRECTTI = ((uint8_t)0x02),\r
+ TIM3_ICSELECTION_TRGI = ((uint8_t)0x03)\r
+} TIM3_ICSelection_TypeDef;\r
+\r
+#define IS_TIM3_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM3_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM3_ICSELECTION_INDIRECTTI) || \\r
+ ((SELECTION) == TIM3_ICSELECTION_TRGI))\r
+\r
+/** TIM3 Input Capture Prescaler */\r
+typedef enum\r
+{\r
+ TIM3_ICPSC_DIV1 = ((uint8_t)0x00),\r
+ TIM3_ICPSC_DIV2 = ((uint8_t)0x04),\r
+ TIM3_ICPSC_DIV4 = ((uint8_t)0x08),\r
+ TIM3_ICPSC_DIV8 = ((uint8_t)0x0C)\r
+} TIM3_ICPSC_TypeDef;\r
+\r
+#define IS_TIM3_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM3_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM3_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM3_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM3_ICPSC_DIV8))\r
+\r
+/** TIM3 Input Capture Filer Value */\r
+#define IS_TIM3_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)\r
+\r
+/** TIM3 interrupt sources */\r
+typedef enum\r
+{\r
+ TIM3_IT_UPDATE = ((uint8_t)0x01),\r
+ TIM3_IT_CC1 = ((uint8_t)0x02),\r
+ TIM3_IT_CC2 = ((uint8_t)0x04)\r
+} TIM3_IT_TypeDef;\r
+\r
+#define IS_TIM3_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x07))\r
+\r
+#define IS_TIM3_GET_IT_OK(IT) (((IT) == TIM3_IT_UPDATE) || \\r
+ ((IT) == TIM3_IT_CC1) || \\r
+ ((IT) == TIM3_IT_CC2))\r
+\r
+/** TIM3 Prescaler Reload Mode */\r
+typedef enum\r
+{\r
+ TIM3_PSCRELOADMODE_UPDATE = ((uint8_t)0x00),\r
+ TIM3_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01)\r
+} TIM3_PSCReloadMode_TypeDef;\r
+\r
+#define IS_TIM3_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM3_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM3_PSCRELOADMODE_IMMEDIATE))\r
+\r
+/** TIM3 Event Source */\r
+typedef enum\r
+{\r
+ TIM3_EVENTSOURCE_UPDATE = ((uint8_t)0x01),\r
+ TIM3_EVENTSOURCE_CC1 = ((uint8_t)0x02),\r
+ TIM3_EVENTSOURCE_CC2 = ((uint8_t)0x04)\r
+} TIM3_EventSource_TypeDef;\r
+\r
+#define IS_TIM3_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))\r
+\r
+/** TIM3 Update Source */\r
+typedef enum\r
+{\r
+ TIM3_UPDATESOURCE_GLOBAL = ((uint8_t)0x00),\r
+ TIM3_UPDATESOURCE_REGULAR = ((uint8_t)0x01)\r
+} TIM3_UpdateSource_TypeDef;\r
+\r
+#define IS_TIM3_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM3_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM3_UPDATESOURCE_REGULAR))\r
+\r
+/** TIM3 Flags */\r
+typedef enum\r
+{\r
+ TIM3_FLAG_UPDATE = ((uint16_t)0x0001),\r
+ TIM3_FLAG_CC1 = ((uint16_t)0x0002),\r
+ TIM3_FLAG_CC2 = ((uint16_t)0x0004),\r
+ TIM3_FLAG_CC1OF = ((uint16_t)0x0200),\r
+ TIM3_FLAG_CC2OF = ((uint16_t)0x0400)\r
+} TIM3_FLAG_TypeDef;\r
+\r
+#define IS_TIM3_GET_FLAG_OK(FLAG) (((FLAG) == TIM3_FLAG_UPDATE) || \\r
+ ((FLAG) == TIM3_FLAG_CC1) || \\r
+ ((FLAG) == TIM3_FLAG_CC2) || \\r
+ ((FLAG) == TIM3_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM3_FLAG_CC2OF) )\r
+\r
+#define IS_TIM3_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF9F8) == 0x0000) && ((uint16_t)(FLAG)!= 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM3_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM3_DeInit(void);\r
+void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler, uint16_t TIM3_Period);\r
+void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);\r
+void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode, TIM3_OutputState_TypeDef TIM3_OutputState, uint16_t TIM3_Pulse, TIM3_OCPolarity_TypeDef TIM3_OCPolarity);\r
+void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);\r
+void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel, TIM3_ICPolarity_TypeDef TIM3_ICPolarity, TIM3_ICSelection_TypeDef TIM3_ICSelection, TIM3_ICPSC_TypeDef TIM3_ICPrescaler, uint8_t TIM3_ICFilter);\r
+void TIM3_Cmd(FunctionalState NewState);\r
+void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);\r
+void TIM3_InternalClockConfig(void);\r
+void TIM3_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);\r
+void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);\r
+void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler, TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);\r
+void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);\r
+void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);\r
+void TIM3_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM3_CCPreloadControl(FunctionalState NewState);\r
+void TIM3_OC1PreloadConfig(FunctionalState NewState);\r
+void TIM3_OC2PreloadConfig(FunctionalState NewState);\r
+void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);\r
+void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);\r
+void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);\r
+void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);\r
+void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode);\r
+void TIM3_SetCounter(uint16_t Counter);\r
+void TIM3_SetAutoreload(uint16_t Autoreload);\r
+void TIM3_SetCompare1(uint16_t Compare1);\r
+void TIM3_SetCompare2(uint16_t Compare2);\r
+void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);\r
+void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);\r
+uint16_t TIM3_GetCapture1(void);\r
+uint16_t TIM3_GetCapture2(void);\r
+uint16_t TIM3_GetCounter(void);\r
+TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);\r
+FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);\r
+void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);\r
+ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);\r
+void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM3_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim4.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM4 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM4_H\r
+#define __STM8S_TIM4_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM4_Exported_Types\r
+ * @{\r
+ */\r
+\r
+\r
+\r
+/** TIM4 Prescaler */\r
+typedef enum\r
+{\r
+ TIM4_PRESCALER_1 = ((uint8_t)0x00),\r
+ TIM4_PRESCALER_2 = ((uint8_t)0x01),\r
+ TIM4_PRESCALER_4 = ((uint8_t)0x02),\r
+ TIM4_PRESCALER_8 = ((uint8_t)0x03),\r
+ TIM4_PRESCALER_16 = ((uint8_t)0x04),\r
+ TIM4_PRESCALER_32 = ((uint8_t)0x05),\r
+ TIM4_PRESCALER_64 = ((uint8_t)0x06),\r
+ TIM4_PRESCALER_128 = ((uint8_t)0x07)\r
+} TIM4_Prescaler_TypeDef;\r
+\r
+#define IS_TIM4_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM4_PRESCALER_1 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_2 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_4 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_8 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_16 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_32 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_64 ) || \\r
+ ((PRESCALER) == TIM4_PRESCALER_128 ) )\r
+\r
+/** TIM4 One Pulse Mode */\r
+typedef enum\r
+{\r
+ TIM4_OPMODE_SINGLE = ((uint8_t)0x01),\r
+ TIM4_OPMODE_REPETITIVE = ((uint8_t)0x00)\r
+} TIM4_OPMode_TypeDef;\r
+\r
+#define IS_TIM4_OPM_MODE_OK(MODE) (((MODE) == TIM4_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM4_OPMODE_REPETITIVE))\r
+\r
+/** TIM4 Prescaler Reload Mode */\r
+typedef enum\r
+{\r
+ TIM4_PSCRELOADMODE_UPDATE = ((uint8_t)0x00),\r
+ TIM4_PSCRELOADMODE_IMMEDIATE = ((uint8_t)0x01)\r
+} TIM4_PSCReloadMode_TypeDef;\r
+\r
+#define IS_TIM4_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM4_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM4_PSCRELOADMODE_IMMEDIATE))\r
+\r
+/** TIM4 Update Source */\r
+typedef enum\r
+{\r
+ TIM4_UPDATESOURCE_GLOBAL = ((uint8_t)0x00),\r
+ TIM4_UPDATESOURCE_REGULAR = ((uint8_t)0x01)\r
+} TIM4_UpdateSource_TypeDef;\r
+\r
+#define IS_TIM4_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM4_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM4_UPDATESOURCE_REGULAR))\r
+\r
+/** TIM4 Event Source */\r
+typedef enum\r
+{\r
+ TIM4_EVENTSOURCE_UPDATE = ((uint8_t)0x01)\r
+}TIM4_EventSource_TypeDef;\r
+\r
+#define IS_TIM4_EVENT_SOURCE_OK(SOURCE) (((SOURCE) == 0x01))\r
+\r
+/** TIM4 Flags */\r
+typedef enum\r
+{\r
+ TIM4_FLAG_UPDATE = ((uint8_t)0x01)\r
+}TIM4_FLAG_TypeDef;\r
+\r
+#define IS_TIM4_GET_FLAG_OK(FLAG) ((FLAG) == TIM4_FLAG_UPDATE)\r
+\r
+\r
+\r
+/** TIM4 interrupt sources */\r
+typedef enum\r
+{\r
+ TIM4_IT_UPDATE = ((uint8_t)0x01)\r
+}TIM4_IT_TypeDef;\r
+\r
+#define IS_TIM4_IT_OK(IT) ((IT) == TIM4_IT_UPDATE)\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM4_Exported_Functions\r
+ * @{\r
+ */\r
+void TIM4_DeInit(void);\r
+void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period);\r
+void TIM4_Cmd(FunctionalState NewState);\r
+void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);\r
+void TIM4_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);\r
+void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);\r
+void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);\r
+void TIM4_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);\r
+void TIM4_SetCounter(uint8_t Counter);\r
+void TIM4_SetAutoreload(uint8_t Autoreload);\r
+uint8_t TIM4_GetCounter(void);\r
+TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);\r
+FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);\r
+void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);\r
+ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);\r
+void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM4_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim5.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM5 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM5_H\r
+#define __STM8S_TIM5_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+\r
+/** TIM5 Forced Action */\r
+typedef enum\r
+{\r
+ TIM5_FORCEDACTION_ACTIVE =((uint8_t)0x50),\r
+ TIM5_FORCEDACTION_INACTIVE =((uint8_t)0x40)\r
+}TIM5_ForcedAction_TypeDef;\r
+\r
+#define IS_TIM5_FORCED_ACTION_OK(ACTION) (((ACTION) == TIM5_FORCEDACTION_ACTIVE) || \\r
+ ((ACTION) == TIM5_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM5 Prescaler */\r
+typedef enum\r
+{\r
+ TIM5_PRESCALER_1 =((uint8_t)0x00),\r
+ TIM5_PRESCALER_2 =((uint8_t)0x01),\r
+ TIM5_PRESCALER_4 =((uint8_t)0x02),\r
+ TIM5_PRESCALER_8 =((uint8_t)0x03),\r
+ TIM5_PRESCALER_16 =((uint8_t)0x04),\r
+ TIM5_PRESCALER_32 =((uint8_t)0x05),\r
+ TIM5_PRESCALER_64 =((uint8_t)0x06),\r
+ TIM5_PRESCALER_128 =((uint8_t)0x07),\r
+ TIM5_PRESCALER_256 =((uint8_t)0x08),\r
+ TIM5_PRESCALER_512 =((uint8_t)0x09),\r
+ TIM5_PRESCALER_1024 =((uint8_t)0x0A),\r
+ TIM5_PRESCALER_2048 =((uint8_t)0x0B),\r
+ TIM5_PRESCALER_4096 =((uint8_t)0x0C),\r
+ TIM5_PRESCALER_8192 =((uint8_t)0x0D),\r
+ TIM5_PRESCALER_16384 =((uint8_t)0x0E),\r
+ TIM5_PRESCALER_32768 =((uint8_t)0x0F)\r
+}TIM5_Prescaler_TypeDef;\r
+\r
+#define IS_TIM5_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_PRESCALER_1) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_2 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_4 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_8 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_16 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_32 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_64 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_128 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_256 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_512 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_1024 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_2048 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_4096 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_8192 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_16384 ) || \\r
+ ((PRESCALER) == TIM5_PRESCALER_32768 ))\r
+\r
+/** TIM5 Output Compare and PWM modes */\r
+typedef enum\r
+{\r
+ TIM5_OCMODE_TIMING =((uint8_t)0x00),\r
+ TIM5_OCMODE_ACTIVE =((uint8_t)0x10),\r
+ TIM5_OCMODE_INACTIVE =((uint8_t)0x20),\r
+ TIM5_OCMODE_TOGGLE =((uint8_t)0x30),\r
+ TIM5_OCMODE_PWM1 =((uint8_t)0x60),\r
+ TIM5_OCMODE_PWM2 =((uint8_t)0x70)\r
+}TIM5_OCMode_TypeDef;\r
+\r
+#define IS_TIM5_OC_MODE_OK(MODE) (((MODE) == TIM5_OCMODE_TIMING) || \\r
+ ((MODE) == TIM5_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM5_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM5_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM5_OCMODE_PWM1) || \\r
+ ((MODE) == TIM5_OCMODE_PWM2))\r
+\r
+#define IS_TIM5_OCM_OK(MODE)(((MODE) == TIM5_OCMODE_TIMING) || \\r
+ ((MODE) == TIM5_OCMODE_ACTIVE) || \\r
+ ((MODE) == TIM5_OCMODE_INACTIVE) || \\r
+ ((MODE) == TIM5_OCMODE_TOGGLE)|| \\r
+ ((MODE) == TIM5_OCMODE_PWM1) || \\r
+ ((MODE) == TIM5_OCMODE_PWM2) || \\r
+ ((MODE) == (uint8_t)TIM5_FORCEDACTION_ACTIVE) || \\r
+ ((MODE) == (uint8_t)TIM5_FORCEDACTION_INACTIVE))\r
+\r
+/** TIM5 One Pulse Mode */\r
+typedef enum\r
+{\r
+ TIM5_OPMODE_SINGLE =((uint8_t)0x01),\r
+ TIM5_OPMODE_REPETITIVE =((uint8_t)0x00)\r
+}TIM5_OPMode_TypeDef;\r
+\r
+#define IS_TIM5_OPM_MODE_OK(MODE) (((MODE) == TIM5_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM5_OPMODE_REPETITIVE))\r
+\r
+/** TIM5 Channel */\r
+typedef enum\r
+{\r
+ TIM5_CHANNEL_1 =((uint8_t)0x00),\r
+ TIM5_CHANNEL_2 =((uint8_t)0x01),\r
+ TIM5_CHANNEL_3 =((uint8_t)0x02)\r
+}TIM5_Channel_TypeDef;\r
+\r
+#define IS_TIM5_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM5_CHANNEL_2) || \\r
+ ((CHANNEL) == TIM5_CHANNEL_3))\r
+\r
+#define IS_TIM5_PWMI_CHANNEL_OK(CHANNEL) (((CHANNEL) == TIM5_CHANNEL_1) || \\r
+ ((CHANNEL) == TIM5_CHANNEL_2))\r
+\r
+/** TIM5 Output Compare Polarity */\r
+typedef enum\r
+{\r
+ TIM5_OCPOLARITY_HIGH =((uint8_t)0x00),\r
+ TIM5_OCPOLARITY_LOW =((uint8_t)0x22)\r
+}TIM5_OCPolarity_TypeDef;\r
+\r
+#define IS_TIM5_OC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_OCPOLARITY_HIGH) || \\r
+ ((POLARITY) == TIM5_OCPOLARITY_LOW))\r
+\r
+/** TIM5 Output Compare states */\r
+typedef enum\r
+{\r
+ TIM5_OUTPUTSTATE_DISABLE =((uint8_t)0x00),\r
+ TIM5_OUTPUTSTATE_ENABLE =((uint8_t)0x11)\r
+}TIM5_OutputState_TypeDef;\r
+\r
+#define IS_TIM5_OUTPUT_STATE_OK(STATE) (((STATE) == TIM5_OUTPUTSTATE_DISABLE) || \\r
+ ((STATE) == TIM5_OUTPUTSTATE_ENABLE))\r
+\r
+/** TIM5 Input Capture Polarity */\r
+typedef enum\r
+{\r
+ TIM5_ICPOLARITY_RISING =((uint8_t)0x00),\r
+ TIM5_ICPOLARITY_FALLING =((uint8_t)0x44)\r
+}TIM5_ICPolarity_TypeDef;\r
+\r
+#define IS_TIM5_IC_POLARITY_OK(POLARITY) (((POLARITY) == TIM5_ICPOLARITY_RISING) || \\r
+ ((POLARITY) == TIM5_ICPOLARITY_FALLING))\r
+\r
+/** TIM5 Input Capture Selection */\r
+typedef enum\r
+{\r
+ TIM5_ICSELECTION_DIRECTTI =((uint8_t)0x01),\r
+ TIM5_ICSELECTION_INDIRECTTI =((uint8_t)0x02),\r
+ TIM5_ICSELECTION_TRGI =((uint8_t)0x03)\r
+}TIM5_ICSelection_TypeDef;\r
+\r
+#define IS_TIM5_IC_SELECTION_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM5_ICSELECTION_INDIRECTTI) || \\r
+ ((SELECTION) == TIM5_ICSELECTION_TRGI))\r
+\r
+#define IS_TIM5_IC_SELECTION1_OK(SELECTION) (((SELECTION) == TIM5_ICSELECTION_DIRECTTI) || \\r
+ ((SELECTION) == TIM5_ICSELECTION_TRGI))\r
+\r
+/** TIM5 Input Capture Prescaler */\r
+typedef enum\r
+{\r
+ TIM5_ICPSC_DIV1 =((uint8_t)0x00),\r
+ TIM5_ICPSC_DIV2 =((uint8_t)0x04),\r
+ TIM5_ICPSC_DIV4 =((uint8_t)0x08),\r
+ TIM5_ICPSC_DIV8 =((uint8_t)0x0C)\r
+}TIM5_ICPSC_TypeDef;\r
+\r
+#define IS_TIM5_IC_PRESCALER_OK(PRESCALER) (((PRESCALER) == TIM5_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM5_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM5_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM5_ICPSC_DIV8))\r
+\r
+/** TIM5 Input Capture Filer Value */\r
+#define IS_TIM5_IC_FILTER_OK(ICFILTER) ((ICFILTER) <= 0x0F)\r
+\r
+/** TIM5 interrupt sources */\r
+typedef enum\r
+{\r
+ TIM5_IT_UPDATE =((uint8_t)0x01),\r
+ TIM5_IT_CC1 =((uint8_t)0x02),\r
+ TIM5_IT_CC2 =((uint8_t)0x04),\r
+ TIM5_IT_CC3 =((uint8_t)0x08),\r
+ TIM5_IT_TRIGGER = ((uint8_t)0x40)\r
+}TIM5_IT_TypeDef;\r
+\r
+#define IS_TIM5_IT_OK(IT) (((IT) != 0x00) && ((IT) <= 0x4F))\r
+\r
+#define IS_TIM5_GET_IT_OK(IT) (((IT) == TIM5_IT_UPDATE) || \\r
+ ((IT) == TIM5_IT_CC1) || \\r
+ ((IT) == TIM5_IT_CC2) || \\r
+ ((IT) == TIM5_IT_CC3) || \\r
+ ((IT) == TIM5_IT_TRIGGER))\r
+\r
+/** TIM5 Prescaler Reload Mode */\r
+typedef enum\r
+{\r
+ TIM5_PSCRELOADMODE_UPDATE =((uint8_t)0x00),\r
+ TIM5_PSCRELOADMODE_IMMEDIATE =((uint8_t)0x01)\r
+}TIM5_PSCReloadMode_TypeDef;\r
+\r
+#define IS_TIM5_PRESCALER_RELOAD_OK(RELOAD) (((RELOAD) == TIM5_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM5_PSCRELOADMODE_IMMEDIATE))\r
+\r
+/** TIM5 Event Source */\r
+typedef enum\r
+{\r
+ TIM5_EVENTSOURCE_UPDATE =((uint8_t)0x01),\r
+ TIM5_EVENTSOURCE_CC1 =((uint8_t)0x02),\r
+ TIM5_EVENTSOURCE_CC2 =((uint8_t)0x04),\r
+ TIM5_EVENTSOURCE_CC3 =((uint8_t)0x08),\r
+ TIM5_EVENTSOURCE_TRIGGER = ((uint8_t)0x40)\r
+}TIM5_EventSource_TypeDef;\r
+\r
+#define IS_TIM5_EVENT_SOURCE_OK(SOURCE) (((SOURCE) != 0x00))\r
+\r
+/** TIM5 Update Source */\r
+typedef enum\r
+{\r
+ TIM5_UPDATESOURCE_GLOBAL =((uint8_t)0x00),\r
+ TIM5_UPDATESOURCE_REGULAR =((uint8_t)0x01)\r
+}TIM5_UpdateSource_TypeDef;\r
+\r
+\r
+#define IS_TIM5_UPDATE_SOURCE_OK(SOURCE) (((SOURCE) == TIM5_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM5_UPDATESOURCE_REGULAR))\r
+\r
+/**\r
+ * @brief TIM5 Trigger Output Source\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_TRGOSOURCE_RESET = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/\r
+ TIM5_TRGOSOURCE_ENABLE = ((uint8_t)0x10), /*!< Trigger Output source = TIM5 is enabled*/\r
+ TIM5_TRGOSOURCE_UPDATE = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/\r
+ TIM5_TRGOSOURCE_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */\r
+ TIM5_TRGOSOURCE_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */\r
+ TIM5_TRGOSOURCE_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */\r
+}TIM5_TRGOSource_TypeDef;\r
+\r
+/**\r
+ * @brief Macro TIM5 TRGO source\r
+ */\r
+#define IS_TIM5_TRGO_SOURCE_OK(SOURCE) \\r
+ (((SOURCE) == TIM5_TRGOSOURCE_RESET) || \\r
+ ((SOURCE) == TIM5_TRGOSOURCE_ENABLE) || \\r
+ ((SOURCE) == TIM5_TRGOSOURCE_UPDATE) || \\r
+ ((SOURCE) == TIM5_TRGOSOURCE_OC1) || \\r
+ ((SOURCE) == TIM5_TRGOSOURCE_OC1REF) || \\r
+ ((SOURCE) == TIM5_TRGOSOURCE_OC2REF))\r
+ \r
+/** TIM5 Flags */\r
+typedef enum\r
+{\r
+ TIM5_FLAG_UPDATE =((uint16_t)0x0001),\r
+ TIM5_FLAG_CC1 =((uint16_t)0x0002),\r
+ TIM5_FLAG_CC2 =((uint16_t)0x0004),\r
+ TIM5_FLAG_CC3 =((uint16_t)0x0008),\r
+ TIM5_FLAG_TRIGGER = ((uint16_t)0x0040),\r
+ TIM5_FLAG_CC1OF =((uint16_t)0x0200),\r
+ TIM5_FLAG_CC2OF =((uint16_t)0x0400),\r
+ TIM5_FLAG_CC3OF =((uint16_t)0x0800)\r
+}TIM5_FLAG_TypeDef;\r
+\r
+#define IS_TIM5_GET_FLAG_OK(FLAG) (((FLAG) == TIM5_FLAG_UPDATE) || \\r
+ ((FLAG) == TIM5_FLAG_CC1) || \\r
+ ((FLAG) == TIM5_FLAG_CC2) || \\r
+ ((FLAG) == TIM5_FLAG_CC3) || \\r
+ ((FLAG) == TIM5_FLAG_TRIGGER) || \\r
+ ((FLAG) == TIM5_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM5_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM5_FLAG_CC3OF))\r
+\r
+#define IS_TIM5_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & 0xF1F0) == 0x0000) && ((uint16_t)(FLAG) != 0x0000))\r
+\r
+\r
+/**\r
+ * @brief TIM5 Slave Mode\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_SLAVEMODE_RESET = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/\r
+ TIM5_SLAVEMODE_GATED = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/\r
+ TIM5_SLAVEMODE_TRIGGER = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/\r
+ TIM5_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/\r
+}TIM5_SlaveMode_TypeDef;\r
+\r
+/**\r
+ * @brief Macro TIM5 Slave mode\r
+ */\r
+#define IS_TIM5_SLAVE_MODE_OK(MODE) \\r
+ (((MODE) == TIM5_SLAVEMODE_RESET) || \\r
+ ((MODE) == TIM5_SLAVEMODE_GATED) || \\r
+ ((MODE) == TIM5_SLAVEMODE_TRIGGER) || \\r
+ ((MODE) == TIM5_SLAVEMODE_EXTERNAL1))\r
+ \r
+/**\r
+ * @brief TIM5 Internal Trigger Selection\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_TS_TIM6 = ((uint8_t)0x00), /*!< TRIG Input source = TIM6 TRIG Output */\r
+ TIM5_TS_TIM1 = ((uint8_t)0x03) /*!< TRIG Input source = TIM1 TRIG Output */\r
+}TIM5_TS_TypeDef;\r
+\r
+/**\r
+ * @brief Macro TIM5 Trigger Selection\r
+ */\r
+#define IS_TIM5_TRIGGER_SELECTION_OK(SELECTION) \\r
+ (((SELECTION) == TIM5_TS_TIM6) || \\r
+ ((SELECTION) == TIM5_TS_TIM1) )\r
+\r
+\r
+#define IS_TIM5_TIX_TRIGGER_SELECTION_OK(SELECTION) \\r
+ (((SELECTION) == TIM5_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM5_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM5_TS_TI2FP2))\r
+\r
+\r
+/**\r
+ * @brief TIM5 Encoder Mode\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_ENCODERMODE_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/\r
+ TIM5_ENCODERMODE_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/\r
+ TIM5_ENCODERMODE_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/\r
+}TIM5_EncoderMode_TypeDef;\r
+/**\r
+ * @brief Macro TIM5 encoder mode\r
+ */\r
+#define IS_TIM5_ENCODER_MODE_OK(MODE) \\r
+ (((MODE) == TIM5_ENCODERMODE_TI1) || \\r
+ ((MODE) == TIM5_ENCODERMODE_TI2) || \\r
+ ((MODE) == TIM5_ENCODERMODE_TI12))\r
+ \r
+/**\r
+ * @brief TIM5 External Trigger Prescaler\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_EXTTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */\r
+ TIM5_EXTTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */\r
+ TIM5_EXTTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */\r
+ TIM5_EXTTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */\r
+}TIM5_ExtTRGPSC_TypeDef;\r
+\r
+/**\r
+ * @brief Macro TIM5 external trigger prescaler\r
+ */\r
+#define IS_TIM5_EXT_PRESCALER_OK(PRESCALER) \\r
+ (((PRESCALER) == TIM5_EXTTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM5_EXTTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM5_EXTTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM5_EXTTRGPSC_DIV8))\r
+ \r
+/**\r
+ * @brief TIM5 External Trigger Polarity\r
+ */\r
+typedef enum\r
+{\r
+ TIM5_EXTTRGPOLARITY_INVERTED = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */\r
+ TIM5_EXTTRGPOLARITY_NONINVERTED = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */\r
+}TIM5_ExtTRGPolarity_TypeDef;\r
+\r
+/**\r
+ * @brief Macro TIM5 Trigger Polarity\r
+ */\r
+#define IS_TIM5_EXT_POLARITY_OK(POLARITY) \\r
+ (((POLARITY) == TIM5_EXTTRGPOLARITY_INVERTED) || \\r
+ ((POLARITY) == TIM5_EXTTRGPOLARITY_NONINVERTED))\r
+ \r
+/**\r
+ * @brief Macro TIM5 External Trigger Filter\r
+ */\r
+#define IS_TIM5_EXT_FILTER_OK(EXTFILTER) ((EXTFILTER) <= 0x0F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM5_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM5_DeInit(void);\r
+void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler, uint16_t TIM5_Period);\r
+void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode, TIM5_OutputState_TypeDef TIM5_OutputState,uint16_t TIM5_Pulse, TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);\r
+void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, TIM5_ICPolarity_TypeDef TIM5_ICPolarity, TIM5_ICSelection_TypeDef TIM5_ICSelection, TIM5_ICPSC_TypeDef TIM5_ICPrescaler, uint8_t TIM5_ICFilter);\r
+void TIM5_Cmd(FunctionalState NewState);\r
+void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);\r
+void TIM5_InternalClockConfig(void);\r
+void TIM5_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);\r
+void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);\r
+void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);\r
+void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);\r
+void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);\r
+void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);\r
+void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);\r
+void TIM5_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM5_CCPreloadControl(FunctionalState NewState);\r
+void TIM5_OC1PreloadConfig(FunctionalState NewState);\r
+void TIM5_OC2PreloadConfig(FunctionalState NewState);\r
+void TIM5_OC3PreloadConfig(FunctionalState NewState);\r
+void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);\r
+void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);\r
+void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);\r
+void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);\r
+void TIM5_SetCounter(uint16_t Counter);\r
+void TIM5_SetAutoreload(uint16_t Autoreload);\r
+void TIM5_SetCompare1(uint16_t Compare1);\r
+void TIM5_SetCompare2(uint16_t Compare2);\r
+void TIM5_SetCompare3(uint16_t Compare3);\r
+void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);\r
+void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);\r
+void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler);\r
+uint16_t TIM5_GetCapture1(void);\r
+uint16_t TIM5_GetCapture2(void);\r
+uint16_t TIM5_GetCapture3(void);\r
+uint16_t TIM5_GetCounter(void);\r
+TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);\r
+FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);\r
+void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);\r
+ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);\r
+void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);\r
+void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource);\r
+void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);\r
+void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM5_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim6.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the TIM6 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_TIM6_H\r
+#define __STM8S_TIM6_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported variables ------------------------------------------------------- */\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM6_Exported_Types\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief TIM6 Prescaler\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_PRESCALER_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/\r
+ TIM6_PRESCALER_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */\r
+ TIM6_PRESCALER_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */\r
+ TIM6_PRESCALER_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */\r
+ TIM6_PRESCALER_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */\r
+ TIM6_PRESCALER_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */\r
+ TIM6_PRESCALER_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */\r
+ TIM6_PRESCALER_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */\r
+}TIM6_Prescaler_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 One Pulse Mode\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_OPMODE_SINGLE = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */\r
+ TIM6_OPMODE_REPETITIVE = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */\r
+}TIM6_OPMode_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Prescaler Reload Mode\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_PSCRELOADMODE_UPDATE =((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/\r
+ TIM6_PSCRELOADMODE_IMMEDIATE =((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/\r
+}TIM6_PSCReloadMode_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Update Source\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_UPDATESOURCE_GLOBAL =((uint8_t)0x00), /*!< Global Update request source */\r
+ TIM6_UPDATESOURCE_REGULAR =((uint8_t)0x01) /*!< Regular Update request source */\r
+}TIM6_UpdateSource_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Event Source\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_EVENTSOURCE_UPDATE = ((uint8_t)0x01), /*!< Update Event*/\r
+ TIM6_EVENTSOURCE_TRIGGER = ((uint8_t)0x40) /*!< Trigger Event*/\r
+}TIM6_EventSource_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Trigger Output Source\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_TRGOSOURCE_RESET = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/\r
+ TIM6_TRGOSOURCE_ENABLE = ((uint8_t)0x10), /*!< Trigger Output source = TIM5 is enabled*/\r
+ TIM6_TRGOSOURCE_UPDATE = ((uint8_t)0x20) /*!< Trigger Output source = Update event*/\r
+}TIM6_TRGOSource_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Slave Mode\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_SLAVEMODE_DISABLE = ((uint8_t)0x00), /*!< Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIM6_SLAVEMODE_RESET = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/\r
+ TIM6_SLAVEMODE_GATED = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/\r
+ TIM6_SLAVEMODE_TRIGGER = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/\r
+ TIM6_SLAVEMODE_EXTERNAL1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/\r
+}TIM6_SlaveMode_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Flags\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_FLAG_UPDATE = ((uint8_t)0x01), /*!< Update Flag */\r
+ TIM6_FLAG_TRIGGER = ((uint8_t)0x40) /*!< Trigger Flag */\r
+}TIM6_FLAG_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 interrupt sources\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_IT_UPDATE = ((uint8_t)0x01), /*!< Update Interrupt*/\r
+ TIM6_IT_TRIGGER = ((uint8_t)0x40) /*!< Trigger Interrupt*/\r
+}TIM6_IT_TypeDef;\r
+\r
+/**\r
+ * @brief TIM6 Internal Trigger Selection\r
+ */\r
+typedef enum\r
+{\r
+ TIM6_TS_TIM1 = ((uint8_t)0x20),/*!< TRIG Input source = TIM1 TRIG Output */\r
+ TIM6_TS_TIM5 = ((uint8_t)0x30) /*!< TRIG Input source = TIM5 TRIG Output */\r
+}TIM6_TS_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros -----------------------------------------------------------*/\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM6_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro TIM6 Prescaler\r
+ */\r
+#define IS_TIM6_PRESCALER_OK(PRESCALER) \\r
+ (((PRESCALER) == TIM6_PRESCALER_1) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_2) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_4) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_8) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_16) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_32) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_64) || \\r
+ ((PRESCALER) == TIM6_PRESCALER_128))\r
+/**\r
+ * @brief Macro TIM6 One Pulse Mode\r
+ */\r
+#define IS_TIM6_OPM_MODE_OK(MODE) \\r
+ (((MODE) == TIM6_OPMODE_SINGLE) || \\r
+ ((MODE) == TIM6_OPMODE_REPETITIVE))\r
+\r
+/**\r
+ * @brief Macro TIM6 Prescaler reload\r
+ */\r
+#define IS_TIM6_PRESCALER_RELOAD_OK(RELOAD) \\r
+ (((RELOAD) == TIM6_PSCRELOADMODE_UPDATE) || \\r
+ ((RELOAD) == TIM6_PSCRELOADMODE_IMMEDIATE))\r
+/**\r
+ * @brief Macro TIM6 Update source\r
+ */\r
+#define IS_TIM6_UPDATE_SOURCE_OK(SOURCE) \\r
+ (((SOURCE) == TIM6_UPDATESOURCE_GLOBAL) || \\r
+ ((SOURCE) == TIM6_UPDATESOURCE_REGULAR))\r
+/**\r
+ * @brief Macro TIM6 Event source\r
+ */\r
+#define IS_TIM6_EVENT_SOURCE_OK(SOURCE) \\r
+ ((((SOURCE) & (uint8_t)0xBE) == 0x00) && \\r
+ ((SOURCE) != 0x00))\r
+\r
+/**\r
+ * @brief Macro TIM6 TRGO source\r
+ */\r
+#define IS_TIM6_TRGO_SOURCE_OK(SOURCE) \\r
+ (((SOURCE) == TIM6_TRGOSOURCE_RESET) || \\r
+ ((SOURCE) == TIM6_TRGOSOURCE_ENABLE)|| \\r
+ ((SOURCE) == TIM6_TRGOSOURCE_UPDATE))\r
+/**\r
+ * @brief Macro TIM6 Slave mode\r
+ */\r
+#define IS_TIM6_SLAVE_MODE_OK(MODE) \\r
+ (((MODE) == TIM6_SLAVEMODE_DISABLE) || \\r
+ ((MODE) == TIM6_SLAVEMODE_RESET) || \\r
+ ((MODE) == TIM6_SLAVEMODE_GATED) || \\r
+ ((MODE) == TIM6_SLAVEMODE_TRIGGER) || \\r
+ ((MODE) == TIM6_SLAVEMODE_EXTERNAL1))\r
+/**\r
+ * @brief Macro TIM6 Flags\r
+ */\r
+#define IS_TIM6_GET_FLAG_OK(FLAG) \\r
+ (((FLAG) == TIM6_FLAG_UPDATE) || \\r
+ ((FLAG) == TIM6_FLAG_TRIGGER))\r
+\r
+#define IS_TIM6_CLEAR_FLAG_OK(FLAG) \\r
+ ((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))\r
+/**\r
+ * @brief Macro TIM6 interrupts\r
+ */\r
+#define IS_TIM6_IT_OK(IT) \\r
+ (((IT) != 0x00) && \\r
+ (((IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))\r
+\r
+#define IS_TIM6_GET_IT_OK(IT) \\r
+ (((IT) == TIM6_IT_UPDATE) || \\r
+ ((IT) == TIM6_IT_TRIGGER))\r
+/**\r
+ * @brief Macro TIM6 Trigger selection\r
+ */\r
+#define IS_TIM6_TRIGGER_SELECTION_OK(SELECTION) \\r
+ (((SELECTION) == TIM6_TS_TIM5) || \\r
+ ((SELECTION) == TIM6_TS_TIM1))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions --------------------------------------------------------*/\r
+\r
+/** @addtogroup TIM6_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM6_DeInit(void);\r
+void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler, uint8_t TIM6_Period);\r
+void TIM6_Cmd(FunctionalState NewState);\r
+void TIM6_UpdateDisableConfig(FunctionalState NewState);\r
+void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource);\r
+void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode);\r
+void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler, TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode);\r
+void TIM6_ARRPreloadConfig(FunctionalState NewState);\r
+void TIM6_SetCounter(uint8_t Counter);\r
+void TIM6_SetAutoreload(uint8_t Autoreload);\r
+uint8_t TIM6_GetCounter(void);\r
+TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void);\r
+void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState);\r
+void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG);\r
+ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT);\r
+void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource);\r
+FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG);\r
+void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT);\r
+void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource);\r
+void TIM6_SelectMasterSlaveMode(FunctionalState NewState);\r
+void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource);\r
+void TIM6_InternalClockConfig(void);\r
+void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_TIM6_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart1.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototypes and macros for the UART1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_UART1_H\r
+#define __STM8S_UART1_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART1_Exported_Types\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief UART1 Irda Modes\r
+ */\r
+\r
+typedef enum { UART1_IRDAMODE_NORMAL = (uint8_t)0x00, /**< 0x00 Irda Normal Mode */\r
+ UART1_IRDAMODE_LOWPOWER = (uint8_t)0x01 /**< 0x01 Irda Low Power Mode */\r
+ } UART1_IrDAMode_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 WakeUP Modes\r
+ */\r
+typedef enum { UART1_WAKEUP_IDLELINE = (uint8_t)0x00, /**< 0x01 Idle Line wake up */\r
+ UART1_WAKEUP_ADDRESSMARK = (uint8_t)0x08 /**< 0x02 Address Mark wake up */\r
+ } UART1_WakeUp_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 LIN Break detection length possible values\r
+ */\r
+typedef enum { UART1_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection */\r
+ UART1_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 /**< 0x02 11 bits Lin Break detection */\r
+ } UART1_LINBreakDetectionLength_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 stop bits possible values\r
+ */\r
+\r
+typedef enum { UART1_STOPBITS_1 = (uint8_t)0x00, /**< One stop bit is transmitted at the end of frame*/\r
+ UART1_STOPBITS_0_5 = (uint8_t)0x10, /**< Half stop bits is transmitted at the end of frame*/\r
+ UART1_STOPBITS_2 = (uint8_t)0x20, /**< Two stop bits are transmitted at the end of frame*/\r
+ UART1_STOPBITS_1_5 = (uint8_t)0x30 /**< One and half stop bits*/\r
+ } UART1_StopBits_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 parity possible values\r
+ */\r
+typedef enum { UART1_PARITY_NO = (uint8_t)0x00, /**< No Parity*/\r
+ UART1_PARITY_EVEN = (uint8_t)0x04, /**< Even Parity*/\r
+ UART1_PARITY_ODD = (uint8_t)0x06 /**< Odd Parity*/\r
+ } UART1_Parity_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 Synchrone modes\r
+ */\r
+typedef enum { UART1_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */\r
+ UART1_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable */\r
+ UART1_SYNCMODE_CPOL_LOW = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */\r
+ UART1_SYNCMODE_CPOL_HIGH = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */\r
+ UART1_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit */\r
+ UART1_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit */\r
+ UART1_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */\r
+ UART1_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01 /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */\r
+ } UART1_SyncMode_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 Word length possible values\r
+ */\r
+typedef enum { UART1_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data */\r
+ UART1_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data */\r
+ } UART1_WordLength_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 Mode possible values\r
+ */\r
+typedef enum { UART1_MODE_RX_ENABLE = (uint8_t)0x08, /**< 0x08 Receive Enable */\r
+ UART1_MODE_TX_ENABLE = (uint8_t)0x04, /**< 0x04 Transmit Enable */\r
+ UART1_MODE_TX_DISABLE = (uint8_t)0x80, /**< 0x80 Transmit Disable */\r
+ UART1_MODE_RX_DISABLE = (uint8_t)0x40, /**< 0x40 Single-wire Half-duplex mode */\r
+ UART1_MODE_TXRX_ENABLE = (uint8_t)0x0C /**< 0x0C Transmit Enable and Receive Enable */\r
+ } UART1_Mode_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 Flag possible values\r
+ */\r
+typedef enum { UART1_FLAG_TXE = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */\r
+ UART1_FLAG_TC = (uint16_t)0x0040, /*!< Transmission Complete flag */\r
+ UART1_FLAG_RXNE = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */\r
+ UART1_FLAG_IDLE = (uint16_t)0x0010, /*!< Idle line detected flag */\r
+ UART1_FLAG_OR = (uint16_t)0x0008, /*!< OverRun error flag */\r
+ UART1_FLAG_NF = (uint16_t)0x0004, /*!< Noise error flag */\r
+ UART1_FLAG_FE = (uint16_t)0x0002, /*!< Framing Error flag */\r
+ UART1_FLAG_PE = (uint16_t)0x0001, /*!< Parity Error flag */\r
+ UART1_FLAG_LBDF = (uint16_t)0x0210, /*!< Line Break Detection Flag */\r
+ UART1_FLAG_SBK = (uint16_t)0x0101 /*!< Send Break characters Flag */\r
+ } UART1_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief UART1 Interrupt definition\r
+ * UART1_IT possible values\r
+ * Elements values convention: 0xZYX\r
+ * X: Position of the corresponding Interrupt\r
+ * - For the following values, X means the interrupt position in the CR2 register.\r
+ * UART1_IT_TXE\r
+ * UART1_IT_TC\r
+ * UART1_IT_RXNE\r
+ * UART1_IT_IDLE \r
+ * UART1_IT_OR \r
+ * - For the UART1_IT_PE value, X means the flag position in the CR1 register.\r
+ * - For the UART1_IT_LBDF value, X means the flag position in the CR4 register.\r
+ * Y: Flag position\r
+ * - For the following values, Y means the flag (pending bit) position in the SR register.\r
+ * UART1_IT_TXE\r
+ * UART1_IT_TC\r
+ * UART1_IT_RXNE\r
+ * UART1_IT_IDLE \r
+ * UART1_IT_OR\r
+ * UART1_IT_PE\r
+ * - For the UART1_IT_LBDF value, Y means the flag position in the CR4 register.\r
+ * Z: Register index: indicate in which register the dedicated interrupt source is:\r
+ * - 1==> CR1 register\r
+ * - 2==> CR2 register\r
+ * - 3==> CR4 register\r
+ */\r
+typedef enum { UART1_IT_TXE = (uint16_t)0x0277, /*!< Transmit interrupt */\r
+ UART1_IT_TC = (uint16_t)0x0266, /*!< Transmission Complete interrupt */\r
+ UART1_IT_RXNE = (uint16_t)0x0255, /*!< Receive interrupt */\r
+ UART1_IT_IDLE = (uint16_t)0x0244, /*!< IDLE line interrupt */\r
+ UART1_IT_OR = (uint16_t)0x0235, /*!< Overrun Error interrupt */\r
+ UART1_IT_PE = (uint16_t)0x0100, /*!< Parity Error interrupt */\r
+ UART1_IT_LBDF = (uint16_t)0x0346, /**< LIN break detection interrupt */\r
+ UART1_IT_RXNE_OR = (uint16_t)0x0205 /*!< Receive/Overrun interrupt */\r
+ } UART1_IT_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART1_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the MODEs possible combination should be one of\r
+ * the following\r
+ */\r
+#define IS_UART1_MODE_OK(Mode) \\r
+ (((Mode) == (uint8_t)UART1_MODE_RX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART1_MODE_RX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART1_MODE_TX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART1_MODE_TX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART1_MODE_TXRX_ENABLE) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_ENABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_ENABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART1_MODE_TX_DISABLE|(uint8_t)UART1_MODE_RX_ENABLE)))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WordLengths\r
+ */\r
+#define IS_UART1_WORDLENGTH_OK(WordLength) \\r
+ (((WordLength) == UART1_WORDLENGTH_8D) || \\r
+ ((WordLength) == UART1_WORDLENGTH_9D))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the SyncModes; it should exclude values such \r
+ * as UART1_CLOCK_ENABLE|UART1_CLOCK_DISABLE\r
+ */\r
+#define IS_UART1_SYNCMODE_OK(SyncMode) \\r
+ (!((((SyncMode)&(((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART1_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART1_SYNCMODE_CLOCK_DISABLE))) \\r
+ || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART1_SYNCMODE_CPOL_LOW )|((uint8_t)UART1_SYNCMODE_CPOL_HIGH))) \\r
+ ||(((SyncMode)&(((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART1_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART1_SYNCMODE_CPHA_BEGINING))) \\r
+ || (((SyncMode)&(((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART1_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART1_SYNCMODE_LASTBIT_ENABLE)))))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the FLAGs\r
+ */\r
+#define IS_UART1_FLAG_OK(Flag) \\r
+ (((Flag) == UART1_FLAG_TXE) || \\r
+ ((Flag) == UART1_FLAG_TC) || \\r
+ ((Flag) == UART1_FLAG_RXNE) || \\r
+ ((Flag) == UART1_FLAG_IDLE) || \\r
+ ((Flag) == UART1_FLAG_OR) || \\r
+ ((Flag) == UART1_FLAG_NF) || \\r
+ ((Flag) == UART1_FLAG_FE) || \\r
+ ((Flag) == UART1_FLAG_PE) || \\r
+ ((Flag) == UART1_FLAG_SBK) || \\r
+ ((Flag) == UART1_FLAG_LBDF))\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the FLAGs that can be cleared by writing 0\r
+ */\r
+#define IS_UART1_CLEAR_FLAG_OK(Flag) \\r
+ (((Flag) == UART1_FLAG_RXNE) || \\r
+ ((Flag) == UART1_FLAG_LBDF))\r
+\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different \r
+ * sensitivity values for the Interrupts\r
+ */\r
+\r
+#define IS_UART1_CONFIG_IT_OK(Interrupt) \\r
+ (((Interrupt) == UART1_IT_PE) || \\r
+ ((Interrupt) == UART1_IT_TXE) || \\r
+ ((Interrupt) == UART1_IT_TC) || \\r
+ ((Interrupt) == UART1_IT_RXNE_OR ) || \\r
+ ((Interrupt) == UART1_IT_IDLE) || \\r
+ ((Interrupt) == UART1_IT_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit\r
+ */\r
+#define IS_UART1_GET_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART1_IT_TXE) || \\r
+ ((ITPendingBit) == UART1_IT_TC) || \\r
+ ((ITPendingBit) == UART1_IT_RXNE) || \\r
+ ((ITPendingBit) == UART1_IT_IDLE) || \\r
+ ((ITPendingBit) == UART1_IT_OR) || \\r
+ ((ITPendingBit) == UART1_IT_LBDF) || \\r
+ ((ITPendingBit) == UART1_IT_PE))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit that can be cleared by writing 0\r
+ */\r
+#define IS_UART1_CLEAR_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART1_IT_RXNE) || \\r
+ ((ITPendingBit) == UART1_IT_LBDF))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the IrDAModes\r
+ */\r
+#define IS_UART1_IRDAMODE_OK(IrDAMode) \\r
+ (((IrDAMode) == UART1_IRDAMODE_LOWPOWER) || \\r
+ ((IrDAMode) == UART1_IRDAMODE_NORMAL))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WakeUps\r
+ */\r
+#define IS_UART1_WAKEUP_OK(WakeUp) \\r
+ (((WakeUp) == UART1_WAKEUP_IDLELINE) || \\r
+ ((WakeUp) == UART1_WAKEUP_ADDRESSMARK))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different \r
+ * sensitivity values for the LINBreakDetectionLengths\r
+ */\r
+#define IS_UART1_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \\r
+ (((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_10BITS) || \\r
+ ((LINBreakDetectionLength) == UART1_LINBREAKDETECTIONLENGTH_11BITS))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the UART1_StopBits\r
+ */\r
+#define IS_UART1_STOPBITS_OK(StopBit) (((StopBit) == UART1_STOPBITS_1) || \\r
+ ((StopBit) == UART1_STOPBITS_0_5) || \\r
+ ((StopBit) == UART1_STOPBITS_2) || \\r
+ ((StopBit) == UART1_STOPBITS_1_5 ))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the Paritys\r
+ */\r
+#define IS_UART1_PARITY_OK(Parity) (((Parity) == UART1_PARITY_NO) || \\r
+ ((Parity) == UART1_PARITY_EVEN) || \\r
+ ((Parity) == UART1_PARITY_ODD ))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the maximum\r
+ * baudrate value\r
+ */\r
+#define IS_UART1_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the address\r
+ * of the UART1 or UART node\r
+ */\r
+#define UART1_ADDRESS_MAX ((uint8_t)16)\r
+#define IS_UART1_ADDRESS_OK(node) ((node) < UART1_ADDRESS_MAX )\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup UART1_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void UART1_DeInit(void);\r
+void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, \r
+ UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, \r
+ UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode);\r
+void UART1_Cmd(FunctionalState NewState);\r
+void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState);\r
+void UART1_HalfDuplexCmd(FunctionalState NewState);\r
+void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode);\r
+void UART1_IrDACmd(FunctionalState NewState);\r
+void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength);\r
+void UART1_LINCmd(FunctionalState NewState);\r
+void UART1_SmartCardCmd(FunctionalState NewState);\r
+void UART1_SmartCardNACKCmd(FunctionalState NewState);\r
+void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp);\r
+void UART1_ReceiverWakeUpCmd(FunctionalState NewState);\r
+uint8_t UART1_ReceiveData8(void);\r
+uint16_t UART1_ReceiveData9(void);\r
+void UART1_SendData8(uint8_t Data);\r
+void UART1_SendData9(uint16_t Data);\r
+void UART1_SendBreak(void);\r
+void UART1_SetAddress(uint8_t UART1_Address);\r
+void UART1_SetGuardTime(uint8_t UART1_GuardTime);\r
+void UART1_SetPrescaler(uint8_t UART1_Prescaler);\r
+FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG);\r
+void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG);\r
+ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT);\r
+void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_UART1_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart2.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototypes and macros for the UART2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_UART2_H\r
+#define __STM8S_UART2_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART2_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART2 Irda Modes\r
+ */\r
+\r
+typedef enum { UART2_IRDAMODE_NORMAL = (uint8_t)0x00, /**< 0x00 Irda Normal Mode */\r
+ UART2_IRDAMODE_LOWPOWER = (uint8_t)0x01 /**< 0x01 Irda Low Power Mode */\r
+\r
+ } UART2_IrDAMode_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 WakeUP Modes\r
+ */\r
+\r
+typedef enum { UART2_WAKEUP_IDLELINE = (uint8_t)0x00, /**< 0x01 Idle Line wake up */\r
+ UART2_WAKEUP_ADDRESSMARK = (uint8_t)0x08 /**< 0x02 Address Mark wake up */\r
+ } UART2_WakeUp_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief UART2 LIN Break detection length possible values\r
+ */\r
+typedef enum { UART2_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 0x01 10 bits Lin Break detection */\r
+ UART2_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 /**< 0x02 11 bits Lin Break detection */\r
+ } UART2_LINBreakDetectionLength_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 stop bits possible values\r
+ */\r
+\r
+typedef enum { UART2_STOPBITS_1 = (uint8_t)0x00, /**< One stop bit is transmitted at the end of frame*/\r
+ UART2_STOPBITS_0_5 = (uint8_t)0x10, /**< Half stop bits is transmitted at the end of frame*/\r
+ UART2_STOPBITS_2 = (uint8_t)0x20, /**< Two stop bits are transmitted at the end of frame*/\r
+ UART2_STOPBITS_1_5 = (uint8_t)0x30 /**< One and half stop bits*/\r
+ } UART2_StopBits_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief UART2 parity possible values\r
+ */\r
+typedef enum { UART2_PARITY_NO = (uint8_t)0x00, /**< No Parity*/\r
+ UART2_PARITY_EVEN = (uint8_t)0x04, /**< Even Parity*/\r
+ UART2_PARITY_ODD = (uint8_t)0x06 /**< Odd Parity*/\r
+ } UART2_Parity_TypeDef;\r
+/**\r
+ * @brief UART2 Mode possible values\r
+ */\r
+typedef enum { UART2_LIN_MODE_MASTER = (uint8_t)0x00, /**< LIN Master Mode*/\r
+ UART2_LIN_MODE_SLAVE = (uint8_t)0x01 /**< LIN Slave Mode*/\r
+ } UART2_LinMode_TypeDef;\r
+/**\r
+ * @brief UART2 automatic resynchronisation possible values\r
+ */\r
+typedef enum { UART2_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, /**< LIN Autosynchronization Disable*/\r
+ UART2_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 /**< LIN Autosynchronization Enable*/\r
+ } UART2_LinAutosync_TypeDef;\r
+/**\r
+ * @brief UART2 Divider Update Method possible values\r
+ */\r
+typedef enum { UART2_LIN_DIVUP_LBRR1 = (uint8_t)0x00, /**< LIN LDIV is updated as soon as LBRR1 is written*/\r
+ UART2_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 /**< LIN LDIV is updated at the next received character*/\r
+ } UART2_LinDivUp_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 Synchrone modes\r
+ */\r
+typedef enum { UART2_SYNCMODE_CLOCK_DISABLE = (uint8_t)0x80, /**< 0x80 Sync mode Disable, SLK pin Disable */\r
+ UART2_SYNCMODE_CLOCK_ENABLE = (uint8_t)0x08, /**< 0x08 Sync mode Enable, SLK pin Enable */\r
+ UART2_SYNCMODE_CPOL_LOW = (uint8_t)0x40, /**< 0x40 Steady low value on SCLK pin outside transmission window */\r
+ UART2_SYNCMODE_CPOL_HIGH = (uint8_t)0x04, /**< 0x04 Steady high value on SCLK pin outside transmission window */\r
+ UART2_SYNCMODE_CPHA_MIDDLE = (uint8_t)0x20, /**< 0x20 SCLK clock line activated in middle of data bit */\r
+ UART2_SYNCMODE_CPHA_BEGINING = (uint8_t)0x02, /**< 0x02 SCLK clock line activated at beginning of data bit */\r
+ UART2_SYNCMODE_LASTBIT_DISABLE = (uint8_t)0x10, /**< 0x10 The clock pulse of the last data bit is not output to the SCLK pin */\r
+ UART2_SYNCMODE_LASTBIT_ENABLE = (uint8_t)0x01 /**< 0x01 The clock pulse of the last data bit is output to the SCLK pin */\r
+ } UART2_SyncMode_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 Word length possible values\r
+ */\r
+typedef enum { UART2_WORDLENGTH_8D = (uint8_t)0x00,/**< 0x00 8 bits Data */\r
+ UART2_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data */\r
+ } UART2_WordLength_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 Mode possible values\r
+ */\r
+typedef enum { UART2_MODE_RX_ENABLE = (uint8_t)0x08, /**< 0x08 Receive Enable */\r
+ UART2_MODE_TX_ENABLE = (uint8_t)0x04, /**< 0x04 Transmit Enable */\r
+ UART2_MODE_TX_DISABLE = (uint8_t)0x80, /**< 0x80 Transmit Disable */\r
+ UART2_MODE_RX_DISABLE = (uint8_t)0x40, /**< 0x40 Single-wire Half-duplex mode */\r
+ UART2_MODE_TXRX_ENABLE = (uint8_t)0x0C /**< 0x0C Transmit Enable and Receive Enable */\r
+ } UART2_Mode_TypeDef;\r
+/**\r
+ * @brief UART2 Flag possible values\r
+ */\r
+typedef enum\r
+{\r
+ UART2_FLAG_TXE = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */\r
+ UART2_FLAG_TC = (uint16_t)0x0040, /*!< Transmission Complete flag */\r
+ UART2_FLAG_RXNE = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */\r
+ UART2_FLAG_IDLE = (uint16_t)0x0010, /*!< Idle line detected flag */\r
+ UART2_FLAG_OR_LHE = (uint16_t)0x0008, /*!< OverRun error flag */\r
+ UART2_FLAG_NF = (uint16_t)0x0004, /*!< Noise error flag */\r
+ UART2_FLAG_FE = (uint16_t)0x0002, /*!< Framing Error flag */\r
+ UART2_FLAG_PE = (uint16_t)0x0001, /*!< Parity Error flag */\r
+ UART2_FLAG_SBK = (uint16_t)0x0101, /**< Send Break Complete interrupt flag */\r
+ UART2_FLAG_LBDF = (uint16_t)0x0210, /**< LIN Break Detection Flag */\r
+ UART2_FLAG_LHDF = (uint16_t)0x0302, /**< LIN Header Detection Flag*/\r
+ UART2_FLAG_LSF = (uint16_t)0x0301 /**< LIN Sync Field Flag*/\r
+} UART2_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief UART2 Interrupt definition\r
+ * UART2_IT possible values\r
+ * Elements values convention: 0xZYX\r
+ * X: Position of the corresponding Interrupt\r
+ * - For the following values, X means the interrupt position in the CR2 register.\r
+ * UART2_IT_TXE\r
+ * UART2_IT_TC\r
+ * UART2_IT_RXNE\r
+ * UART2_IT_IDLE \r
+ * UART2_IT_OR \r
+ * - For the UART2_IT_PE value, X means the flag position in the CR1 register.\r
+ * - For the UART2_IT_LBDF value, X means the flag position in the CR4 register.\r
+ * - For the UART2_IT_LHDF value, X means the flag position in the CR6 register.\r
+ * Y: Flag position\r
+ * - For the following values, Y means the flag (pending bit) position in the SR register.\r
+ * UART2_IT_TXE\r
+ * UART2_IT_TC\r
+ * UART2_IT_RXNE\r
+ * UART2_IT_IDLE \r
+ * UART2_IT_OR\r
+ * UART2_IT_PE\r
+ * - For the UART2_IT_LBDF value, Y means the flag position in the CR4 register.\r
+ * - For the UART2_IT_LHDF value, Y means the flag position in the CR6 register.\r
+ * Z: Register index: indicate in which register the dedicated interrupt source is:\r
+ * - 1==> CR1 register\r
+ * - 2==> CR2 register\r
+ * - 3==> CR4 register\r
+ * - 4==> CR6 register\r
+ */\r
+typedef enum { UART2_IT_TXE = (uint16_t)0x0277, /**< Transmit interrupt */\r
+ UART2_IT_TC = (uint16_t)0x0266, /**< Transmission Complete interrupt */\r
+ UART2_IT_RXNE = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */\r
+ UART2_IT_IDLE = (uint16_t)0x0244, /**< Idle line detected interrupt */\r
+ UART2_IT_OR = (uint16_t)0x0235, /**< OverRun error interrupt */\r
+ UART2_IT_PE = (uint16_t)0x0100, /**< Parity Error interrupt */\r
+ UART2_IT_LBDF = (uint16_t)0x0346, /**< LIN Break Detection interrupt */\r
+ UART2_IT_LHDF = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/\r
+ UART2_IT_RXNE_OR = (uint16_t)0x0205 /*!< Receive/Overrun interrupt */\r
+ } UART2_IT_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART2_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function to check the different functions parameters.\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the MODEs possible combination should be one of\r
+ * the following.\r
+ */\r
+ \r
+#define IS_UART2_MODE_OK(Mode) \\r
+ (((Mode) == (uint8_t)UART2_MODE_RX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART2_MODE_RX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART2_MODE_TX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART2_MODE_TX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART2_MODE_TXRX_ENABLE) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_ENABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_ENABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART2_MODE_TX_DISABLE|(uint8_t)UART2_MODE_RX_ENABLE)))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WordLengths\r
+ */\r
+#define IS_UART2_WORDLENGTH_OK(WordLength) \\r
+ (((WordLength) == UART2_WORDLENGTH_8D) || \\r
+ ((WordLength) == UART2_WORDLENGTH_9D))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the SyncModes; it should exclude values such \r
+ * as UART2_CLOCK_ENABLE|UART2_CLOCK_DISABLE\r
+ */\r
+#define IS_UART2_SYNCMODE_OK(SyncMode) \\r
+ (!((((SyncMode)&(((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) == (((uint8_t)UART2_SYNCMODE_CLOCK_ENABLE)|((uint8_t)UART2_SYNCMODE_CLOCK_DISABLE))) || \\r
+ (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) == (((uint8_t)UART2_SYNCMODE_CPOL_LOW )|((uint8_t)UART2_SYNCMODE_CPOL_HIGH))) || \\r
+ (((SyncMode)&(((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) == (((uint8_t)UART2_SYNCMODE_CPHA_MIDDLE)|((uint8_t)UART2_SYNCMODE_CPHA_BEGINING))) || \\r
+ (((SyncMode)&(((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE))) == (((uint8_t)UART2_SYNCMODE_LASTBIT_DISABLE)|((uint8_t)UART2_SYNCMODE_LASTBIT_ENABLE)))))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the FLAGs\r
+ */\r
+#define IS_UART2_FLAG_OK(Flag) \\r
+ (((Flag) == UART2_FLAG_TXE) || \\r
+ ((Flag) == UART2_FLAG_TC) || \\r
+ ((Flag) == UART2_FLAG_RXNE) || \\r
+ ((Flag) == UART2_FLAG_IDLE) || \\r
+ ((Flag) == UART2_FLAG_OR_LHE) || \\r
+ ((Flag) == UART2_FLAG_NF) || \\r
+ ((Flag) == UART2_FLAG_FE) || \\r
+ ((Flag) == UART2_FLAG_PE) || \\r
+ ((Flag) == UART2_FLAG_SBK) || \\r
+ ((Flag) == UART2_FLAG_LSF) || \\r
+ ((Flag) == UART2_FLAG_LHDF) || \\r
+ ((Flag) == UART2_FLAG_LBDF))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the FLAGs that can be cleared by writing 0\r
+ */\r
+#define IS_UART2_CLEAR_FLAG_OK(Flag) \\r
+ (((Flag) == UART2_FLAG_RXNE) || \\r
+ ((Flag) == UART2_FLAG_LHDF) || \\r
+ ((Flag) == UART2_FLAG_LSF) || \\r
+ ((Flag) == UART2_FLAG_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check \r
+ * the different sensitivity values for the Interrupts\r
+ */\r
+\r
+#define IS_UART2_CONFIG_IT_OK(Interrupt) \\r
+ (((Interrupt) == UART2_IT_PE) || \\r
+ ((Interrupt) == UART2_IT_TXE) || \\r
+ ((Interrupt) == UART2_IT_TC) || \\r
+ ((Interrupt) == UART2_IT_RXNE_OR ) || \\r
+ ((Interrupt) == UART2_IT_IDLE) || \\r
+ ((Interrupt) == UART2_IT_LHDF) || \\r
+ ((Interrupt) == UART2_IT_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit\r
+ */\r
+#define IS_UART2_GET_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART2_IT_TXE) || \\r
+ ((ITPendingBit) == UART2_IT_TC) || \\r
+ ((ITPendingBit) == UART2_IT_RXNE) || \\r
+ ((ITPendingBit) == UART2_IT_IDLE) || \\r
+ ((ITPendingBit) == UART2_IT_OR) || \\r
+ ((ITPendingBit) == UART2_IT_LBDF) || \\r
+ ((ITPendingBit) == UART2_IT_LHDF) || \\r
+ ((ITPendingBit) == UART2_IT_PE))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit that can be cleared by writing 0\r
+ */\r
+#define IS_UART2_CLEAR_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART2_IT_RXNE) || \\r
+ ((ITPendingBit) == UART2_IT_LHDF) || \\r
+ ((ITPendingBit) == UART2_IT_LBDF))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the IrDAModes\r
+ */\r
+#define IS_UART2_IRDAMODE_OK(IrDAMode) \\r
+ (((IrDAMode) == UART2_IRDAMODE_LOWPOWER) || \\r
+ ((IrDAMode) == UART2_IRDAMODE_NORMAL))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WakeUps\r
+ */\r
+#define IS_UART2_WAKEUP_OK(WakeUp) \\r
+ (((WakeUp) == UART2_WAKEUP_IDLELINE) || \\r
+ ((WakeUp) == UART2_WAKEUP_ADDRESSMARK))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the LINBreakDetectionLengths\r
+ */\r
+#define IS_UART2_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLength) \\r
+ (((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_10BITS) || \\r
+ ((LINBreakDetectionLength) == UART2_LINBREAKDETECTIONLENGTH_11BITS))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the UART2_StopBits\r
+ */\r
+#define IS_UART2_STOPBITS_OK(StopBit) (((StopBit) == UART2_STOPBITS_1) || \\r
+ ((StopBit) == UART2_STOPBITS_0_5) || \\r
+ ((StopBit) == UART2_STOPBITS_2) || \\r
+ ((StopBit) == UART2_STOPBITS_1_5 ))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the Paritys\r
+ */\r
+#define IS_UART2_PARITY_OK(Parity) (((Parity) == UART2_PARITY_NO) || \\r
+ ((Parity) == UART2_PARITY_EVEN) || \\r
+ ((Parity) == UART2_PARITY_ODD ))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the maximum\r
+ * baudrate value\r
+ */\r
+#define IS_UART2_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the address \r
+ * of the UART2 or UART node\r
+ */\r
+#define UART2_ADDRESS_MAX ((uint8_t)16)\r
+#define IS_UART2_ADDRESS_OK(node) ((node) < UART2_ADDRESS_MAX )\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN mode\r
+ */\r
+#define IS_UART2_SLAVE_OK(Mode) \\r
+ (((Mode) == UART2_LIN_MODE_MASTER) || \\r
+ ((Mode) == UART2_LIN_MODE_SLAVE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN \r
+ * automatic resynchronization mode\r
+ */\r
+#define IS_UART2_AUTOSYNC_OK(AutosyncMode) \\r
+ (((AutosyncMode) == UART2_LIN_AUTOSYNC_ENABLE) || \\r
+ ((AutosyncMode) == UART2_LIN_AUTOSYNC_DISABLE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN divider update method\r
+ */\r
+#define IS_UART2_DIVUP_OK(DivupMethode) \\r
+ (((DivupMethode) == UART2_LIN_DIVUP_LBRR1) || \\r
+ ((DivupMethode) == UART2_LIN_DIVUP_NEXTRXNE))\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup UART2_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void UART2_DeInit(void);\r
+void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, \r
+ UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, \r
+ UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode);\r
+void UART2_Cmd(FunctionalState NewState);\r
+void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState);\r
+void UART2_HalfDuplexCmd(FunctionalState NewState);\r
+void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode);\r
+void UART2_IrDACmd(FunctionalState NewState);\r
+void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength);\r
+void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode, \r
+ UART2_LinAutosync_TypeDef UART2_Autosync, \r
+ UART2_LinDivUp_TypeDef UART2_DivUp);\r
+void UART2_LINCmd(FunctionalState NewState);\r
+void UART2_SmartCardCmd(FunctionalState NewState);\r
+void UART2_SmartCardNACKCmd(FunctionalState NewState);\r
+void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp);\r
+void UART2_ReceiverWakeUpCmd(FunctionalState NewState);\r
+uint8_t UART2_ReceiveData8(void);\r
+uint16_t UART2_ReceiveData9(void);\r
+void UART2_SendData8(uint8_t Data);\r
+void UART2_SendData9(uint16_t Data);\r
+void UART2_SendBreak(void);\r
+void UART2_SetAddress(uint8_t UART2_Address);\r
+void UART2_SetGuardTime(uint8_t UART2_GuardTime);\r
+void UART2_SetPrescaler(uint8_t UART2_Prescaler);\r
+FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG);\r
+void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG);\r
+ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT);\r
+void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_UART2_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart3.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototypes and macros for the UART3 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_UART3_H\r
+#define __STM8S_UART3_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART3_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief UART3 WakeUP Modes\r
+ */\r
+typedef enum { UART3_WAKEUP_IDLELINE = (uint8_t)0x00, /**< 0x01 Idle Line wake up*/\r
+ UART3_WAKEUP_ADDRESSMARK = (uint8_t)0x08 /**< 0x02 Address Mark wake up*/\r
+ } UART3_WakeUp_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 LIN Break detection length possible values\r
+ */\r
+typedef enum { UART3_LINBREAKDETECTIONLENGTH_10BITS = (uint8_t)0x00, /**< 10 bits Lin Break detection */\r
+ UART3_LINBREAKDETECTIONLENGTH_11BITS = (uint8_t)0x01 /**< 11 bits Lin Break detection */\r
+ } UART3_LINBreakDetectionLength_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief UART3 stop bits possible values\r
+ */\r
+typedef enum { UART3_STOPBITS_1 = (uint8_t)0x00, /**< One stop bit is transmitted at the end of frame*/\r
+ UART3_STOPBITS_2 = (uint8_t)0x20 /**< Two stop bits are transmitted at the end of frame*/\r
+ } UART3_StopBits_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 parity possible values\r
+ */\r
+typedef enum { UART3_PARITY_NO = (uint8_t)0x00, /**< No Parity*/\r
+ UART3_PARITY_EVEN = (uint8_t)0x04, /**< Even Parity*/\r
+ UART3_PARITY_ODD = (uint8_t)0x06 /**< Odd Parity*/\r
+ } UART3_Parity_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 Word length possible values\r
+ */\r
+typedef enum { UART3_WORDLENGTH_8D = (uint8_t)0x00, /**< 0x00 8 bits Data*/\r
+ UART3_WORDLENGTH_9D = (uint8_t)0x10 /**< 0x10 9 bits Data*/\r
+ } UART3_WordLength_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 Mode Transmit/Receive possible values\r
+ */\r
+typedef enum { UART3_MODE_RX_ENABLE = (uint8_t)0x08, /**< 0x08 Receive Enable*/\r
+ UART3_MODE_TX_ENABLE = (uint8_t)0x04, /**< 0x04 Transmit Enable*/\r
+ UART3_MODE_TX_DISABLE = (uint8_t)0x80, /**< 0x80 Receive Enable*/\r
+ UART3_MODE_RX_DISABLE = (uint8_t)0x40, /**< 0x40 Single-wire Half-duplex mode*/\r
+ UART3_MODE_TXRX_ENABLE = (uint8_t)0x0C /**< 0x0C Receive Enable and Transmit enable*/\r
+ } UART3_Mode_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 Mode possible values\r
+ */\r
+typedef enum { UART3_LIN_MODE_MASTER = (uint8_t)0x00, /**< LIN Master Mode*/\r
+ UART3_LIN_MODE_SLAVE = (uint8_t)0x01 /**< LIN Slave Mode*/\r
+ } UART3_LinMode_TypeDef;\r
+/**\r
+ * @brief UART3 automatic resynchronisation possible values\r
+ */\r
+typedef enum { UART3_LIN_AUTOSYNC_DISABLE = (uint8_t)0x00, /**< LIN Autosynchronization Disable*/\r
+ UART3_LIN_AUTOSYNC_ENABLE = (uint8_t)0x01 /**< LIN Autosynchronization Enable*/\r
+ } UART3_LinAutosync_TypeDef;\r
+/**\r
+ * @brief UART3 Divider Update Method possible values\r
+ */\r
+typedef enum { UART3_LIN_DIVUP_LBRR1 = (uint8_t)0x00, /**< LIN LDIV is updated as soon as LBRR1 is written*/\r
+ UART3_LIN_DIVUP_NEXTRXNE = (uint8_t)0x01 /**< LIN LDIV is updated at the next received character*/\r
+ } UART3_LinDivUp_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief UART3 Flag possible values\r
+ */\r
+typedef enum\r
+{\r
+ UART3_FLAG_TXE = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */\r
+ UART3_FLAG_TC = (uint16_t)0x0040, /*!< Transmission Complete flag */\r
+ UART3_FLAG_RXNE = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */\r
+ UART3_FLAG_IDLE = (uint16_t)0x0010, /*!< Idle line detected flag */\r
+ UART3_FLAG_OR_LHE = (uint16_t)0x0008, /*!< OverRun error flag */\r
+ UART3_FLAG_NF = (uint16_t)0x0004, /*!< Noise error flag */\r
+ UART3_FLAG_FE = (uint16_t)0x0002, /*!< Framing Error flag */\r
+ UART3_FLAG_PE = (uint16_t)0x0001, /*!< Parity Error flag */\r
+ UART3_FLAG_SBK = (uint16_t)0x0101, /**< Send Break Complete interrupt flag */\r
+ UART3_FLAG_LBDF = (uint16_t)0x0210, /**< LIN Break Detection Flag */\r
+ UART3_FLAG_LHDF = (uint16_t)0x0302, /**< LIN Header Detection Flag*/\r
+ UART3_FLAG_LSF = (uint16_t)0x0301 /**< LIN Sync Field Flag*/\r
+} UART3_Flag_TypeDef;\r
+\r
+/**\r
+ * @brief UART3 Interrupt definition\r
+ * UART3_IT possible values\r
+ * Elements values convention: 0xZYX\r
+ * X: Position of the corresponding Interrupt\r
+ * - For the following values, X means the interrupt position in the CR2 register.\r
+ * UART3_IT_TXE\r
+ * UART3_IT_TC\r
+ * UART3_IT_RXNE\r
+ * UART3_IT_IDLE \r
+ * UART3_IT_OR \r
+ * - For the UART3_IT_PE value, X means the flag position in the CR1 register.\r
+ * - For the UART3_IT_LBDF value, X means the flag position in the CR4 register.\r
+ * - For the UART3_IT_LHDF value, X means the flag position in the CR6 register.\r
+ * Y: Flag position\r
+ * - For the following values, Y means the flag (pending bit) position in the SR register.\r
+ * UART3_IT_TXE\r
+ * UART3_IT_TC\r
+ * UART3_IT_RXNE\r
+ * UART3_IT_IDLE \r
+ * UART3_IT_OR\r
+ * UART3_IT_PE\r
+ * - For the UART3_IT_LBDF value, Y means the flag position in the CR4 register.\r
+ * - For the UART3_IT_LHDF value, Y means the flag position in the CR6 register.\r
+ * Z: Register index: indicate in which register the dedicated interrupt source is:\r
+ * - 1==> CR1 register\r
+ * - 2==> CR2 register\r
+ * - 3==> CR4 register\r
+ * - 4==> CR6 register\r
+ */\r
+typedef enum { UART3_IT_TXE = (uint16_t)0x0277, /**< Transmit interrupt */\r
+ UART3_IT_TC = (uint16_t)0x0266, /**< Transmission Complete interrupt */\r
+ UART3_IT_RXNE = (uint16_t)0x0255, /**< Data Register Not Empty interrupt */\r
+ UART3_IT_IDLE = (uint16_t)0x0244, /**< Idle line detected interrupt */\r
+ UART3_IT_OR = (uint16_t)0x0235, /**< OverRun error interrupt */\r
+ UART3_IT_PE = (uint16_t)0x0100, /**< Parity Error interrupt */\r
+ UART3_IT_LBDF = (uint16_t)0x0346, /**< LIN Break Detection interrupt */\r
+ UART3_IT_LHDF = (uint16_t)0x0412, /**< LIN Header Detection interrupt*/\r
+ UART3_IT_RXNE_OR = (uint16_t)0x0205 /*!< Receive/Overrun interrupt */\r
+ } UART3_IT_TypeDef;\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macros ------------------------------------------------------------*/\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup UART3_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the FLAGs\r
+ */\r
+#define IS_UART3_FLAG_OK(Flag) \\r
+ (((Flag) == UART3_FLAG_TXE) || \\r
+ ((Flag) == UART3_FLAG_TC) || \\r
+ ((Flag) == UART3_FLAG_RXNE) || \\r
+ ((Flag) == UART3_FLAG_IDLE) || \\r
+ ((Flag) == UART3_FLAG_OR_LHE) || \\r
+ ((Flag) == UART3_FLAG_NF) || \\r
+ ((Flag) == UART3_FLAG_FE) || \\r
+ ((Flag) == UART3_FLAG_PE) || \\r
+ ((Flag) == UART3_FLAG_SBK) || \\r
+ ((Flag) == UART3_FLAG_LSF) || \\r
+ ((Flag) == UART3_FLAG_LHDF) || \\r
+ ((Flag) == UART3_FLAG_LBDF))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the FLAGs that can be cleared by writing 0\r
+ */\r
+#define IS_UART3_CLEAR_FLAG_OK(Flag) \\r
+ (((Flag) == UART3_FLAG_RXNE) || \\r
+ ((Flag) == UART3_FLAG_LHDF) || \\r
+ ((Flag) == UART3_FLAG_LSF) || \\r
+ ((Flag) == UART3_FLAG_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the \r
+ * different sensitivity values for the Interrupts\r
+ */\r
+\r
+#define IS_UART3_CONFIG_IT_OK(Interrupt) \\r
+ (((Interrupt) == UART3_IT_PE) || \\r
+ ((Interrupt) == UART3_IT_TXE) || \\r
+ ((Interrupt) == UART3_IT_TC) || \\r
+ ((Interrupt) == UART3_IT_RXNE_OR ) || \\r
+ ((Interrupt) == UART3_IT_IDLE) || \\r
+ ((Interrupt) == UART3_IT_LHDF) || \\r
+ ((Interrupt) == UART3_IT_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit\r
+ */\r
+#define IS_UART3_GET_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART3_IT_TXE) || \\r
+ ((ITPendingBit) == UART3_IT_TC) || \\r
+ ((ITPendingBit) == UART3_IT_RXNE) || \\r
+ ((ITPendingBit) == UART3_IT_IDLE) || \\r
+ ((ITPendingBit) == UART3_IT_OR) || \\r
+ ((ITPendingBit) == UART3_IT_LBDF) || \\r
+ ((ITPendingBit) == UART3_IT_LHDF) || \\r
+ ((ITPendingBit) == UART3_IT_PE))\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different \r
+ * sensitivity values for the pending bit that can be cleared by writing 0\r
+ */\r
+#define IS_UART3_CLEAR_IT_OK(ITPendingBit) \\r
+ (((ITPendingBit) == UART3_IT_RXNE) || \\r
+ ((ITPendingBit) == UART3_IT_LHDF) || \\r
+ ((ITPendingBit) == UART3_IT_LBDF))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the MODEs\r
+ */\r
+#define IS_UART3_MODE_OK(Mode) \\r
+ (((Mode) == (uint8_t)UART3_MODE_RX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART3_MODE_RX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART3_MODE_TX_ENABLE) || \\r
+ ((Mode) == (uint8_t)UART3_MODE_TX_DISABLE) || \\r
+ ((Mode) == (uint8_t)UART3_MODE_TXRX_ENABLE) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_ENABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_ENABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_DISABLE)) || \\r
+ ((Mode) == (uint8_t)((uint8_t)UART3_MODE_TX_DISABLE|(uint8_t)UART3_MODE_RX_ENABLE)))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WordLengths\r
+ */\r
+#define IS_UART3_WORDLENGTH_OK(WordLength) \\r
+ (((WordLength) == UART3_WORDLENGTH_8D) || \\r
+ ((WordLength) == UART3_WORDLENGTH_9D))\r
+\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the WakeUps\r
+ */\r
+#define IS_UART3_WAKEUP_OK(WakeUpMode) \\r
+ (((WakeUpMode) == UART3_WAKEUP_IDLELINE) || \\r
+ ((WakeUpMode) == UART3_WAKEUP_ADDRESSMARK))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the LINBreakDetectionLengths\r
+ */\r
+#define IS_UART3_LINBREAKDETECTIONLENGTH_OK(LINBreakDetectionLengths) \\r
+ (((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_10BITS) || \\r
+ ((LINBreakDetectionLengths) == UART3_LINBREAKDETECTIONLENGTH_11BITS))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the UART3_StopBits\r
+ */\r
+#define IS_UART3_STOPBITS_OK(StopBit) \\r
+ (((StopBit) == UART3_STOPBITS_1) || \\r
+ ((StopBit) == UART3_STOPBITS_2))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the different\r
+ * sensitivity values for the Parity\r
+ */\r
+#define IS_UART3_PARITY_OK(Parity) \\r
+ (((Parity) == UART3_PARITY_NO) || \\r
+ ((Parity) == UART3_PARITY_EVEN) || \\r
+ ((Parity) == UART3_PARITY_ODD ))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the maximum \r
+ * baudrate value\r
+ */\r
+#define IS_UART3_BAUDRATE_OK(NUM) ((NUM) <= (uint32_t)625000)\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the address \r
+ * of the UART3 or UART node\r
+ */\r
+#define UART3_ADDRESS_MAX ((uint8_t)16)\r
+#define IS_UART3_ADDRESS_OK(Node) ((Node) < UART3_ADDRESS_MAX)\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN mode\r
+ */\r
+#define IS_UART3_SLAVE_OK(Mode) \\r
+ (((Mode) == UART3_LIN_MODE_MASTER) || \\r
+ ((Mode) == UART3_LIN_MODE_SLAVE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN \r
+ * automatic resynchronization mode\r
+ */\r
+#define IS_UART3_AUTOSYNC_OK(AutosyncMode) \\r
+ (((AutosyncMode) == UART3_LIN_AUTOSYNC_ENABLE) || \\r
+ ((AutosyncMode) == UART3_LIN_AUTOSYNC_DISABLE))\r
+\r
+/**\r
+ * @brief Macro used by the assert_param function in order to check the LIN \r
+ * divider update method\r
+ */\r
+#define IS_UART3_DIVUP_OK(DivupMethode) \\r
+ (((DivupMethode) == UART3_LIN_DIVUP_LBRR1) || \\r
+ ((DivupMethode) == UART3_LIN_DIVUP_NEXTRXNE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup UART3_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void UART3_DeInit(void);\r
+void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, \r
+ UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, \r
+ UART3_Mode_TypeDef Mode);\r
+void UART3_Cmd(FunctionalState NewState);\r
+void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState);\r
+void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength);\r
+void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode, \r
+ UART3_LinAutosync_TypeDef UART3_Autosync, \r
+ UART3_LinDivUp_TypeDef UART3_DivUp);\r
+void UART3_LINCmd(FunctionalState NewState);\r
+void UART3_ReceiverWakeUpCmd(FunctionalState NewState);\r
+void UART3_WakeUpConfig( UART3_WakeUp_TypeDef UART3_WakeUp);\r
+uint8_t UART3_ReceiveData8(void);\r
+uint16_t UART3_ReceiveData9(void);\r
+void UART3_SendData8(uint8_t Data);\r
+void UART3_SendData9(uint16_t Data);\r
+void UART3_SendBreak(void);\r
+void UART3_SetAddress(uint8_t UART3_Address);\r
+FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG);\r
+void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG);\r
+ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT);\r
+void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_UART3_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all functions prototype and macros for the WWDG peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_WWDG_H\r
+#define __STM8S_WWDG_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/* Private macros ------------------------------------------------------------*/\r
+\r
+/** @addtogroup WWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the\r
+ * values of the window register.\r
+ */\r
+#define IS_WWDG_WINDOWLIMITVALUE_OK(WindowLimitValue) ((WindowLimitValue) <= 0x7F)\r
+\r
+/**\r
+ * @brief Macro used by the assert function in order to check the different\r
+ * values of the counter register.\r
+ */\r
+#define IS_WWDG_COUNTERVALUE_OK(CounterValue) ((CounterValue) <= 0x7F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+/** @addtogroup WWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void WWDG_Init(uint8_t Counter, uint8_t WindowValue);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+uint8_t WWDG_GetCounter(void);\r
+void WWDG_SWReset(void);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* __STM8S_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_adc1.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions/macros for the ADC1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_adc1.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup ADC1_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ADC1 peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC1_DeInit(void)\r
+{\r
+ ADC1->CSR = ADC1_CSR_RESET_VALUE;\r
+ ADC1->CR1 = ADC1_CR1_RESET_VALUE;\r
+ ADC1->CR2 = ADC1_CR2_RESET_VALUE;\r
+ ADC1->CR3 = ADC1_CR3_RESET_VALUE;\r
+ ADC1->TDRH = ADC1_TDRH_RESET_VALUE;\r
+ ADC1->TDRL = ADC1_TDRL_RESET_VALUE;\r
+ ADC1->HTRH = ADC1_HTRH_RESET_VALUE;\r
+ ADC1->HTRL = ADC1_HTRL_RESET_VALUE;\r
+ ADC1->LTRH = ADC1_LTRH_RESET_VALUE;\r
+ ADC1->LTRL = ADC1_LTRL_RESET_VALUE;\r
+ ADC1->AWCRH = ADC1_AWCRH_RESET_VALUE;\r
+ ADC1->AWCRL = ADC1_AWCRL_RESET_VALUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the ADC1 peripheral according to the specified parameters\r
+ * @param ADC1_ConversionMode: specifies the conversion mode\r
+ * can be one of the values of @ref ADC1_ConvMode_TypeDef.\r
+ * @param ADC1_Channel: specifies the channel to convert\r
+ * can be one of the values of @ref ADC1_Channel_TypeDef.\r
+ * @param ADC1_PrescalerSelection: specifies the ADC1 prescaler\r
+ * can be one of the values of @ref ADC1_PresSel_TypeDef.\r
+ * @param ADC1_ExtTrigger: specifies the external trigger\r
+ * can be one of the values of @ref ADC1_ExtTrig_TypeDef.\r
+ * @param ADC1_ExtTriggerState: specifies the external trigger new state\r
+ * can be one of the values of @ref FunctionalState.\r
+ * @param ADC1_Align: specifies the converted data alignment\r
+ * can be one of the values of @ref ADC1_Align_TypeDef.\r
+ * @param ADC1_SchmittTriggerChannel: specifies the schmitt trigger channel\r
+ * can be one of the values of @ref ADC1_SchmittTrigg_TypeDef.\r
+ * @param ADC1_SchmittTriggerState: specifies the schmitt trigger state\r
+ * can be one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_PresSel_TypeDef ADC1_PrescalerSelection, ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState ADC1_SchmittTriggerState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));\r
+ assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));\r
+ assert_param(IS_ADC1_PRESSEL_OK(ADC1_PrescalerSelection));\r
+ assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(((ADC1_ExtTriggerState))));\r
+ assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));\r
+ assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(ADC1_SchmittTriggerState));\r
+\r
+ /*-----------------CR1 & CSR configuration --------------------*/\r
+ /* Configure the conversion mode and the channel to convert\r
+ respectively according to ADC1_ConversionMode & ADC1_Channel values & ADC1_Align values */\r
+ ADC1_ConversionConfig(ADC1_ConversionMode, ADC1_Channel, ADC1_Align);\r
+ /* Select the prescaler division factor according to ADC1_PrescalerSelection values */\r
+ ADC1_PrescalerConfig(ADC1_PrescalerSelection);\r
+\r
+ /*-----------------CR2 configuration --------------------*/\r
+ /* Configure the external trigger state and event respectively\r
+ according to NewState, ADC1_ExtTrigger */\r
+ ADC1_ExternalTriggerConfig(ADC1_ExtTrigger, ADC1_ExtTriggerState);\r
+\r
+ /*------------------TDR configuration ---------------------------*/\r
+ /* Configure the schmitt trigger channel and state respectively\r
+ according to ADC1_SchmittTriggerChannel & ADC1_SchmittTriggerNewState values */\r
+ ADC1_SchmittTriggerConfig(ADC1_SchmittTriggerChannel, ADC1_SchmittTriggerState);\r
+\r
+ /* Enable the ADC1 peripheral */\r
+ ADC1->CR1 |= ADC1_CR1_ADON;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the ADC1 peripheral.\r
+ * @param NewState: specifies the peripheral enabled or disabled state.\r
+ * @retval None\r
+ */\r
+void ADC1_Cmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->CR1 |= ADC1_CR1_ADON;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->CR1 &= (uint8_t)(~ADC1_CR1_ADON);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the ADC1 scan mode.\r
+ * @param NewState: specifies the selected mode enabled or disabled state.\r
+ * @retval None\r
+ */\r
+void ADC1_ScanModeCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->CR2 |= ADC1_CR2_SCAN;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->CR2 &= (uint8_t)(~ADC1_CR2_SCAN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the ADC1 data store into the Data Buffer registers rather than in the Data Register\r
+ * @param NewState: specifies the selected mode enabled or disabled state.\r
+ * @retval None\r
+ */\r
+void ADC1_DataBufferCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->CR3 |= ADC1_CR3_DBUF;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->CR3 &= (uint8_t)(~ADC1_CR3_DBUF);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC1 interrupt.\r
+ * @param ADC1_IT specifies the name of the interrupt to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * - ADC1_IT_AWDITEN : Analog WDG interrupt enable\r
+ * - ADC1_IT_EOCITEN : EOC iterrupt enable\r
+ * @param NewState specifies the state of the interrupt to apply.\r
+ * @retval None\r
+ */\r
+void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_IT_OK(ADC1_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC1 interrupts */\r
+ ADC1->CSR |= (uint8_t)ADC1_IT;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the ADC1 interrupts */\r
+ ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ADC1_IT);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the ADC1 prescaler division factor.\r
+ * @param ADC1_Prescaler: the selected precaler.\r
+ * It can be one of the values of @ref ADC1_PresSel_TypeDef.\r
+ * @retval None\r
+ */\r
+void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler)\r
+{\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_ADC1_PRESSEL_OK(ADC1_Prescaler));\r
+\r
+ /* Clear the SPSEL bits */\r
+ ADC1->CR1 &= (uint8_t)(~ADC1_CR1_SPSEL);\r
+ /* Select the prescaler division factor according to ADC1_PrescalerSelection values */\r
+ ADC1->CR1 |= (uint8_t)(ADC1_Prescaler);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC1 Schmitt Trigger on a selected channel.\r
+ * @param ADC1_SchmittTriggerChannel specifies the desired Channel.\r
+ * It can be set of the values of @ref ADC1_SchmittTrigg_TypeDef.\r
+ * @param NewState specifies Channel new status.\r
+ * can have one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_SCHMITTTRIG_OK(ADC1_SchmittTriggerChannel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (ADC1_SchmittTriggerChannel == ADC1_SCHMITTTRIG_ALL)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->TDRL &= (uint8_t)0x0;\r
+ ADC1->TDRH &= (uint8_t)0x0;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->TDRL |= (uint8_t)0xFF;\r
+ ADC1->TDRH |= (uint8_t)0xFF;\r
+ }\r
+ }\r
+ else if (ADC1_SchmittTriggerChannel < ADC1_SCHMITTTRIG_CHANNEL8)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel));\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC1_SchmittTriggerChannel);\r
+ }\r
+ }\r
+ else /* ADC1_SchmittTriggerChannel >= ADC1_SCHMITTTRIG_CHANNEL8 */\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8)));\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC1_SchmittTriggerChannel - (uint8_t)8));\r
+ }\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the ADC1 conversion on selected channel.\r
+ * @param ADC1_ConversionMode Specifies the conversion type.\r
+ * It can be set of the values of @ref ADC1_ConvMode_TypeDef\r
+ * @param ADC1_Channel specifies the ADC1 Channel.\r
+ * It can be set of the values of @ref ADC1_Channel_TypeDef\r
+ * @param ADC1_Align specifies the conerted data alignment.\r
+ * It can be set of the values of @ref ADC1_Align_TypeDef\r
+ * @retval None\r
+ */\r
+void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode, ADC1_Channel_TypeDef ADC1_Channel, ADC1_Align_TypeDef ADC1_Align)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_CONVERSIONMODE_OK(ADC1_ConversionMode));\r
+ assert_param(IS_ADC1_CHANNEL_OK(ADC1_Channel));\r
+ assert_param(IS_ADC1_ALIGN_OK(ADC1_Align));\r
+\r
+ /* Clear the align bit */\r
+ ADC1->CR2 &= (uint8_t)(~ADC1_CR2_ALIGN);\r
+ /* Configure the data alignment */\r
+ ADC1->CR2 |= (uint8_t)(ADC1_Align);\r
+\r
+ if (ADC1_ConversionMode == ADC1_CONVERSIONMODE_CONTINUOUS)\r
+ {\r
+ /* Set the continuous coversion mode */\r
+ ADC1->CR1 |= ADC1_CR1_CONT;\r
+ }\r
+ else /* ADC1_ConversionMode == ADC1_CONVERSIONMODE_SINGLE */\r
+ {\r
+ /* Set the single conversion mode */\r
+ ADC1->CR1 &= (uint8_t)(~ADC1_CR1_CONT);\r
+ }\r
+\r
+ /* Clear the ADC1 channels */\r
+ ADC1->CSR &= (uint8_t)(~ADC1_CSR_CH);\r
+ /* Select the ADC1 channel */\r
+ ADC1->CSR |= (uint8_t)(ADC1_Channel);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the ADC1 conversion on external trigger event.\r
+ * @par Full description:\r
+ * The selected external trigger evant can be enabled or disabled.\r
+ * @param ADC1_ExtTrigger to select the External trigger event.\r
+ * can have one of the values of @ref ADC1_ExtTrig_TypeDef.\r
+ * @param NewState to enable/disable the selected external trigger\r
+ * can have one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Clear the external trigger selection bits */\r
+ ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTSEL);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected external Trigger */\r
+ ADC1->CR2 |= (uint8_t)(ADC1_CR2_EXTTRIG);\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the selected external trigger */\r
+ ADC1->CR2 &= (uint8_t)(~ADC1_CR2_EXTTRIG);\r
+ }\r
+\r
+ /* Set the selected external trigger */\r
+ ADC1->CR2 |= (uint8_t)(ADC1_ExtTrigger);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start ADC1 conversion\r
+ * @par Full description:\r
+ * This function triggers the start of conversion, after ADC1 configuration.\r
+ * @param None\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Enable the ADC1 peripheral before calling this function\r
+ */\r
+void ADC1_StartConversion(void)\r
+{\r
+ ADC1->CR1 |= ADC1_CR1_ADON;\r
+}\r
+\r
+/**\r
+ * @brief Get one sample of measured signal.\r
+ * @param None\r
+ * @retval ConversionValue: value of the measured signal.\r
+ * @par Required preconditions:\r
+ * ADC1 conversion finished.\r
+ */\r
+uint16_t ADC1_GetConversionValue(void)\r
+{\r
+\r
+ uint16_t temph = 0;\r
+ uint8_t templ = 0;\r
+\r
+ if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */\r
+ {\r
+ /* Read LSB first */\r
+ templ = ADC1->DRL;\r
+ /* Then read MSB */\r
+ temph = ADC1->DRH;\r
+\r
+ temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));\r
+ }\r
+ else /* Left alignment */\r
+ {\r
+ /* Read MSB firts*/\r
+ temph = ADC1->DRH;\r
+ /* Then read LSB */\r
+ templ = ADC1->DRL;\r
+\r
+ temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));\r
+ }\r
+\r
+ return ((uint16_t)temph);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the analog watchdog for the given channel.\r
+ * @param Channel specifies the desired Channel.\r
+ * It can be set of the values of @ref ADC1_Channel_TypeDef.\r
+ * @param NewState specifies the analog watchdog new state.\r
+ * can have one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+ assert_param(IS_ADC1_CHANNEL_OK(Channel));\r
+\r
+ if (Channel < (uint8_t)8)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->AWCRL |= (uint8_t)((uint8_t)1 << Channel);\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->AWCRL &= (uint8_t)~(uint8_t)((uint8_t)1 << Channel);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC1->AWCRH |= (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8));\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC1->AWCRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (uint8_t)(Channel - (uint8_t)8));\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the high threshold of the analog watchdog.\r
+ * @param Threshold specifies the high threshold value.\r
+ * this value depends on the reference voltage range.\r
+ * @retval None\r
+ */\r
+void ADC1_SetHighThreshold(uint16_t Threshold)\r
+{\r
+ ADC1->HTRH = (uint8_t)(Threshold >> (uint8_t)2);\r
+ ADC1->HTRL = (uint8_t)Threshold;\r
+}\r
+\r
+/**\r
+ * @brief Sets the low threshold of the analog watchdog.\r
+ * @param Threshold specifies the low threshold value.\r
+ * this value depends on the reference voltage range.\r
+ * @retval None\r
+ */\r
+void ADC1_SetLowThreshold(uint16_t Threshold)\r
+{\r
+ ADC1->LTRL = (uint8_t)Threshold;\r
+ ADC1->LTRH = (uint8_t)(Threshold >> (uint8_t)2);\r
+}\r
+\r
+/**\r
+ * @brief Get one sample of measured signal.\r
+ * @param Buffer specifies the buffer to read.\r
+ * @retval BufferValue: value read from the given buffer.\r
+ * @par Required preconditions:\r
+ * ADC1 conversion finished.\r
+ */\r
+uint16_t ADC1_GetBufferValue(uint8_t Buffer)\r
+{\r
+\r
+ uint16_t temph = 0;\r
+ uint8_t templ = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_BUFFER_OK(Buffer));\r
+\r
+ if ((ADC1->CR2 & ADC1_CR2_ALIGN) != 0) /* Right alignment */\r
+ {\r
+ /* Read LSB first */\r
+ templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);\r
+ /* Then read MSB */\r
+ temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));\r
+\r
+ temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));\r
+ }\r
+ else /* Left alignment */\r
+ {\r
+ /* Read MSB firts*/\r
+ temph = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1));\r
+ /* Then read LSB */\r
+ templ = *(uint8_t*)(uint16_t)((uint16_t)ADC1_BaseAddress + (uint8_t)(Buffer << 1) + 1);\r
+\r
+ temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)(temph << 8));\r
+ }\r
+\r
+ return ((uint16_t)temph);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Checks the specified analog watchdog channel status.\r
+ * @param Channel: specify the channel of which to check the analog watchdog\r
+ * can be one of the values of @ref ADC1_Channel_TypeDef.\r
+ * @retval FlagStatus Status of the analog watchdog.\r
+ */\r
+FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)\r
+{\r
+ uint8_t status = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_CHANNEL_OK(Channel));\r
+\r
+ if (Channel < (uint8_t)8)\r
+ {\r
+ status = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << Channel));\r
+ }\r
+ else /* Channel = 8 | 9 */\r
+ {\r
+ status = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (Channel - (uint8_t)8)));\r
+ }\r
+\r
+ return ((FlagStatus)status);\r
+}\r
+\r
+/**\r
+ * @brief Checks the specified ADC1 flag status.\r
+ * @param Flag: ADC1 flag.\r
+ * can be one of the values of @ref ADC1_Flag_TypeDef.\r
+ * @retval FlagStatus Status of the ADC1 flag.\r
+ */\r
+FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)\r
+{\r
+ uint8_t flagstatus = 0;\r
+ uint8_t temp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_FLAG_OK(Flag));\r
+\r
+ if ((Flag & 0x0F) == 0x01)\r
+ {\r
+ /* Get OVR flag status */\r
+ flagstatus = (uint8_t)(ADC1->CR3 & ADC1_CR3_OVR);\r
+ }\r
+ else if ((Flag & 0xF0) == 0x10)\r
+ {\r
+ /* Get analog watchdog channel status */\r
+ temp = (uint8_t)(Flag & (uint8_t)0x0F);\r
+ if (temp < 8)\r
+ {\r
+ flagstatus = (uint8_t)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));\r
+ }\r
+ else\r
+ {\r
+ flagstatus = (uint8_t)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));\r
+ }\r
+ }\r
+ else /* Get EOC | AWD flag status */\r
+ {\r
+ flagstatus = (uint8_t)(ADC1->CSR & Flag);\r
+ }\r
+ return ((FlagStatus)flagstatus);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Clear the specified ADC1 Flag.\r
+ * @param Flag: ADC1 flag.\r
+ * can be one of the values of @ref ADC1_Flag_TypeDef.\r
+ * @retval None\r
+ */\r
+void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)\r
+{\r
+ uint8_t temp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_FLAG_OK(Flag));\r
+\r
+ if ((Flag & 0x0F) == 0x01)\r
+ {\r
+ /* Clear OVR flag status */\r
+ ADC1->CR3 &= (uint8_t)(~ADC1_CR3_OVR);\r
+ }\r
+ else if ((Flag & 0xF0) == 0x10)\r
+ {\r
+ /* Clear analog watchdog channel status */\r
+ temp = (uint8_t)(Flag & (uint8_t)0x0F);\r
+ if (temp < 8)\r
+ {\r
+ ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);\r
+ }\r
+ else\r
+ {\r
+ ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));\r
+ }\r
+ }\r
+ else /* Clear EOC | AWD flag status */\r
+ {\r
+ ADC1->CSR &= (uint8_t) (~Flag);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified pending bit status\r
+ * @param ITPendingBit : the IT pending bit to check.\r
+ * This parameter can be one of the following values:\r
+ * - ADC1_IT_AWD : Analog WDG IT status\r
+ * - ADC1_IT_AWS0 : Analog channel 0 IT status\r
+ * - ADC1_IT_AWS1 : Analog channel 1 IT status\r
+ * - ADC1_IT_AWS2 : Analog channel 2 IT status\r
+ * - ADC1_IT_AWS3 : Analog channel 3 IT status\r
+ * - ADC1_IT_AWS4 : Analog channel 4 IT status\r
+ * - ADC1_IT_AWS5 : Analog channel 5 IT status\r
+ * - ADC1_IT_AWS6 : Analog channel 6 IT status\r
+ * - ADC1_IT_AWS7 : Analog channel 7 IT status\r
+ * - ADC1_IT_AWS8 : Analog channel 8 IT status\r
+ * - ADC1_IT_AWS9 : Analog channel 9 IT status\r
+ * - ADC1_IT_EOC : EOC pending bit\r
+ * @retval ITStatus: status of the specified pending bit.\r
+ */\r
+ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)\r
+{\r
+ ITStatus itstatus = RESET;\r
+ uint8_t temp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));\r
+\r
+ if (((uint16_t)ITPendingBit & 0xF0) == 0x10)\r
+ {\r
+ /* Get analog watchdog channel status */\r
+ temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);\r
+ if (temp < 8)\r
+ {\r
+ itstatus = (ITStatus)(ADC1->AWSRL & (uint8_t)((uint8_t)1 << temp));\r
+ }\r
+ else\r
+ {\r
+ itstatus = (ITStatus)(ADC1->AWSRH & (uint8_t)((uint8_t)1 << (temp - 8)));\r
+ }\r
+ }\r
+ else /* Get EOC | AWD flag status */\r
+ {\r
+ itstatus = (ITStatus)(ADC1->CSR & (uint8_t)ITPendingBit);\r
+ }\r
+ return ((ITStatus)itstatus);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Clear the ADC1 End of Conversion pending bit.\r
+ * @param ITPendingBit : the IT pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - ADC1_IT_AWD : Analog WDG IT status\r
+ * - ADC1_IT_AWS0 : Analog channel 0 IT status\r
+ * - ADC1_IT_AWS1 : Analog channel 1 IT status\r
+ * - ADC1_IT_AWS2 : Analog channel 2 IT status\r
+ * - ADC1_IT_AWS3 : Analog channel 3 IT status\r
+ * - ADC1_IT_AWS4 : Analog channel 4 IT status\r
+ * - ADC1_IT_AWS5 : Analog channel 5 IT status\r
+ * - ADC1_IT_AWS6 : Analog channel 6 IT status\r
+ * - ADC1_IT_AWS7 : Analog channel 7 IT status\r
+ * - ADC1_IT_AWS8 : Analog channel 8 IT status\r
+ * - ADC1_IT_AWS9 : Analog channel 9 IT status\r
+ * - ADC1_IT_EOC : EOC pending bit\r
+ * @retval None\r
+ */\r
+void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)\r
+{\r
+ uint8_t temp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));\r
+\r
+ if (((uint16_t)ITPendingBit & 0xF0) == 0x10)\r
+ {\r
+ /* Clear analog watchdog channel status */\r
+ temp = (uint8_t)((uint16_t)ITPendingBit & 0x0F);\r
+ if (temp < 8)\r
+ {\r
+ ADC1->AWSRL &= (uint8_t)~(uint8_t)((uint8_t)1 << temp);\r
+ }\r
+ else\r
+ {\r
+ ADC1->AWSRH &= (uint8_t)~(uint8_t)((uint8_t)1 << (temp - 8));\r
+ }\r
+ }\r
+ else /* Clear EOC | AWD flag status */\r
+ {\r
+ ADC1->CSR &= (uint8_t)((uint16_t)~(uint16_t)ITPendingBit);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_adc2.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions/macros for the ADC2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_adc2.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup ADC2_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ADC2 peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC2_DeInit(void)\r
+{\r
+ ADC2->CSR = ADC2_CSR_RESET_VALUE;\r
+ ADC2->CR1 = ADC2_CR1_RESET_VALUE;\r
+ ADC2->CR2 = ADC2_CR2_RESET_VALUE;\r
+ ADC2->TDRH = ADC2_TDRH_RESET_VALUE;\r
+ ADC2->TDRL = ADC2_TDRL_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADC2 peripheral according to the specified parameters\r
+ * @param ADC2_ConversionMode: specifies the conversion mode\r
+ * can be one of the values of @ref ADC2_ConvMode_TypeDef.\r
+ * @param ADC2_Channel: specifies the channel to convert\r
+ * can be one of the values of @ref ADC2_Channel_TypeDef.\r
+ * @param ADC2_PrescalerSelection: specifies the ADC2 prescaler\r
+ * can be one of the values of @ref ADC2_PresSel_TypeDef.\r
+ * @param ADC2_ExtTrigger: specifies the external trigger\r
+ * can be one of the values of @ref ADC2_ExtTrig_TypeDef.\r
+ * @param ADC2_ExtTriggerState: specifies the external trigger new state\r
+ * can be one of the values of @ref FunctionalState.\r
+ * @param ADC2_Align: specifies the converted data alignment\r
+ * can be one of the values of @ref ADC2_Align_TypeDef.\r
+ * @param ADC2_SchmittTriggerChannel: specifies the schmitt trigger channel\r
+ * can be one of the values of @ref ADC2_SchmittTrigg_TypeDef.\r
+ * @param ADC2_SchmittTriggerState: specifies the schmitt trigger state\r
+ * can be one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC2_Init(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_PresSel_TypeDef ADC2_PrescalerSelection, ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState ADC2_ExtTriggerState, ADC2_Align_TypeDef ADC2_Align, ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState ADC2_SchmittTriggerState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));\r
+ assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));\r
+ assert_param(IS_ADC2_PRESSEL_OK(ADC2_PrescalerSelection));\r
+ assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(((ADC2_ExtTriggerState))));\r
+ assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));\r
+ assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(ADC2_SchmittTriggerState));\r
+\r
+ /*-----------------CR1 & CSR configuration --------------------*/\r
+ /* Configure the conversion mode and the channel to convert\r
+ respectively according to ADC2_ConversionMode & ADC2_Channel values & ADC2_Align values */\r
+ ADC2_ConversionConfig(ADC2_ConversionMode, ADC2_Channel, ADC2_Align);\r
+ /* Select the prescaler division factor according to ADC2_PrescalerSelection values */\r
+ ADC2_PrescalerConfig(ADC2_PrescalerSelection);\r
+\r
+ /*-----------------CR2 configuration --------------------*/\r
+ /* Configure the external trigger state and event respectively\r
+ according to ADC2_ExtTrigStatus, ADC2_ExtTrigger */\r
+ ADC2_ExternalTriggerConfig(ADC2_ExtTrigger, ADC2_ExtTriggerState);\r
+\r
+ /*------------------TDR configuration ---------------------------*/\r
+ /* Configure the schmitt trigger channel and state respectively\r
+ according to ADC2_SchmittTriggerChannel & ADC2_SchmittTriggerNewState values */\r
+ ADC2_SchmittTriggerConfig(ADC2_SchmittTriggerChannel, ADC2_SchmittTriggerState);\r
+\r
+ /* Enable the ADC2 peripheral */\r
+ ADC2->CR1 |= ADC2_CR1_ADON;\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the ADC2 peripheral.\r
+ * @param NewState: specifies the peripheral enabled or disabled state.\r
+ * @retval None\r
+ */\r
+void ADC2_Cmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC2->CR1 |= ADC2_CR1_ADON;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC2->CR1 &= (uint8_t)(~ADC2_CR1_ADON);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADC2 interrupt.\r
+ * @param NewState specifies the state of ADC2 interrupt.\r
+ * @retval None\r
+ */\r
+void ADC2_ITConfig(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the ADC2 interrupts */\r
+ ADC2->CSR |= (uint8_t)ADC2_CSR_EOCIE;\r
+ }\r
+ else /*NewState == DISABLE */\r
+ {\r
+ /* Disable the ADC2 interrupts */\r
+ ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOCIE);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the ADC2 prescaler division factor.\r
+ * @param ADC2_Prescaler: the selected prescaler.\r
+ * It can be one of the values of @ref ADC2_PresSel_TypeDef.\r
+ * @retval None\r
+ */\r
+void ADC2_PrescalerConfig(ADC2_PresSel_TypeDef ADC2_Prescaler)\r
+{\r
+\r
+ /* Check the parameter */\r
+ assert_param(IS_ADC2_PRESSEL_OK(ADC2_Prescaler));\r
+\r
+ /* Clear the SPSEL bits */\r
+ ADC2->CR1 &= (uint8_t)(~ADC2_CR1_SPSEL);\r
+ /* Select the prescaler division factor according to ADC2_PrescalerSelection values */\r
+ ADC2->CR1 |= (uint8_t)(ADC2_Prescaler);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the ADC2 Schmitt Trigger on a selected channel.\r
+ * @param ADC2_SchmittTriggerChannel specifies the desired Channel.\r
+ * It can be set of the values of @ref ADC2_SchmittTrigg_TypeDef.\r
+ * @param NewState specifies the Channel ADC2 Schmitt Trigger new status.\r
+ * can have one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC2_SchmittTriggerConfig(ADC2_SchmittTrigg_TypeDef ADC2_SchmittTriggerChannel, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC2_SCHMITTTRIG_OK(ADC2_SchmittTriggerChannel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (ADC2_SchmittTriggerChannel == ADC2_SCHMITTTRIG_ALL)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC2->TDRL &= (uint8_t)0x0;\r
+ ADC2->TDRH &= (uint8_t)0x0;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC2->TDRL |= (uint8_t)0xFF;\r
+ ADC2->TDRH |= (uint8_t)0xFF;\r
+ }\r
+ }\r
+ else if (ADC2_SchmittTriggerChannel < ADC2_SCHMITTTRIG_CHANNEL8)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC2->TDRL &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel));\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC2->TDRL |= (uint8_t)((uint8_t)0x01 << (uint8_t)ADC2_SchmittTriggerChannel);\r
+ }\r
+ }\r
+ else /* ADC2_SchmittTriggerChannel >= ADC2_SCHMITTTRIG_CHANNEL8 */\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ ADC2->TDRH &= (uint8_t)(~(uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8)));\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ ADC2->TDRH |= (uint8_t)((uint8_t)0x01 << ((uint8_t)ADC2_SchmittTriggerChannel - (uint8_t)8));\r
+ }\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the ADC2 conversion on selected channel.\r
+ * @param ADC2_ConversionMode Specifies the conversion type.\r
+ * It can be set of the values of @ref ADC2_ConvMode_TypeDef\r
+ * @param ADC2_Channel specifies the ADC2 Channel.\r
+ * It can be set of the values of @ref ADC2_Channel_TypeDef\r
+ * @param ADC2_Align specifies the converted data alignment.\r
+ * It can be set of the values of @ref ADC2_Align_TypeDef\r
+ * @retval None\r
+ */\r
+void ADC2_ConversionConfig(ADC2_ConvMode_TypeDef ADC2_ConversionMode, ADC2_Channel_TypeDef ADC2_Channel, ADC2_Align_TypeDef ADC2_Align)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC2_CONVERSIONMODE_OK(ADC2_ConversionMode));\r
+ assert_param(IS_ADC2_CHANNEL_OK(ADC2_Channel));\r
+ assert_param(IS_ADC2_ALIGN_OK(ADC2_Align));\r
+\r
+ /* Clear the align bit */\r
+ ADC2->CR2 &= (uint8_t)(~ADC2_CR2_ALIGN);\r
+ /* Configure the data alignment */\r
+ ADC2->CR2 |= (uint8_t)(ADC2_Align);\r
+\r
+ if (ADC2_ConversionMode == ADC2_CONVERSIONMODE_CONTINUOUS)\r
+ {\r
+ /* Set the continuous conversion mode */\r
+ ADC2->CR1 |= ADC2_CR1_CONT;\r
+ }\r
+ else /* ADC2_ConversionMode == ADC2_CONVERSIONMODE_SINGLE */\r
+ {\r
+ /* Set the single conversion mode */\r
+ ADC2->CR1 &= (uint8_t)(~ADC2_CR1_CONT);\r
+ }\r
+\r
+ /* Clear the ADC2 channels */\r
+ ADC2->CSR &= (uint8_t)(~ADC2_CSR_CH);\r
+ /* Select the ADC2 channel */\r
+ ADC2->CSR |= (uint8_t)(ADC2_Channel);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the ADC2 conversion on external trigger event.\r
+ * @par Full description:\r
+ * The selected external trigger event can be enabled or disabled.\r
+ * @param ADC2_ExtTrigger to select the External trigger event.\r
+ * can have one of the values of @ref ADC2_ExtTrig_TypeDef.\r
+ * @param NewState to enable/disable the selected external trigger\r
+ * can have one of the values of @ref FunctionalState.\r
+ * @retval None\r
+ */\r
+void ADC2_ExternalTriggerConfig(ADC2_ExtTrig_TypeDef ADC2_ExtTrigger, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC2_EXTTRIG_OK(ADC2_ExtTrigger));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Clear the external trigger selection bits */\r
+ ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTSEL);\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected external Trigger */\r
+ ADC2->CR2 |= (uint8_t)(ADC2_CR2_EXTTRIG);\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the selected external trigger */\r
+ ADC2->CR2 &= (uint8_t)(~ADC2_CR2_EXTTRIG);\r
+ }\r
+\r
+ /* Set the slected external trigger */\r
+ ADC2->CR2 |= (uint8_t)(ADC2_ExtTrigger);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Start ADC2 conversion\r
+ * @par Full description:\r
+ * This function triggers the start of conversion, after ADC2 configuration.\r
+ * @param None\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Enable the ADC2 peripheral before calling this function\r
+ */\r
+void ADC2_StartConversion(void)\r
+{\r
+ ADC2->CR1 |= ADC2_CR1_ADON;\r
+}\r
+\r
+/**\r
+ * @brief Get one sample of measured signal.\r
+ * @param None\r
+ * @retval ConversionValue: value of the measured signal.\r
+ * @par Required preconditions:\r
+ * ADC2 conversion finished.\r
+ */\r
+uint16_t ADC2_GetConversionValue(void)\r
+{\r
+\r
+ uint16_t temph = 0;\r
+ uint8_t templ = 0;\r
+\r
+ if ((ADC2->CR2 & ADC2_CR2_ALIGN) != 0) /* Right alignment */\r
+ {\r
+ /* Read LSB first */\r
+ templ = ADC2->DRL;\r
+ /* Then read MSB */\r
+ temph = ADC2->DRH;\r
+\r
+ temph = (uint16_t)(templ | (uint16_t)(temph << (uint8_t)8));\r
+ }\r
+ else /* Left alignment */\r
+ {\r
+ /* Read MSB firts*/\r
+ temph = ADC2->DRH;\r
+ /* Then read LSB */\r
+ templ = ADC2->DRL;\r
+\r
+ temph = (uint16_t)((uint16_t)((uint16_t)templ << 6) | (uint16_t)((uint16_t)temph << 8));\r
+ }\r
+\r
+ return ((uint16_t)temph);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Checks the ADC2 EOC flag status.\r
+ * @param None\r
+ * @retval FlagStatus Status of the ADC2 EOC flag.\r
+ */\r
+FlagStatus ADC2_GetFlagStatus(void)\r
+{\r
+ /* Get EOC flag status */\r
+ return (FlagStatus)(ADC2->CSR & ADC2_CSR_EOC);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Clear the ADC2 EOC Flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC2_ClearFlag(void)\r
+{\r
+ ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);\r
+}\r
+\r
+/**\r
+ * @brief Returns the EOC pending bit status\r
+ * @par Parameters:\r
+ * None\r
+ * @retval FlagStatus: status of the EOC pending bit.\r
+ */\r
+ITStatus ADC2_GetITStatus(void)\r
+{\r
+ return (ITStatus)(ADC2->CSR & ADC2_CSR_EOC);\r
+}\r
+\r
+/**\r
+ * @brief Clear the ADC2 End of Conversion pending bit.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ADC2_ClearITPendingBit(void)\r
+{\r
+ ADC2->CSR &= (uint8_t)(~ADC2_CSR_EOC);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_awu.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the AWU peripheral. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_awu.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* See also AWU_Timebase_TypeDef structure in stm8s_awu.h file :\r
+ N 2 5 1 2 4 8 1 3 6 1 2 5 1 2 1 3\r
+ O 5 0 m m m m 6 2 4 2 5 1 s s 2 0\r
+ I 0 0 s s s s m m m 8 6 2 s s\r
+ T u u s s s m m m\r
+ s s s s s\r
+*/\r
+/** Contains the different values to write in the APR register (used by AWU_Init function) */\r
+CONST uint8_t APR_Array[17] =\r
+ {\r
+ 0, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 61, 23, 23, 62\r
+ };\r
+\r
+/** Contains the different values to write in the TBR register (used by AWU_Init function) */\r
+CONST uint8_t TBR_Array[17] =\r
+ {\r
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 12, 14, 15, 15\r
+ };\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup AWU_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the AWU peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void AWU_DeInit(void)\r
+{\r
+ AWU->CSR = AWU_CSR_RESET_VALUE;\r
+ AWU->APR = AWU_APR_RESET_VALUE;\r
+ AWU->TBR = AWU_TBR_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the AWU peripheral according to the specified parameters.\r
+ * @param AWU_TimeBase : Time base selection (interval between AWU interrupts).\r
+ * can be one of the values of @ref AWU_Timebase_TypeDef.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * The LS RC calibration must be performed before calling this function.\r
+ */\r
+void AWU_Init(AWU_Timebase_TypeDef AWU_TimeBase)\r
+{\r
+\r
+ /* Check parameter */\r
+ assert_param(IS_AWU_TIMEBASE_OK(AWU_TimeBase));\r
+\r
+ /* Enable the AWU peripheral */\r
+ AWU->CSR |= AWU_CSR_AWUEN;\r
+\r
+ /* Set the TimeBase */\r
+ AWU->TBR &= (uint8_t)(~AWU_TBR_AWUTB);\r
+ AWU->TBR |= TBR_Array[(uint8_t)AWU_TimeBase];\r
+\r
+ /* Set the APR divider */\r
+ AWU->APR &= (uint8_t)(~AWU_APR_APR);\r
+ AWU->APR |= APR_Array[(uint8_t)AWU_TimeBase];\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the AWU peripheral.\r
+ * @param NewState Indicates the new state of the AWU peripheral.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Initialisation of AWU and LS RC calibration must be done before.\r
+ */\r
+void AWU_Cmd(FunctionalState NewState)\r
+{\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the AWU peripheral */\r
+ AWU->CSR |= AWU_CSR_AWUEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the AWU peripheral */\r
+ AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update APR register with the measured LSI frequency.\r
+ * @par Note on the APR calculation:\r
+ * A is the integer part of lsifreqkhz/4 and x the decimal part.\r
+ * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]\r
+ * but we know that A + x = lsifreqkhz/4 ==> 4x = lsifreqkhz-4A\r
+ * so [F1] can be written :\r
+ * 4A >= (lsifreqkhz-4A)(1+2A)\r
+ * @param LSIFreqHz Low Speed RC frequency measured by timer (in Hz).\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * - AWU must be disabled to avoid unwanted interrupts.\r
+ */\r
+void AWU_LSICalibrationConfig(uint32_t LSIFreqHz)\r
+{\r
+\r
+ uint16_t lsifreqkhz = 0x0;\r
+ uint16_t A = 0x0;\r
+\r
+ /* Check parameter */\r
+ assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));\r
+\r
+ lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */\r
+\r
+ /* Calculation of AWU calibration value */\r
+\r
+ A = (uint16_t)(lsifreqkhz >> 2U); /* Division by 4, keep integer part only */\r
+\r
+ if ((4U * A) >= ((lsifreqkhz - (4U * A)) * (1U + (2U * A))))\r
+ {\r
+ AWU->APR = (uint8_t)(A - 2U);\r
+ }\r
+ else\r
+ {\r
+ AWU->APR = (uint8_t)(A - 1U);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures AWU in Idle mode to reduce power consumption.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void AWU_IdleModeEnable(void)\r
+{\r
+ /* Disable AWU peripheral */\r
+ AWU->CSR &= (uint8_t)(~AWU_CSR_AWUEN);\r
+\r
+ /* No AWU timebase */\r
+ AWU->TBR = (uint8_t)(~AWU_TBR_AWUTB);\r
+}\r
+\r
+/**\r
+ * @brief Returns status of the AWU peripheral flag.\r
+ * @param None\r
+ * @retval FlagStatus : Status of the AWU flag.\r
+ * This parameter can be any of the @ref FlagStatus enumeration.\r
+ */\r
+FlagStatus AWU_GetFlagStatus(void)\r
+{\r
+ return((FlagStatus)(((uint8_t)(AWU->CSR & AWU_CSR_AWUF) == (uint8_t)0x00) ? RESET : SET));\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_beep.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the BEEP peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_beep.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup BEEP_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the BEEP peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BEEP_DeInit(void)\r
+{\r
+ BEEP->CSR = BEEP_CSR_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the BEEP function according to the specified parameters.\r
+ * @param BEEP_Frequency Frequency selection.\r
+ * can be one of the values of @ref BEEP_Frequency_TypeDef.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * The LS RC calibration must be performed before calling this function.\r
+ */\r
+void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)\r
+{\r
+\r
+ /* Check parameter */\r
+ assert_param(IS_BEEP_FREQUENCY_OK(BEEP_Frequency));\r
+\r
+ /* Set a default calibration value if no calibration is done */\r
+ if ((BEEP->CSR & BEEP_CSR_BEEPDIV) == BEEP_CSR_BEEPDIV)\r
+ {\r
+ BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */\r
+ BEEP->CSR |= BEEP_CALIBRATION_DEFAULT;\r
+ }\r
+\r
+ /* Select the output frequency */\r
+ BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPSEL);\r
+ BEEP->CSR |= (uint8_t)(BEEP_Frequency);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enable or disable the BEEP function.\r
+ * @param NewState Indicates the new state of the BEEP function.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Initialisation of BEEP and LS RC calibration must be done before.\r
+ */\r
+void BEEP_Cmd(FunctionalState NewState)\r
+{\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the BEEP peripheral */\r
+ BEEP->CSR |= BEEP_CSR_BEEPEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the BEEP peripheral */\r
+ BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update CSR register with the measured LSI frequency.\r
+ * @par Note on the APR calculation:\r
+ * A is the integer part of LSIFreqkHz/4 and x the decimal part.\r
+ * x <= A/(1+2A) is equivalent to A >= x(1+2A) and also to 4A >= 4x(1+2A) [F1]\r
+ * but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A\r
+ * so [F1] can be written :\r
+ * 4A >= (LSIFreqkHz-4A)(1+2A)\r
+ * @param LSIFreqHz Low Speed RC frequency measured by timer (in Hz).\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * - BEEP must be disabled to avoid unwanted interrupts.\r
+ */\r
+void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)\r
+{\r
+\r
+ uint16_t lsifreqkhz;\r
+ uint16_t A;\r
+\r
+ /* Check parameter */\r
+ assert_param(IS_LSI_FREQUENCY_OK(LSIFreqHz));\r
+\r
+ lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */\r
+\r
+ /* Calculation of BEEPER calibration value */\r
+\r
+ BEEP->CSR &= (uint8_t)(~BEEP_CSR_BEEPDIV); /* Clear bits */\r
+\r
+ A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */\r
+\r
+ if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))\r
+ {\r
+ BEEP->CSR |= (uint8_t)(A - 2U);\r
+ }\r
+ else\r
+ {\r
+ BEEP->CSR |= (uint8_t)(A - 1U);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_can.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the CAN peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_can.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define CAN_IDLIST_IDMASK_MASK ((uint8_t) 0x55)\r
+#define CAN_IDMASK_IDLIST_MASK ((uint8_t) 0xAA)\r
+#define CAN_MODE_MASK ((uint8_t) 0x03)\r
+#define CAN_ACKNOWLEDGE_TIMEOUT ((uint16_t)0xFFFF)\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+__IO uint32_t _Id = 0;\r
+__IO uint8_t _IDE = 0;\r
+__IO uint8_t _RTR = 0;\r
+__IO uint8_t _DLC = 0;\r
+__IO uint8_t _Data[8] = {0};\r
+__IO uint8_t _FMI = 0;\r
+/* Private function prototypes -----------------------------------------------*/\r
+static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/**\r
+ * @addtogroup CAN_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CAN_DeInit(void)\r
+{\r
+ /* Request initialisation */\r
+ CAN->MCR = CAN_MCR_INRQ;\r
+ CAN->PSR = CAN_Page_Config;\r
+ CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);\r
+ CAN->Page.Config.ESR = CAN_ESR_RESET_VALUE;\r
+ CAN->Page.Config.EIER = CAN_EIER_RESET_VALUE;\r
+ CAN->Page.Config.BTR1 = CAN_BTR1_RESET_VALUE;\r
+ CAN->Page.Config.BTR2 = CAN_BTR2_RESET_VALUE;\r
+ CAN->Page.Config.FMR1 = CAN_FMR1_RESET_VALUE;\r
+ CAN->Page.Config.FMR2 = CAN_FMR2_RESET_VALUE;\r
+ CAN->Page.Config.FCR1 = CAN_FCR_RESET_VALUE;\r
+ CAN->Page.Config.FCR2 = CAN_FCR_RESET_VALUE;\r
+ CAN->Page.Config.FCR3 = CAN_FCR_RESET_VALUE;\r
+ CAN_OperatingModeRequest(CAN_OperatingMode_Normal);\r
+ CAN->PSR = CAN_Page_RxFifo;\r
+ CAN->Page.RxFIFO.MDLCR = CAN_MDLC_RESET_VALUE;\r
+ CAN->PSR = CAN_Page_TxMailBox0;\r
+ CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;\r
+ CAN->PSR = CAN_Page_TxMailBox1;\r
+ CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;\r
+ CAN->PSR = CAN_Page_TxMailBox2;\r
+ CAN->Page.TxMailbox.MDLCR = CAN_MDLC_RESET_VALUE;\r
+\r
+ CAN->MCR = CAN_MCR_RESET_VALUE;\r
+ CAN->MSR = (uint8_t)(~CAN_MSR_RESET_VALUE);/* rc_w1 */\r
+ CAN->TSR = (uint8_t)(~CAN_TSR_RESET_VALUE);/* rc_w1 */\r
+ CAN->RFR = (uint8_t)(~CAN_RFR_RESET_VALUE);/* rc_w1 */\r
+ CAN->IER = CAN_IER_RESET_VALUE;\r
+ CAN->DGR = CAN_DGR_RESET_VALUE;\r
+ CAN->PSR = CAN_PSR_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified parameters.\r
+ * @param CAN_MasterCtrl : Master control option, can be one or a combination of @ref CAN_MasterCtrl_TypeDef.\r
+ * @param CAN_Mode : CAN mode , can be one of @ref CAN_Mode_TypeDef.\r
+ * @param CAN_SynJumpWidth : CAN Synchronisation Jump Width , can be one of @ref CAN_SynJumpWidth_TypeDef.\r
+ * @param CAN_BitSeg1 : CAN bit segment 1 , can be one of @ref CAN_BitSeg1_TypeDef.\r
+ * @param CAN_BitSeg2 : CAN bit segment 2 , can be one of @ref CAN_BitSeg2_TypeDef.\r
+ * @param CAN_Prescaler : CAN Baud Rate Prescaler , can be a value from 0x01 to 0xFF.\r
+ * @retval Indicates if initialization is succeed. it can be one of @ref CAN_InitStatus_TypeDef enumeration.\r
+ */\r
+CAN_InitStatus_TypeDef CAN_Init(CAN_MasterCtrl_TypeDef CAN_MasterCtrl,\r
+ CAN_Mode_TypeDef CAN_Mode,\r
+ CAN_SynJumpWidth_TypeDef CAN_SynJumpWidth,\r
+ CAN_BitSeg1_TypeDef CAN_BitSeg1,\r
+ CAN_BitSeg2_TypeDef CAN_BitSeg2,\r
+ uint8_t CAN_Prescaler)\r
+{\r
+ CAN_InitStatus_TypeDef InitStatus = CAN_InitStatus_Failed;\r
+ uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_MASTERCTRL_OK(CAN_MasterCtrl));\r
+ assert_param(IS_CAN_MODE_OK(CAN_Mode));\r
+ assert_param(IS_CAN_SYNJUMPWIDTH_OK(CAN_SynJumpWidth));\r
+ assert_param(IS_CAN_BITSEG1_OK(CAN_BitSeg1));\r
+ assert_param(IS_CAN_BITSEG2_OK(CAN_BitSeg2));\r
+ assert_param(IS_CAN_PRESCALER_OK(CAN_Prescaler));\r
+\r
+ /* Request initialisation */\r
+ CAN->MCR = CAN_MCR_INRQ;\r
+ /* Wait the acknowledge */\r
+ while (((uint8_t)(CAN->MSR & CAN_MSR_INAK) != 0x01) && ((uint16_t)timeout != 0))\r
+ {\r
+ timeout--;\r
+ }\r
+\r
+ /* Check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+\r
+ InitStatus = CAN_InitStatus_Failed;\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Set the time triggered communication mode & Set the automatic bus-off management & Set the automatic wake-up mode\r
+ & Set the no automatic retransmission & Set the receive FIFO locked mode & Set the transmit FIFO priority */\r
+ CAN->MCR |= (uint8_t)CAN_MasterCtrl;\r
+\r
+ /* Set the bit timing register */\r
+ CAN->DGR |= (uint8_t)CAN_Mode ;\r
+ CAN->PSR = CAN_Page_Config;\r
+ CAN->Page.Config.BTR1 = (uint8_t)((uint8_t)(CAN_Prescaler - (uint8_t)1) | CAN_SynJumpWidth);\r
+ CAN->Page.Config.BTR2 = (uint8_t)(CAN_BitSeg1 | (uint8_t)CAN_BitSeg2);\r
+\r
+ /* Request leave initialisation */\r
+ CAN->MCR &= (uint8_t)(~CAN_MCR_INRQ);\r
+ /* Wait the acknowledge */\r
+ timeout = 0xFFFF;\r
+ while ((((uint8_t)(CAN->MSR & CAN_MSR_INAK) == 0x01))&&(timeout != 0))\r
+ {\r
+ timeout--;\r
+ }\r
+ /* Check acknowledged */\r
+ if ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CAN_InitStatus_Failed;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CAN_InitStatus_Success;\r
+ }\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+\r
+ /* Return the status of initialization */\r
+ return (CAN_InitStatus_TypeDef)InitStatus;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral Filter according to the specified parameters.\r
+ * @param CAN_FilterNumber : CAN Filter number , can be one of @ref CAN_FilterNumber_TypeDef\r
+ * @param CAN_FilterActivation : CAN Filter Activation state , can be one of @ref FunctionalState\r
+ * @param CAN_FilterMode : CAN Filter Mode , can be one of @ref CAN_FilterMode_TypeDef\r
+ * @param CAN_FilterScale : CAN Filter Scale , can be one of @ref CAN_FilterScale_TypeDef\r
+ * @param CAN_FilterID1 : CAN Filter ID 1 , can be a value from 0x00 to 0xFF\r
+ * @param CAN_FilterID2 : CAN Filter ID 2 , can be a value from 0x00 to 0xFF\r
+ * @param CAN_FilterID3 : CAN Filter ID 3 , can be a value from 0x00 to 0xFF\r
+ * @param CAN_FilterID4 : CAN Filter ID 4 , can be a value from 0x00 to 0xFF\r
+ * @param CAN_FilterIDMask1 : CAN Filter ID 1/ Mask 1 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter\r
+ * @param CAN_FilterIDMask2 : CAN Filter ID 2/ Mask 2 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter\r
+ * @param CAN_FilterIDMask3 : CAN Filter ID 3/ Mask 3 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter\r
+ * @param CAN_FilterIDMask4 : CAN Filter ID 4/ Mask 4 , can be a value from 0x00 to 0xFF depending of CAN_FilterMode parameter\r
+ * @retval None\r
+ */\r
+void CAN_FilterInit(CAN_FilterNumber_TypeDef CAN_FilterNumber,\r
+ FunctionalState CAN_FilterActivation,\r
+ CAN_FilterMode_TypeDef CAN_FilterMode,\r
+ CAN_FilterScale_TypeDef CAN_FilterScale,\r
+ uint8_t CAN_FilterID1,\r
+ uint8_t CAN_FilterID2,\r
+ uint8_t CAN_FilterID3,\r
+ uint8_t CAN_FilterID4,\r
+ uint8_t CAN_FilterIDMask1,\r
+ uint8_t CAN_FilterIDMask2,\r
+ uint8_t CAN_FilterIDMask3,\r
+ uint8_t CAN_FilterIDMask4)\r
+{\r
+ uint8_t fact = 0;\r
+ uint8_t fsc = 0;\r
+ uint8_t fmhl = 0;\r
+\r
+ CAN_Page_TypeDef can_page_filter = CAN_Page_Filter01;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER_OK(CAN_FilterNumber));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(CAN_FilterActivation));\r
+ assert_param(IS_CAN_FILTER_MODE_OK(CAN_FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE_OK(CAN_FilterScale));\r
+\r
+\r
+ if (CAN_FilterNumber == CAN_FilterNumber_0)\r
+ {\r
+ fact = 0x01;\r
+ fsc = 0x00;\r
+ fmhl = 0x03;\r
+\r
+ can_page_filter = CAN_Page_Filter01;\r
+ }\r
+ else if (CAN_FilterNumber == CAN_FilterNumber_1)\r
+ {\r
+ fact = 0x10;\r
+ fsc = 0x04;\r
+ fmhl = 0x0C;\r
+\r
+ can_page_filter = CAN_Page_Filter01;\r
+ }\r
+ else if (CAN_FilterNumber == CAN_FilterNumber_2)\r
+ {\r
+ fact = 0x01;\r
+ fsc = 0x00;\r
+ fmhl = 0x30;\r
+\r
+ can_page_filter = CAN_Page_Filter23;\r
+ }\r
+ else if (CAN_FilterNumber == CAN_FilterNumber_3)\r
+ {\r
+ fact = 0x10;\r
+ fsc = 0x04;\r
+ fmhl = 0xC0;\r
+\r
+ can_page_filter = CAN_Page_Filter23;\r
+ }\r
+ else if (CAN_FilterNumber == CAN_FilterNumber_4)\r
+ {\r
+ fact = 0x01;\r
+ fsc = 0x00;\r
+ fmhl = 0x03;\r
+\r
+ can_page_filter = CAN_Page_Filter45;\r
+ }\r
+ else /*if (CAN_FilterNumber == CAN_FilterNumber_5)*/\r
+ {\r
+ fact = 0x10;\r
+ fsc = 0x04;\r
+ fmhl = 0x0C;\r
+\r
+ can_page_filter = CAN_Page_Filter45;\r
+ }\r
+\r
+\r
+ CAN_OperatingModeRequest(CAN_OperatingMode_Initialization);\r
+\r
+ CAN->PSR = CAN_Page_Config;\r
+ /*---------------------------------------------------------*/\r
+ /*Configuration of Filter Scale */\r
+ /*---------------------------------------------------------*/\r
+\r
+ if (can_page_filter == CAN_Page_Filter01) /* FCR1 */\r
+ {\r
+ /* Filter Deactivation & Reset the Filter Scale */\r
+ CAN->Page.Config.FCR1 &= (uint8_t)(~(uint8_t)(fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc )));\r
+ /* Set the new Filter Scale */\r
+ CAN->Page.Config.FCR1 |= (uint8_t)(CAN_FilterScale << fsc);\r
+ }\r
+ else if (can_page_filter == CAN_Page_Filter23) /* FCR2*/\r
+ {\r
+ /* Filter Deactivation & Reset the Filter Scale */\r
+ CAN->Page.Config.FCR2 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));\r
+\r
+ /* Set the new Filter Scale */\r
+ CAN->Page.Config.FCR2 |= (uint8_t)(CAN_FilterScale << fsc);\r
+\r
+ }\r
+ else /*if(can_page_filter == CAN_Page_Filter45)*/ /* FCR3*/\r
+ {\r
+ /* Filter Deactivation & Reset the Filter Scale */\r
+ CAN->Page.Config.FCR3 &= (uint8_t)~(uint8_t)( fact | (uint8_t)((uint8_t)(CAN_FCR1_FSC00|CAN_FCR1_FSC01) << fsc ));\r
+\r
+ /* Set the new Filter Scale */\r
+ CAN->Page.Config.FCR3 |= (uint8_t)(CAN_FilterScale << fsc);\r
+ }\r
+\r
+ /*---------------------------------------------------------*/\r
+ /*Configuration of Filter Mode */\r
+ /*---------------------------------------------------------*/\r
+ if (can_page_filter != CAN_Page_Filter45) /* FMR1*/\r
+ {\r
+ /* Filter Mode */\r
+ if (CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN->Page.Config.FMR1 &= (uint8_t)~(fmhl);\r
+ }\r
+ else if ( CAN_FilterMode == CAN_FilterMode_IdList)\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN->Page.Config.FMR1 |= (uint8_t)(fmhl);\r
+ }\r
+ else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)\r
+ {\r
+ /*Identifier list mode is first for the filter*/\r
+ CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);\r
+ }\r
+ else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/\r
+ {\r
+ /*Id Mask mode is first for the filter*/\r
+ CAN->Page.Config.FMR1 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);\r
+ }\r
+\r
+\r
+ }\r
+ else /* FMR2 */\r
+ {\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN->Page.Config.FMR2 &= (uint8_t)~(fmhl);\r
+ }\r
+ else if ( CAN_FilterMode == CAN_FilterMode_IdList)\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN->Page.Config.FMR2 |= (uint8_t)(fmhl);\r
+ }\r
+ else if ( CAN_FilterMode == CAN_FilterMode_IdList_IdMask)\r
+ {\r
+ /*Identifier list mode is first for the filter*/\r
+ CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDLIST_IDMASK_MASK);\r
+ }\r
+ else /* ( CAN_FilterMode == CAN_FilterMode_IdMask_IdList)*/\r
+ {\r
+ /*Id Mask mode is first for the filter*/\r
+ CAN->Page.Config.FMR2 |= (uint8_t)(fmhl & CAN_IDMASK_IDLIST_MASK);\r
+ }\r
+ }\r
+ /*---------------------------------------------------------*/\r
+ /*Configuration of Filter IDs */\r
+ /*---------------------------------------------------------*/\r
+ CAN->PSR = (uint8_t)can_page_filter;\r
+ if (fsc != 0)\r
+ {\r
+ /* Filter Scale */\r
+ if (CAN_FilterScale == CAN_FilterScale_8Bit)\r
+ {\r
+ CAN->Page.Filter.FR09 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR10 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR11 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR12 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR13 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR14 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR15 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR16 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)\r
+ {\r
+ CAN->Page.Filter.FR09 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR10 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR11 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR12 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR13 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR14 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR15 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR16 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_16Bit)\r
+ {\r
+ CAN->Page.Filter.FR09 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR10 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR11 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR12 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR13 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR14 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR15 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR16 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_32Bit)\r
+ {\r
+ CAN->Page.Filter.FR09 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR10 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR11 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR12 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR13 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR14 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR15 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR16 = CAN_FilterIDMask4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Filter Scale */\r
+ if (CAN_FilterScale == CAN_FilterScale_8Bit)\r
+ {\r
+ CAN->Page.Filter.FR01 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR02 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR03 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR04 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR05 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR06 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR07 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR08 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_16_8Bit)\r
+ {\r
+ CAN->Page.Filter.FR01 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR02 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR03 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR04 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR05 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR06 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR07 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR08 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_16Bit)\r
+ {\r
+ CAN->Page.Filter.FR01 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR02 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR03 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR04 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR05 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR06 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR07 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR08 = CAN_FilterIDMask4;\r
+ }\r
+ else if (CAN_FilterScale == CAN_FilterScale_32Bit)\r
+ {\r
+ CAN->Page.Filter.FR01 = CAN_FilterID1;\r
+ CAN->Page.Filter.FR02 = CAN_FilterID2;\r
+ CAN->Page.Filter.FR03 = CAN_FilterID3;\r
+ CAN->Page.Filter.FR04 = CAN_FilterID4;\r
+ CAN->Page.Filter.FR05 = CAN_FilterIDMask1;\r
+ CAN->Page.Filter.FR06 = CAN_FilterIDMask2;\r
+ CAN->Page.Filter.FR07 = CAN_FilterIDMask3;\r
+ CAN->Page.Filter.FR08 = CAN_FilterIDMask4;\r
+ }\r
+ }\r
+\r
+\r
+ /*---------------------------------------------------------*/\r
+ /*Configuration of Filter Activation */\r
+ /*---------------------------------------------------------*/\r
+ /* Filter activation */\r
+ CAN->PSR = CAN_Page_Config;\r
+ if (CAN_FilterActivation != DISABLE)\r
+ {\r
+ if ((CAN_FilterNumber & 0x06) == 0x00) /* FCR1*/\r
+ { CAN->Page.Config.FCR1 |= (uint8_t)fact;\r
+ }\r
+ else if ((CAN_FilterNumber & 0x06) == 0x02) /*FCR2*/\r
+ { CAN->Page.Config.FCR2 |= (uint8_t)fact;\r
+ }\r
+ else /*if((CAN_FilterNumber & 0x06) == 0x04)*/ /*FCR3*/\r
+ { CAN->Page.Config.FCR3 |= (uint8_t)fact;\r
+ }\r
+ }\r
+ CAN_OperatingModeRequest(CAN_OperatingMode_Normal);\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CAN interrupts.\r
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
+ * @param NewState : CAN_IT new state , can be one of @ref FunctionalState\r
+ * @retval None\r
+ */\r
+void CAN_ITConfig(CAN_IT_TypeDef CAN_IT, FunctionalState NewState)\r
+{\r
+ uint8_t tmperrorinterrupt = 0;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IT_CONFIG_OK(CAN_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ tmperrorinterrupt = (uint8_t)(((uint16_t)CAN_IT) >>7);\r
+ tmperrorinterrupt = (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0xF0) | \r
+ (uint8_t)((uint8_t)((uint16_t)tmperrorinterrupt & 0x0F) >>1));\r
+\r
+ CAN->PSR = CAN_Page_Config;\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CAN interrupt */\r
+ CAN->IER |= (uint8_t)(CAN_IT);\r
+ CAN->Page.Config.EIER |= (uint8_t)(tmperrorinterrupt);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CAN interrupt */\r
+ CAN->IER &= (uint8_t)~(uint8_t)((uint16_t)CAN_IT);\r
+ CAN->Page.Config.EIER &= (uint8_t)~(tmperrorinterrupt);\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the ST7 CAN Compatibility.\r
+ * if the ST7 compatibility is Enabled, CAN provides only 2 mailboxes.\r
+ * if the ST7 compatibility is Disabled, CAN provides 3 mailboxes.\r
+ * @param CAN_ST7Compatibility : CAN ST7 Compatibility , this parameter can be one of @ref CAN_ST7Compatibility_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void CAN_ST7CompatibilityCmd(CAN_ST7Compatibility_TypeDef CAN_ST7Compatibility)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ST7_COMPATIBILITY_OK(CAN_ST7Compatibility));\r
+ /*Reset the old configuration of TXM2E */\r
+ CAN->DGR &= (uint8_t)(~CAN_DGR_TXM2E);\r
+\r
+ /*Set the old configuration of TXM2E */\r
+ CAN->DGR |= (uint8_t)CAN_ST7Compatibility;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CAN Time TriggerOperation communication mode.\r
+ * @param NewState : Mode new state , can be one of @ref FunctionalState\r
+ * @retval None\r
+ */\r
+void CAN_TTComModeCmd(FunctionalState NewState)\r
+{\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /*Enable the TTCM mode */\r
+ CAN->MCR |= CAN_MCR_TTCM;\r
+ /*Set TGT bits setting in Tx and FIFO pages*/\r
+ CAN->PSR = CAN_Page_TxMailBox0;\r
+ CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;\r
+ CAN->PSR = CAN_Page_TxMailBox1;\r
+ CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;\r
+ CAN->PSR = CAN_Page_TxMailBox2;\r
+ CAN->Page.TxMailbox.MDLCR |= CAN_MDLCR_TGT;\r
+ CAN->PSR = CAN_Page_RxFifo;\r
+ CAN->Page.RxFIFO.MDLCR |= CAN_MDLCR_TGT;\r
+ }\r
+ else\r
+ {\r
+ /*Disable the TTCM mode */\r
+ CAN->MCR &= ((uint8_t)~CAN_MCR_TTCM);\r
+ /*Reset TGT bits setting in Tx and FIFO pages*/\r
+ CAN->PSR = CAN_Page_TxMailBox0;\r
+ CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);\r
+ CAN->PSR = CAN_Page_TxMailBox1;\r
+ CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);\r
+ CAN->PSR = CAN_Page_TxMailBox2;\r
+ CAN->Page.TxMailbox.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);\r
+ CAN->PSR = CAN_Page_RxFifo;\r
+ CAN->Page.RxFIFO.MDLCR &= ((uint8_t)~CAN_MDLCR_TGT);\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Initiates the transmission of a message.\r
+ * @param CAN_Id the ID number of the message, its size depends on @ref CAN_IDE value.\r
+ * @param[in] CAN_IDE the ID type of the message, this parameter can be one of the @ref CAN_Id_TypeDef enumeration.\r
+ * @param[in] CAN_RTR the message type, this parameter can be one of the @ref CAN_RTR_TypeDef enumeration.\r
+ * @param[in] CAN_DLC the number of data in the message type, this parameter can be a value between 0 to 7.\r
+ * @param[in] CAN_Data pointer to a the @ref uint8_t table which contains data to sent.\r
+ * @retval Transmit Status, this returned value can be one of the @ref CAN_TxStatus_TypeDef enumeration.\r
+ */\r
+CAN_TxStatus_TypeDef CAN_Transmit(uint32_t CAN_Id,\r
+ CAN_Id_TypeDef CAN_IDE,\r
+ CAN_RTR_TypeDef CAN_RTR,\r
+ uint8_t CAN_DLC,\r
+ uint8_t *CAN_Data)\r
+{\r
+ CAN_TxStatus_TypeDef CAN_TxStatus = CAN_TxStatus_NoMailBox;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IDTYPE_OK(CAN_IDE));\r
+ if (CAN_IDE != CAN_Id_Standard)\r
+ {\r
+ assert_param(IS_CAN_EXTID_OK(CAN_Id));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_STDID_OK(CAN_Id));\r
+ }\r
+ assert_param(IS_CAN_RTR_OK(CAN_RTR));\r
+ assert_param(IS_CAN_DLC_OK(CAN_DLC));\r
+ /* Select one empty transmit mailbox */\r
+ if ((CAN->TPR & CAN_TPR_TME0) == CAN_TPR_TME0)\r
+ {\r
+ CAN_TxStatus = CAN_TxStatus_MailBox0Ok;\r
+ }\r
+ else if ((CAN->TPR & CAN_TPR_TME1) == CAN_TPR_TME1)\r
+ {\r
+ CAN_TxStatus = CAN_TxStatus_MailBox1Ok;\r
+ }\r
+ else if ((CAN->TPR & CAN_TPR_TME2) == CAN_TPR_TME2)\r
+ {\r
+ CAN_TxStatus = CAN_TxStatus_MailBox2Ok;\r
+ }\r
+ else\r
+ {\r
+ CAN_TxStatus = CAN_TxStatus_NoMailBox;\r
+ }\r
+ if (CAN_TxStatus != CAN_TxStatus_NoMailBox)\r
+ {\r
+ CAN->PSR = (uint8_t)CAN_TxStatus;\r
+ /* Set up the Id */\r
+ if (CAN_IDE != CAN_Id_Standard)\r
+ {\r
+ CAN_Id &= (uint32_t)CAN_EXTID_SIZE;\r
+ CAN->Page.TxMailbox.MIDR4 = (uint8_t)(CAN_Id);\r
+ CAN_Id = CAN_Id>>8;\r
+ CAN->Page.TxMailbox.MIDR3 = (uint8_t)(CAN_Id);\r
+ CAN_Id = CAN_Id>>8;\r
+ CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id);\r
+ CAN_Id = CAN_Id>>8;\r
+ CAN->Page.TxMailbox.MIDR1 = (uint8_t)(CAN_Id |CAN_IDE | CAN_RTR);\r
+ }\r
+ else\r
+ {\r
+ CAN_Id &= (uint16_t)CAN_STDID_SIZE;\r
+ CAN->Page.TxMailbox.MIDR1 = (uint8_t)((CAN_Id>>6) | (CAN_RTR)) ;\r
+ CAN->Page.TxMailbox.MIDR2 = (uint8_t)(CAN_Id<<2);\r
+ }\r
+ /* Set up the DLC */\r
+ /*clear old DLC value*/\r
+ CAN->Page.TxMailbox.MDLCR &= (uint8_t)0xF0;\r
+ /*set the new value of DLC*/\r
+ CAN->Page.TxMailbox.MDLCR |= CAN_DLC;\r
+ /* Set up the data field */\r
+ CAN->Page.TxMailbox.MDAR1 = CAN_Data[0];\r
+ CAN->Page.TxMailbox.MDAR2 = CAN_Data[1];\r
+ CAN->Page.TxMailbox.MDAR3 = CAN_Data[2];\r
+ CAN->Page.TxMailbox.MDAR4 = CAN_Data[3];\r
+ CAN->Page.TxMailbox.MDAR5 = CAN_Data[4];\r
+ CAN->Page.TxMailbox.MDAR6 = CAN_Data[5];\r
+ CAN->Page.TxMailbox.MDAR7 = CAN_Data[6];\r
+ CAN->Page.TxMailbox.MDAR8 = CAN_Data[7];\r
+ /* Request transmission */\r
+ CAN->Page.TxMailbox.MCSR |= CAN_MCSR_TXRQ;\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+ return (CAN_TxStatus_TypeDef)CAN_TxStatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks the transmission of a message.\r
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission, can be on of @ref CAN_TransmitMailBox_TypeDef.\r
+ * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.\r
+ */\r
+CAN_TxStatus_TypeDef CAN_TransmitStatus(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ CAN_TxStatus_TypeDef tstate = CAN_TxStatus_Failed;\r
+ uint8_t tmpstate=0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));\r
+\r
+ switch (CAN_TransmitMailbox)\r
+ {\r
+ case (CAN_TransmitMailBox_0): tmpstate = (uint8_t)((CAN->TSR & (uint8_t)(CAN_TSR_RQCP0|CAN_TSR_TXOK0)));\r
+ tmpstate |= (uint8_t)((CAN->TPR & CAN_TPR_TME0));\r
+ break;\r
+ case (CAN_TransmitMailBox_1): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP1|CAN_TSR_TXOK1))>>1);\r
+ tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME1) >> 1);\r
+ break;\r
+ case (CAN_TransmitMailBox_2): tmpstate = (uint8_t)((uint8_t)(CAN->TSR & (uint8_t)(CAN_TSR_RQCP2|CAN_TSR_TXOK2))>>2);\r
+ tmpstate |= (uint8_t)((uint8_t)(CAN->TPR & CAN_TPR_TME2) >> 2);\r
+ break;\r
+ default:\r
+ tstate = CAN_TxStatus_Failed;\r
+ break;\r
+ }\r
+\r
+ switch (tmpstate)\r
+ {\r
+ /*transmit pending */\r
+ case (0x00): tstate = CAN_TxStatus_Pending;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x05): tstate = CAN_TxStatus_Failed;\r
+ break;\r
+ /* transmit succeeded */\r
+ case (0x15): tstate = CAN_TxStatus_Ok;\r
+ break;\r
+ /* transmit mailbox is empty : no activity on this TX mail box */\r
+ case (0x04): tstate = CAN_TxStatus_MailBoxEmpty;\r
+ break;\r
+ default:\r
+ tstate = CAN_TxStatus_Failed;\r
+ break;\r
+ }\r
+\r
+ return (CAN_TxStatus_TypeDef)tstate;\r
+}\r
+\r
+/**\r
+ * @brief Cancels a transmit request.\r
+ * @param TransmitMailbox : the Transmission mailbox, can be one of CAN_TransmitMailBox_TypeDef\r
+ * @retval None\r
+ */\r
+void CAN_CancelTransmit(CAN_TransmitMailBox_TypeDef CAN_TransmitMailbox)\r
+{\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_TRANSMITMAILBOX_OK(CAN_TransmitMailbox));\r
+ /*switch to the specific page */\r
+ CAN->PSR = (uint8_t)CAN_TransmitMailbox;\r
+ /* abort transmission */\r
+ CAN->Page.TxMailbox.MCSR |= CAN_MCSR_ABRQ;\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Releases the CAN FIFO.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CAN_FIFORelease(void)\r
+{\r
+ /* Release FIFO*/\r
+ CAN->RFR = CAN_RFR_RFOM; /*rc-w1*/\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of pending messages.\r
+ * @retval Number of pending messages.\r
+ */\r
+CAN_NbrPendingMessage_TypeDef CAN_MessagePending(void)\r
+{\r
+ CAN_NbrPendingMessage_TypeDef msgpending = CAN_NbrPendingMessage_0;\r
+ msgpending = (CAN_NbrPendingMessage_TypeDef)(CAN->RFR & CAN_RFR_FMP01);\r
+ return (CAN_NbrPendingMessage_TypeDef)msgpending;\r
+}\r
+\r
+/**\r
+ * @brief Receives a message which contains CAN Id, IDE, RTR\r
+ * DLC, datas and FMI number.\r
+ * In order to get these data, use CAN_GetReceivedId(), CAN_GetReceivedIDE(), CAN_GetReceivedRTR(),\r
+ * CAN_GetReceivedDLC(), CAN_GetReceivedFMI() and CAN_GetReceivedData() functions.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CAN_Receive(void)\r
+{\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+ uint32_t temp1 = 0, temp2 = 0, temp3 = 0;\r
+\r
+ /* select Fifo page*/\r
+ CAN->PSR = CAN_Page_RxFifo;\r
+\r
+ /* Get the Id */\r
+ _IDE = (uint8_t)(CAN->Page.RxFIFO.MIDR1 & CAN_Id_Extended);\r
+ if (_IDE != CAN_Id_Standard)\r
+ {\r
+ temp1 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR3) << 8);\r
+ temp2 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR2) << 16); \r
+ temp3 = ((uint32_t)((uint32_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 24);\r
+\r
+ _Id = (uint32_t)CAN_EXTID_SIZE & ((CAN->Page.RxFIFO.MIDR4) | temp1 | temp2 | temp3 );\r
+ }\r
+ else\r
+ {\r
+ temp1 = (uint16_t)((uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR1 & 0x1F) << 6));\r
+ temp2 = (uint16_t)((uint16_t)((uint16_t)CAN->Page.RxFIFO.MIDR2 >> 2)&0x3F);\r
+\r
+ _Id = (uint16_t)CAN_STDID_SIZE & (temp1 | temp2 );\r
+ }\r
+\r
+ _RTR = (uint8_t)((uint8_t)0x20 & CAN->Page.RxFIFO.MIDR1);\r
+\r
+ /* Get the DLC */\r
+ _DLC = (uint8_t)(CAN->Page.RxFIFO.MDLCR & (uint8_t)0x0F);\r
+\r
+ /* Get the FMI */\r
+ _FMI = CAN->Page.RxFIFO.MFMI;\r
+\r
+ /* Get the data field */\r
+ _Data[0] = CAN->Page.RxFIFO.MDAR1;\r
+ _Data[1] = CAN->Page.RxFIFO.MDAR2;\r
+ _Data[2] = CAN->Page.RxFIFO.MDAR3;\r
+ _Data[3] = CAN->Page.RxFIFO.MDAR4;\r
+ _Data[4] = CAN->Page.RxFIFO.MDAR5;\r
+ _Data[5] = CAN->Page.RxFIFO.MDAR6;\r
+ _Data[6] = CAN->Page.RxFIFO.MDAR7;\r
+ _Data[7] = CAN->Page.RxFIFO.MDAR8;\r
+\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease();\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN Id of the received message.\r
+ * @param None\r
+ * @retval the received CAN message Id.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+uint32_t CAN_GetReceivedId(void)\r
+{\r
+ return (_Id);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN IDE of the received message.\r
+ * @param None\r
+ * @retval the received CAN message IDE.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+CAN_Id_TypeDef CAN_GetReceivedIDE(void)\r
+{\r
+ return (CAN_Id_TypeDef)(_IDE);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN RTR of the received message.\r
+ * @param None\r
+ * @retval the received CAN message RTR.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+CAN_RTR_TypeDef CAN_GetReceivedRTR(void)\r
+{\r
+ return (CAN_RTR_TypeDef)(_RTR);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN DLC of the received message.\r
+ * @param None\r
+ * @retval the received CAN message DLC.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+uint8_t CAN_GetReceivedDLC(void)\r
+{\r
+ return (_DLC);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN Data of the received message.\r
+ * @param CAN_DataIndexe : number of the received Data, it can\r
+ * be an integer between 0 to 7.\r
+ * @retval the received CAN message ith Data.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+uint8_t CAN_GetReceivedData(uint8_t CAN_DataIndex)\r
+{\r
+ assert_param(IS_CAN_DLC_OK(CAN_DataIndex));\r
+ return (_Data[CAN_DataIndex]);\r
+}\r
+\r
+/**\r
+ * @brief Gets the CAN FMI of the received message.\r
+ * @param None\r
+ * @retval the received CAN message FMI.\r
+ * @par Required preconditions:\r
+ * This function is used to get data loaded by CAN_Receive function.\r
+ * Before using this function, CAN_Receive function must be called.\r
+ */\r
+uint8_t CAN_GetReceivedFMI(void)\r
+{\r
+ return (_FMI);\r
+}\r
+\r
+/**\r
+ * @brief Returns the Received time stamp.\r
+ * @param None\r
+ * @retval uint16_t the received time stamp.\r
+ */\r
+uint16_t CAN_GetMessageTimeStamp(void)\r
+{\r
+ uint16_t timestamp = 0;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+ /*switch to the specific page */\r
+ CAN->PSR = CAN_Page_RxFifo;\r
+ /* Get the Received Time stamp */\r
+ timestamp = CAN->Page.RxFIFO.MTSRL;\r
+ timestamp |= (uint16_t)(((uint16_t)CAN->Page.RxFIFO.MTSRH)<<8);\r
+\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+\r
+ return (uint16_t)(timestamp);\r
+}\r
+\r
+/**\r
+ * @brief Enters the Sleep low power mode.\r
+ * @param None\r
+ * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an other case.\r
+ */\r
+CAN_Sleep_TypeDef CAN_Sleep(void)\r
+{\r
+\r
+ CAN_Sleep_TypeDef sleepstatus = CAN_Sleep_Failed;\r
+\r
+ /* Request Sleep mode */\r
+ CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode not entered */\r
+ sleepstatus = CAN_Sleep_Ok;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return (CAN_Sleep_TypeDef) sleepstatus;\r
+}\r
+\r
+/**\r
+ * @brief Wakes the CAN up.\r
+ * @param None\r
+ * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an other case.\r
+ */\r
+CAN_WakeUp_TypeDef CAN_WakeUp(void)\r
+{\r
+ CAN_WakeUp_TypeDef wakeupstatus = CAN_WakeUp_Failed;\r
+\r
+ /* Wake up request */\r
+ CAN->MCR &= (uint8_t)(~CAN_MCR_SLEEP);\r
+\r
+ /* Sleep mode status */\r
+ if ((CAN->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode exited */\r
+ wakeupstatus = CAN_WakeUp_Ok;\r
+ }\r
+\r
+ /* At this step, sleep mode status */\r
+ return (CAN_WakeUp_TypeDef)wakeupstatus;\r
+}\r
+\r
+/**\r
+ * @brief Select the CAN Operation mode.\r
+ * @param CAN_OperatingMode CAN Operating Mode ,\r
+ * this parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.\r
+ * @retval the status of the requested mode which can be \r
+ * - CAN_ModeStatus_Failed CAN failed entring the specific mode\r
+ * - CAN_ModeStatus_Success CAN Succeed entring the specific mode \r
+\r
+ */\r
+CAN_ModeStatus_TypeDef CAN_OperatingModeRequest(CAN_OperatingMode_TypeDef CAN_OperatingMode)\r
+{\r
+\r
+ uint16_t timeout = CAN_ACKNOWLEDGE_TIMEOUT;\r
+ uint8_t modestatus = 0;\r
+\r
+ assert_param(IS_CAN_OPERATINGMODE_OK(CAN_OperatingMode));\r
+\r
+ if (CAN_OperatingMode == CAN_OperatingMode_Initialization)\r
+ {\r
+ /* Request initialisation */\r
+ CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_SLEEP)) | CAN_MCR_INRQ);\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))\r
+ {\r
+ timeout--;\r
+ }\r
+ if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)\r
+ {\r
+ modestatus = CAN_ModeStatus_Failed;\r
+ }\r
+ else\r
+ {\r
+ modestatus = CAN_ModeStatus_Success; \r
+ }\r
+\r
+ }\r
+ else if (CAN_OperatingMode == CAN_OperatingMode_Normal)\r
+ {\r
+ /* Request leave initialisation and sleep mode and enter Normal mode */\r
+ CAN->MCR &= (uint8_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CAN->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))\r
+ {\r
+ timeout--;\r
+ }\r
+ if ((CAN->MSR & CAN_MODE_MASK) != 0)\r
+ {\r
+ modestatus = CAN_ModeStatus_Failed;\r
+ }\r
+ else\r
+ {\r
+ modestatus = CAN_ModeStatus_Success; \r
+ }\r
+ }\r
+ else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)\r
+ {\r
+ /* Request Sleep mode */\r
+ CAN->MCR = (uint8_t)((uint8_t)(CAN->MCR & (uint8_t)(~CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))\r
+ {\r
+ timeout--;\r
+ }\r
+ if ((CAN->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)\r
+ {\r
+ modestatus = CAN_ModeStatus_Failed; \r
+ }\r
+ else\r
+ {\r
+ modestatus = CAN_ModeStatus_Success; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ modestatus = CAN_ModeStatus_Failed;\r
+ }\r
+ return (CAN_ModeStatus_TypeDef)(modestatus);\r
+}\r
+\r
+/**\r
+ * @brief Gets the Last Error Code.\r
+ * @param None\r
+ * @retval Error Code.\r
+ */\r
+CAN_ErrorCode_TypeDef CAN_GetLastErrorCode(void)\r
+{\r
+ CAN_ErrorCode_TypeDef errcode = CAN_ErrorCode_NoErr;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+ CAN->PSR = CAN_Page_Config;\r
+ errcode = (CAN_ErrorCode_TypeDef)((CAN->Page.Config.ESR) & (CAN_ESR_LEC));\r
+\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+\r
+ return (CAN_ErrorCode_TypeDef)(errcode);\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN's pending flags.\r
+ * @param CAN_FLAG : Flag to be cleared, can be one of the following parameters:\r
+ * CAN_FLAG_RQCP0 Request MailBox0 Flag\r
+ * CAN_FLAG_RQCP1 Request MailBox1 Flag\r
+ * CAN_FLAG_RQCP2 Request MailBox2 Flag\r
+ * CAN_FLAG_FF FIFO Full Flag\r
+ * CAN_FLAG_FOV FIFO Overrun Flag\r
+ * CAN_FLAG_WKU wake up Flag\r
+ * CAN_FLAG_LEC Last error code Flag\r
+ * @retval None\r
+ */\r
+void CAN_ClearFlag(CAN_FLAG_TypeDef CAN_Flag)\r
+{\r
+ CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FLAG_CLEAR_OK(CAN_Flag));\r
+ if (((uint16_t)CAN_Flag & 0x0700)!= RESET)\r
+ {\r
+ if (((uint16_t)CAN_Flag & 0x020B)!= RESET)\r
+ {\r
+ /*Receive Flags*/\r
+ CAN->RFR = (uint8_t)(CAN_Flag);\r
+ }\r
+ else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)\r
+ {\r
+ /*Transmit Flags*/\r
+ CAN->TSR = (uint8_t)(CAN_Flag);\r
+ }\r
+ else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/\r
+ {\r
+ /*wake up Flags*/\r
+ CAN->MSR = (uint8_t)(CAN_Flag);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*Error Flags*/\r
+ can_page = CAN_GetSelectedPage();\r
+\r
+ /* Clear the selected CAN flags */\r
+ CAN->PSR = CAN_Page_Config;\r
+ CAN->Page.Config.ESR = (uint8_t)RESET;\r
+\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN flag is set or not.\r
+ * @param CAN_FLAG: specifies the flag to check, can be one of @ref CAN_FLAG_TypeDef enumeration.\r
+ * @retval The new state of CAN_FLAG which can be one of @ref FlagStatus.\r
+ */\r
+FlagStatus CAN_GetFlagStatus(CAN_FLAG_TypeDef CAN_Flag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ CAN_Page_TypeDef can_page = (CAN_Page_TypeDef)0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FLAG_STATUS_OK(CAN_Flag));\r
+\r
+ if (((uint16_t)CAN_Flag & 0x0700)!= RESET)\r
+ {\r
+ if (((uint16_t)CAN_Flag & 0x020B)!= RESET)\r
+ {\r
+ /*Receive Flags*/\r
+ if ((CAN->RFR & (uint16_t)CAN_Flag )!= RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ }\r
+ else if (((uint16_t)CAN_Flag & 0x0403)!= RESET)\r
+ {\r
+ /*Transmit Flags*/\r
+ if ((CAN->TSR & (uint16_t)CAN_Flag )!= RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else /*if((CAN_Flag & 0x0108)!=(uint16_t)RESET)*/\r
+ {\r
+ /*wake up Flags*/\r
+ if ((CAN->MSR & (uint16_t)CAN_Flag )!= RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /*Error Flags*/\r
+ can_page = CAN_GetSelectedPage();\r
+\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.ESR & (uint16_t)CAN_Flag) != RESET)\r
+ {\r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+ }\r
+\r
+\r
+ /* Return the CAN_FLAG status */\r
+ return (FlagStatus)bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN interrupt has occurred or not.\r
+ * @param CAN_IT: specifies the CAN interrupt source to check, can be one of @ref CAN_IT_TypeDef.\r
+ * @retval The new state of CAN_IT, which can be one of @ref ITStatus.\r
+ */\r
+ITStatus CAN_GetITStatus(CAN_IT_TypeDef CAN_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IT_STATUS_OK(CAN_IT));\r
+\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ if ((CAN->IER & CAN_IER_TMEIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->TSR, CAN_TSR_RQCP012);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+\r
+ case CAN_IT_FMP:\r
+ if ((CAN->IER & CAN_IER_FMPIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FMP01);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ case CAN_IT_FF:\r
+ if ((CAN->IER & CAN_IER_FFIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FULL);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ case CAN_IT_FOV:\r
+ if ((CAN->IER & CAN_IER_FOVIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->RFR, CAN_RFR_FOVR);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ case CAN_IT_WKU:\r
+ if ((CAN->IER & CAN_IER_WKUIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->MSR, CAN_MSR_WKUI);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+\r
+ case CAN_IT_ERR:\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.EIER & CAN_EIER_ERRIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+\r
+ case CAN_IT_EWG:\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.EIER & CAN_EIER_EWGIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EWGF);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+\r
+ case CAN_IT_EPV:\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.EIER & CAN_EIER_EPVIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_EPVF);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ case CAN_IT_BOF:\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.EIER & CAN_EIER_BOFIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_BOFF);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ case CAN_IT_LEC:\r
+ CAN->PSR = CAN_Page_Config;\r
+ if ((CAN->Page.Config.EIER & CAN_EIER_LECIE) !=RESET)\r
+ {\r
+ pendingbitstatus = CheckITStatus(CAN->Page.Config.ESR, CAN_ESR_LEC);\r
+ }\r
+ else\r
+ {\r
+ pendingbitstatus = RESET;\r
+ }\r
+ break;\r
+ default :\r
+ pendingbitstatus = RESET;\r
+ break;\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+ /* Return the CAN_IT status */\r
+ return (ITStatus)pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN\92s interrupt pending bits.\r
+ * @param CAN_IT: specifies the interrupt pending bit to clear,\r
+ * can be one of the following parameters:\r
+ * CAN_IT_TME = Transmit mailbox empty interrupt\r
+ * CAN_IT_FF =FIFO full interrupt\r
+ * CAN_IT_FOV =FIFO overrun interrupt\r
+ * CAN_IT_WKU =Wake-up interrupt\r
+ * CAN_IT_ERR =General Error interrupt\r
+ * CAN_IT_EWG =Error warning interrupt\r
+ * CAN_IT_EPV =Error passive interrupt\r
+ * CAN_IT_BOF = Bus-off interrupt\r
+ * CAN_IT_LEC =Last error code interrupt\r
+ * @retval None\r
+ */\r
+void CAN_ClearITPendingBit(CAN_IT_TypeDef CAN_IT)\r
+{\r
+ CAN_Page_TypeDef can_page = CAN_GetSelectedPage();\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_IT_PENDING_BIT_OK(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ CAN->TSR = CAN_TSR_RQCP012;/* rc_w1*/\r
+ break;\r
+\r
+ case CAN_IT_FF:\r
+ CAN->RFR = CAN_RFR_FULL; /* rc_w1*/\r
+ break;\r
+\r
+ case CAN_IT_FOV:\r
+ CAN->RFR = CAN_RFR_FOVR; /* rc_w1*/\r
+ break;\r
+\r
+ case CAN_IT_WKU:\r
+ CAN->MSR = CAN_MSR_WKUI; /* rc_w1*/\r
+ break;\r
+\r
+ case CAN_IT_ERR:\r
+ CAN->PSR = CAN_Page_Config;\r
+ CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;\r
+ CAN->MSR = CAN_MSR_ERRI;\r
+ break;\r
+\r
+ case CAN_IT_EWG:\r
+ CAN->MSR = CAN_MSR_ERRI;\r
+ break;\r
+\r
+ case CAN_IT_EPV:\r
+ CAN->MSR = CAN_MSR_ERRI;\r
+ break;\r
+\r
+ case CAN_IT_BOF:\r
+ CAN->MSR = CAN_MSR_ERRI;\r
+ break;\r
+\r
+ case CAN_IT_LEC:\r
+ CAN->PSR = CAN_Page_Config;\r
+ CAN->Page.Config.ESR = (uint8_t)CAN_ESR_RESET_VALUE;\r
+ break;\r
+\r
+\r
+\r
+ default :\r
+ break;\r
+ }\r
+ /*Restore Last Page*/\r
+ CAN_SelectPage(can_page);\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected registers page.\r
+ * @param None\r
+ * @retval the selected page which can be one of the @ref CAN_Page_TypeDef.\r
+ */\r
+CAN_Page_TypeDef CAN_GetSelectedPage(void)\r
+{\r
+ return (CAN_Page_TypeDef)(CAN->PSR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the registers page to be selected.\r
+ * @param the selected page which can be one of the @ref CAN_Page_TypeDef.\r
+ * @retval None\r
+ */\r
+void CAN_SelectPage(CAN_Page_TypeDef CAN_Page)\r
+{\r
+ CAN->PSR = (uint8_t)CAN_Page;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the CAN interrupt has occurred or not.\r
+ * @param CAN_Reg: specifies the CAN interrupt register to check.\r
+ * @param It_Bit: specifies the interrupt source bit to check.\r
+ * @retval The new state of the CAN Interrupt, which can be one of ITStatus.\r
+ */\r
+static ITStatus CheckITStatus(uint8_t CAN_Reg, uint8_t It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ if ((CAN_Reg & It_Bit) != (uint8_t)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+ return (ITStatus)pendingbitstatus;\r
+}\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_clk.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the CLK peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+#include "stm8s_clk.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/* Private Constants ---------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup CLK_Private_Constants\r
+ * @{\r
+ */\r
+\r
+CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}; /*!< Holds the different HSI Divider factors */\r
+CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}; /*!< Holds the different CLK prescaler values */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+/**\r
+ * @addtogroup CLK_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CLK peripheral registers to their default reset\r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ * @par Warning:\r
+ * Resetting the CCOR register: \n\r
+ * When the CCOEN bit is set, the reset of the CCOR register require\r
+ * two consecutive write instructions in order to reset first the CCOEN bit\r
+ * and the second one is to reset the CCOSEL bits.\r
+ */\r
+void CLK_DeInit(void)\r
+{\r
+\r
+ CLK->ICKR = CLK_ICKR_RESET_VALUE;\r
+ CLK->ECKR = CLK_ECKR_RESET_VALUE;\r
+ CLK->SWR = CLK_SWR_RESET_VALUE;\r
+ CLK->SWCR = CLK_SWCR_RESET_VALUE;\r
+ CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;\r
+ CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;\r
+ CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;\r
+ CLK->CSSR = CLK_CSSR_RESET_VALUE;\r
+ CLK->CCOR = CLK_CCOR_RESET_VALUE;\r
+ while ((CLK->CCOR & CLK_CCOR_CCOEN)!= 0)\r
+ {}\r
+ CLK->CCOR = CLK_CCOR_RESET_VALUE;\r
+ CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;\r
+ CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed Internal oscillator (HSI).\r
+ * @par Full description:\r
+ * If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically\r
+ * switched-on (HSIEN=1) and selected as next clock master\r
+ * (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.\n\r
+ * @param NewState this parameter is the Wake-up Mode state.\r
+ * @retval None\r
+ */\r
+void CLK_FastHaltWakeUpCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set FHWU bit (HSI oscillator is automatically switched-on) */\r
+ CLK->ICKR |= CLK_ICKR_FHWU;\r
+ }\r
+ else /* FastHaltWakeup = DISABLE */\r
+ {\r
+ /* Reset FHWU bit */\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_FHWU);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enable or Disable the External High Speed oscillator (HSE).\r
+ * @param NewState new state of HSEEN, value accepted ENABLE, DISABLE.\r
+ * @retval None\r
+ */\r
+void CLK_HSECmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set HSEEN bit */\r
+ CLK->ECKR |= CLK_ECKR_HSEEN;\r
+ }\r
+ else\r
+ {\r
+ /* Reset HSEEN bit */\r
+ CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @param NewState new state of HSIEN, value accepted ENABLE, DISABLE.\r
+ * @retval None\r
+ */\r
+void CLK_HSICmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set HSIEN bit */\r
+ CLK->ICKR |= CLK_ICKR_HSIEN;\r
+ }\r
+ else\r
+ {\r
+ /* Reset HSIEN bit */\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @param NewState new state of LSIEN, value accepted ENABLE, DISABLE.\r
+ * @retval None\r
+ */\r
+void CLK_LSICmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set LSIEN bit */\r
+ CLK->ICKR |= CLK_ICKR_LSIEN;\r
+ }\r
+ else\r
+ {\r
+ /* Reset LSIEN bit */\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disablle the Configurable Clock Output (CCO).\r
+ * @param NewState : New state of CCEN bit (CCO register).\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void CLK_CCOCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set CCOEN bit */\r
+ CLK->CCOR |= CLK_CCOR_CCOEN;\r
+ }\r
+ else\r
+ {\r
+ /* Reset CCOEN bit */\r
+ CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOEN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Starts or Stops manually the clock switch execution.\r
+ * @par Full description:\r
+ * NewState parameter set the SWEN.\r
+ * @param NewState new state of SWEN, value accepted ENABLE, DISABLE.\r
+ * @retval None\r
+ */\r
+void CLK_ClockSwitchCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE )\r
+ {\r
+ /* Enable the Clock Switch */\r
+ CLK->SWCR |= CLK_SWCR_SWEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Clock Switch */\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the slow active halt wake up\r
+ * @param NewState: specifies the Slow Active Halt wake up state.\r
+ * can be set of the following values:\r
+ * - DISABLE: Slow Active Halt mode disabled;\r
+ * - ENABLE: Slow Active Halt mode enabled.\r
+ * @retval None\r
+ */\r
+void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set S_ACTHALT bit */\r
+ CLK->ICKR |= CLK_ICKR_SWUAH;\r
+ }\r
+ else\r
+ {\r
+ /* Reset S_ACTHALT bit */\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_SWUAH);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified peripheral CLK.\r
+ * @param CLK_Peripheral : This parameter specifies the peripheral clock to gate.\r
+ * This parameter can be any of the @ref CLK_Peripheral_TypeDef enumeration.\r
+ * @param NewState : New state of specified peripheral clock.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+ assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));\r
+\r
+ if (((uint8_t)CLK_Peripheral & (uint8_t)0x10) == 0x00)\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the peripheral Clock */\r
+ CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));\r
+ }\r
+ else\r
+ {\r
+ /* Disable the peripheral Clock */\r
+ CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the peripheral Clock */\r
+ CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));\r
+ }\r
+ else\r
+ {\r
+ /* Disable the peripheral Clock */\r
+ CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));\r
+ }\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief configures the Switch from one clock to another\r
+ * @param CLK_SwitchMode select the clock switch mode.\r
+ * It can be set of the values of @ref CLK_SwitchMode_TypeDef\r
+ * @param CLK_NewClock choice of the future clock.\r
+ * It can be set of the values of @ref CLK_Source_TypeDef\r
+ * @param NewState Enable or Disable the Clock Switch interrupt.\r
+ * @param CLK_CurrentClockState current clock to switch OFF or to keep ON.\r
+ * It can be set of the values of @ref CLK_CurrentClockState_TypeDef\r
+ * @retval ErrorStatus this shows the clock switch status (ERROR/SUCCESS).\r
+ */\r
+ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)\r
+{\r
+\r
+ CLK_Source_TypeDef clock_master;\r
+ uint16_t DownCounter = CLK_TIMEOUT;\r
+ ErrorStatus Swif = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));\r
+ assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(ITState));\r
+ assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));\r
+\r
+ /* Current clock master saving */\r
+ clock_master = (CLK_Source_TypeDef)CLK->CMSR;\r
+\r
+ /* Automatic switch mode management */\r
+ if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)\r
+ {\r
+\r
+ /* Enables Clock switch */\r
+ CLK->SWCR |= CLK_SWCR_SWEN;\r
+\r
+ /* Enables or Disables Switch interrupt */\r
+ if (ITState != DISABLE)\r
+ {\r
+ CLK->SWCR |= CLK_SWCR_SWIEN;\r
+ }\r
+ else\r
+ {\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);\r
+ }\r
+\r
+ /* Selection of the target clock source */\r
+ CLK->SWR = (uint8_t)CLK_NewClock;\r
+\r
+ while ((((CLK->SWCR & CLK_SWCR_SWBSY) != 0 )&& (DownCounter != 0)))\r
+ {\r
+ DownCounter--;\r
+ }\r
+\r
+ if (DownCounter != 0)\r
+ {\r
+ Swif = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ Swif = ERROR;\r
+ }\r
+\r
+ }\r
+ else /* CLK_SwitchMode == CLK_SWITCHMODE_MANUAL */\r
+ {\r
+\r
+ /* Enables or Disables Switch interrupt if required */\r
+ if (ITState != DISABLE)\r
+ {\r
+ CLK->SWCR |= CLK_SWCR_SWIEN;\r
+ }\r
+ else\r
+ {\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);\r
+ }\r
+\r
+ /* Selection of the target clock source */\r
+ CLK->SWR = (uint8_t)CLK_NewClock;\r
+\r
+ /* In manual mode, there is no risk to be stuck in a loop, value returned\r
+ is then always SUCCESS */\r
+ Swif = SUCCESS;\r
+\r
+ }\r
+\r
+ /* Switch OFF current clock if required */\r
+ if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))\r
+ {\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);\r
+ }\r
+ else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))\r
+ {\r
+ CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);\r
+ }\r
+ else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))\r
+ {\r
+ CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);\r
+ }\r
+\r
+ return(Swif);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the HSI clock dividers.\r
+ * @param HSIPrescaler : Specifies the HSI clock divider to apply.\r
+ * This parameter can be any of the @ref CLK_Prescaler_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));\r
+\r
+ /* Clear High speed internal clock prescaler */\r
+ CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);\r
+\r
+ /* Set High speed internal clock prescaler */\r
+ CLK->CKDIVR |= (uint8_t)HSIPrescaler;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Output the selected clock on a dedicated I/O pin.\r
+ * @param CLK_CCO : Specifies the clock source.\r
+ * This parameter can be any of the @ref CLK_Output_TypeDef enumeration.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register \n\r
+ * to be set as input with pull-up or push-pull output.\r
+ */\r
+void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));\r
+\r
+ /* Clears of the CCO type bits part */\r
+ CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOSEL);\r
+\r
+ /* Selects the source provided on cco_ck output */\r
+ CLK->CCOR |= (uint8_t)CLK_CCO;\r
+\r
+ /* Enable the clock output */\r
+ CLK->CCOR |= CLK_CCOR_CCOEN;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CLK interrupts.\r
+ * @param CLK_IT This parameter specifies the interrupt sources.\r
+ * It can be one of the values of @ref CLK_IT_TypeDef.\r
+ * @param NewState New state of the Interrupt.\r
+ * Value accepted ENABLE, DISABLE.\r
+ * @retval None\r
+ */\r
+void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+ assert_param(IS_CLK_IT_OK(CLK_IT));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ switch (CLK_IT)\r
+ {\r
+ case CLK_IT_SWIF: /* Enable the clock switch interrupt */\r
+ CLK->SWCR |= CLK_SWCR_SWIEN;\r
+ break;\r
+ case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */\r
+ CLK->CSSR |= CLK_CSSR_CSSDIE;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else /*(NewState == DISABLE)*/\r
+ {\r
+ switch (CLK_IT)\r
+ {\r
+ case CLK_IT_SWIF: /* Disable the clock switch interrupt */\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);\r
+ break;\r
+ case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */\r
+ CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the HSI and CPU clock dividers.\r
+ * @param ClockPrescaler Specifies the HSI or CPU clock divider to apply.\r
+ * @retval None\r
+ */\r
+void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_PRESCALER_OK(CLK_Prescaler));\r
+\r
+ if (((uint8_t)CLK_Prescaler & (uint8_t)0x80) == 0x00) /* Bit7 = 0 means HSI divider */\r
+ {\r
+ CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);\r
+ CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_HSIDIV);\r
+ }\r
+ else /* Bit7 = 1 means CPU divider */\r
+ {\r
+ CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_CPUDIV);\r
+ CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_CPUDIV);\r
+ }\r
+\r
+}\r
+/**\r
+ * @brief Configures the SWIM clock frequency on the fly.\r
+ * @param CLK_SWIMDivider Specifies the SWIM clock divider to apply.\r
+ * can be one of the value of @ref CLK_SWIMDivider_TypeDef\r
+ * @retval None\r
+ */\r
+void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));\r
+\r
+ if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)\r
+ {\r
+ /* SWIM clock is not divided by 2 */\r
+ CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;\r
+ }\r
+ else /* CLK_SWIMDivider == CLK_SWIMDIVIDER_2 */\r
+ {\r
+ /* SWIM clock is divided by 2 */\r
+ CLK->SWIMCCR &= (uint8_t)(~CLK_SWIMCCR_SWIMDIV);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Enables the Clock Security System.\r
+ * @par Full description:\r
+ * once CSS is enabled it cannot be disabled until the next reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CLK_ClockSecuritySystemEnable(void)\r
+{\r
+ /* Set CSSEN bit */\r
+ CLK->CSSR |= CLK_CSSR_CSSEN;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval Clock source used.\r
+ * can be one of the values of @ref CLK_Source_TypeDef\r
+ */\r
+CLK_Source_TypeDef CLK_GetSYSCLKSource(void)\r
+{\r
+ return((CLK_Source_TypeDef)CLK->CMSR);\r
+}\r
+\r
+/**\r
+ * @brief This function returns the frequencies of different on chip clocks.\r
+ * @param None\r
+ * @retval the master clock frequency\r
+ */\r
+uint32_t CLK_GetClockFreq(void)\r
+{\r
+\r
+ uint32_t clockfrequency = 0;\r
+ CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;\r
+ uint8_t tmp = 0, presc = 0;\r
+\r
+ /* Get CLK source. */\r
+ clocksource = (CLK_Source_TypeDef)CLK->CMSR;\r
+\r
+ if (clocksource == CLK_SOURCE_HSI)\r
+ {\r
+ tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);\r
+ tmp = (uint8_t)(tmp >> 3);\r
+ presc = HSIDivFactor[tmp];\r
+ clockfrequency = HSI_VALUE / presc;\r
+ }\r
+ else if ( clocksource == CLK_SOURCE_LSI)\r
+ {\r
+ clockfrequency = LSI_VALUE;\r
+ }\r
+ else\r
+ {\r
+ clockfrequency = HSE_VALUE;\r
+ }\r
+\r
+ return((uint32_t)clockfrequency);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @par Full description:\r
+ * @param CLK_HSICalibrationValue calibration trimming value.\r
+ * can be one of the values of @ref CLK_HSITrimValue_TypeDef\r
+ * @retval None\r
+ */\r
+void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));\r
+\r
+ /* Store the new value */\r
+ CLK->HSITRIMR = (uint8_t)( (uint8_t)(CLK->HSITRIMR & (uint8_t)(~CLK_HSITRIMR_HSITRIM))|((uint8_t)CLK_HSICalibrationValue));\r
+\r
+}\r
+\r
+/**\r
+ * @brief Reset the SWBSY flag (SWICR Reister)\r
+ * @par Full description:\r
+ * This function reset SWBSY flag in order to reset clock switch operations (target\r
+ * oscillator is broken, stabilization is longing too much, etc.). If at the same time \n\r
+ * software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CLK_SYSCLKEmergencyClear(void)\r
+{\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWBSY);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CLK flag is set or not.\r
+ * @par Full description:\r
+ * @param CLK_FLAG Flag to check.\r
+ * can be one of the values of @ref CLK_Flag_TypeDef\r
+ * @retval FlagStatus, status of the checked flag\r
+ */\r
+FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)\r
+{\r
+\r
+ uint16_t statusreg = 0;\r
+ uint8_t tmpreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_FLAG_OK(CLK_FLAG));\r
+\r
+ /* Get the CLK register index */\r
+ statusreg = (uint16_t)((uint16_t)CLK_FLAG & (uint16_t)0xFF00);\r
+\r
+\r
+ if (statusreg == 0x0100) /* The flag to check is in ICKRregister */\r
+ {\r
+ tmpreg = CLK->ICKR;\r
+ }\r
+ else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */\r
+ {\r
+ tmpreg = CLK->ECKR;\r
+ }\r
+ else if (statusreg == 0x0300) /* The flag to check is in SWIC register */\r
+ {\r
+ tmpreg = CLK->SWCR;\r
+ }\r
+ else if (statusreg == 0x0400) /* The flag to check is in CSS register */\r
+ {\r
+ tmpreg = CLK->CSSR;\r
+ }\r
+ else /* The flag to check is in CCO register */\r
+ {\r
+ tmpreg = CLK->CCOR;\r
+ }\r
+\r
+ if ((tmpreg & (uint8_t)CLK_FLAG) != (uint8_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return((FlagStatus)bitstatus);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CLK interrupt has is enabled or not.\r
+ * @param CLK_IT specifies the CLK interrupt.\r
+ * can be one of the values of @ref CLK_IT_TypeDef\r
+ * @retval ITStatus, new state of CLK_IT (SET or RESET).\r
+ */\r
+ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)\r
+{\r
+\r
+ ITStatus bitstatus = RESET;\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_IT_OK(CLK_IT));\r
+\r
+ if (CLK_IT == CLK_IT_SWIF)\r
+ {\r
+ /* Check the status of the clock switch interrupt */\r
+ if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else /* CLK_IT == CLK_IT_CSSDIE */\r
+ {\r
+ /* Check the status of the security system detection interrupt */\r
+ if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+\r
+ /* Return the CLK_IT status */\r
+ return bitstatus;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Clears the CLK\92s interrupt pending bits.\r
+ * @param CLK_IT specifies the interrupt pending bits.\r
+ * can be one of the values of @ref CLK_IT_TypeDef\r
+ * @retval None\r
+ */\r
+void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)\r
+{\r
+\r
+ /* check the parameters */\r
+ assert_param(IS_CLK_IT_OK(CLK_IT));\r
+\r
+ if (CLK_IT == (uint8_t)CLK_IT_CSSD)\r
+ {\r
+ /* Clear the status of the security system detection interrupt */\r
+ CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSD);\r
+ }\r
+ else /* CLK_PendingBit == (uint8_t)CLK_IT_SWIF */\r
+ {\r
+ /* Clear the status of the clock switch interrupt */\r
+ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);\r
+ }\r
+\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_exti.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the EXTI peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_exti.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup EXTI_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the external interrupt control registers to their default reset value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->CR1 = EXTI_CR1_RESET_VALUE;\r
+ EXTI->CR2 = EXTI_CR2_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Set the external interrupt sensitivity of the selected port.\r
+ * @warning\r
+ * - The modification of external interrupt sensitivity is only possible when the interrupts are disabled.\r
+ * - The normal behavior is to disable the interrupts before calling this function, and re-enable them after.\r
+ * @param Port The port number to access.\r
+ * @param SensitivityValue The external interrupt sensitivity value to set.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Global interrupts must be disabled before calling this function.\r
+ */\r
+void EXTI_SetExtIntSensitivity(EXTI_Port_TypeDef Port, EXTI_Sensitivity_TypeDef SensitivityValue)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_EXTI_PORT_OK(Port));\r
+ assert_param(IS_EXTI_SENSITIVITY_OK(SensitivityValue));\r
+\r
+ /* Set external interrupt sensitivity */\r
+ switch (Port)\r
+ {\r
+ case EXTI_PORT_GPIOA:\r
+ EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PAIS);\r
+ EXTI->CR1 |= (uint8_t)(SensitivityValue);\r
+ break;\r
+ case EXTI_PORT_GPIOB:\r
+ EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PBIS);\r
+ EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 2);\r
+ break;\r
+ case EXTI_PORT_GPIOC:\r
+ EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PCIS);\r
+ EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 4);\r
+ break;\r
+ case EXTI_PORT_GPIOD:\r
+ EXTI->CR1 &= (uint8_t)(~EXTI_CR1_PDIS);\r
+ EXTI->CR1 |= (uint8_t)((uint8_t)(SensitivityValue) << 6);\r
+ break;\r
+ case EXTI_PORT_GPIOE:\r
+ EXTI->CR2 &= (uint8_t)(~EXTI_CR2_PEIS);\r
+ EXTI->CR2 |= (uint8_t)(SensitivityValue);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the TLI interrupt sensitivity.\r
+ * @param SensitivityValue The TLI interrupt sensitivity value.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * Global interrupts must be disabled before calling this function.\r
+ */\r
+void EXTI_SetTLISensitivity(EXTI_TLISensitivity_TypeDef SensitivityValue)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_EXTI_TLISENSITIVITY_OK(SensitivityValue));\r
+\r
+ /* Set TLI interrupt sensitivity */\r
+ EXTI->CR2 &= (uint8_t)(~EXTI_CR2_TLIS);\r
+ EXTI->CR2 |= (uint8_t)(SensitivityValue);\r
+}\r
+\r
+/**\r
+ * @brief Get the external interrupt sensitivity of the selected port.\r
+ * @param Port The port number to access.\r
+ * @retval EXTI_Sensitivity_TypeDef The external interrupt sensitivity of the selected port.\r
+ */\r
+EXTI_Sensitivity_TypeDef EXTI_GetExtIntSensitivity(EXTI_Port_TypeDef Port)\r
+{\r
+ uint8_t value = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_EXTI_PORT_OK(Port));\r
+\r
+ switch (Port)\r
+ {\r
+ case EXTI_PORT_GPIOA:\r
+ value = (uint8_t)(EXTI->CR1 & EXTI_CR1_PAIS);\r
+ break;\r
+ case EXTI_PORT_GPIOB:\r
+ value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PBIS) >> 2);\r
+ break;\r
+ case EXTI_PORT_GPIOC:\r
+ value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PCIS) >> 4);\r
+ break;\r
+ case EXTI_PORT_GPIOD:\r
+ value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_PDIS) >> 6);\r
+ break;\r
+ case EXTI_PORT_GPIOE:\r
+ value = (uint8_t)(EXTI->CR2 & EXTI_CR2_PEIS);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return((EXTI_Sensitivity_TypeDef)value);\r
+}\r
+\r
+/**\r
+ * @brief Get the TLI interrupt sensitivity.\r
+ * @param None\r
+ * @retval EXTI_TLISensitivity_TypeDef The TLI interrupt sensitivity read.\r
+ */\r
+EXTI_TLISensitivity_TypeDef EXTI_GetTLISensitivity(void)\r
+{\r
+\r
+ uint8_t value = 0;\r
+\r
+ /* Get TLI interrupt sensitivity */\r
+ value = (uint8_t)(EXTI->CR2 & EXTI_CR2_TLIS);\r
+\r
+ return((EXTI_TLISensitivity_TypeDef)value);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_flash.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the FLASH peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_flash.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/**\r
+@code\r
+ This driver provides functions to configure and program the Flash memory of all\r
+ STM8S devices.\r
+\r
+ It includes as well functions that can be either executed from RAM or not, and\r
+ other functions that must be executed from RAM otherwise useless.\r
+\r
+ The table below lists the functions that can be executed from RAM.\r
+\r
+ +--------------------------------------------------------------------------------|\r
+ | Functions prototypes | RAM execution | Comments |\r
+ ---------------------------------------------------------------------------------|\r
+ | | Mandatory in case of block | Can be executed |\r
+ | FLASH_WaitForLastOperation | Operation: | from Flash in case |\r
+ | | - Block programming | of byte and word |\r
+ | | - Block erase | Operations |\r
+ |--------------------------------------------------------------------------------|\r
+ | FLASH_ProgramBlock | Exclusively | useless from Flash |\r
+ |--------------------------------------------------------------------------------|\r
+ | FLASH_EraseBlock | Exclusively | useless from Flash |\r
+ |--------------------------------------------------------------------------------|\r
+\r
+ To be able to execute functions from RAM several steps have to be followed.\r
+ These steps may differ from one toolchain to another.\r
+ A detailed description is available below within this driver.\r
+ You can also refer to the FLASH examples provided within the\r
+ STM8S_StdPeriph_Lib package.\r
+\r
+@endcode\r
+*/\r
+\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define FLASH_CLEAR_BYTE ((uint8_t)0x00)\r
+#define FLASH_SET_BYTE ((uint8_t)0xFF)\r
+#define OPERATION_TIMEOUT ((uint32_t)0xFFFFF)\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+\r
+/** @addtogroup FLASH_Public_functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Unlocks the program or data EEPROM memory\r
+ * @param FLASH_MemType : Memory type to unlock\r
+ * This parameter can be a value of @ref FLASH_MemType_TypeDef\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));\r
+\r
+ /* Unlock program memory */\r
+ if (FLASH_MemType == FLASH_MEMTYPE_PROG)\r
+ {\r
+ FLASH->PUKR = FLASH_RASS_KEY1;\r
+ FLASH->PUKR = FLASH_RASS_KEY2;\r
+ }\r
+ /* Unlock data memory */\r
+ else\r
+ {\r
+ FLASH->DUKR = FLASH_RASS_KEY2; /* Warning: keys are reversed on data memory !!! */\r
+ FLASH->DUKR = FLASH_RASS_KEY1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Locks the program or data EEPROM memory\r
+ * @param FLASH_MemType : Memory type\r
+ * This parameter can be a value of @ref FLASH_MemType_TypeDef\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));\r
+\r
+ /* Lock memory */\r
+ FLASH->IAPSR &= (uint8_t)FLASH_MemType;\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FLASH registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_DeInit(void)\r
+{\r
+ FLASH->CR1 = FLASH_CR1_RESET_VALUE;\r
+ FLASH->CR2 = FLASH_CR2_RESET_VALUE;\r
+ FLASH->NCR2 = FLASH_NCR2_RESET_VALUE;\r
+ FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_DUL);\r
+ FLASH->IAPSR &= (uint8_t)(~FLASH_IAPSR_PUL);\r
+ (void) FLASH->IAPSR; /* Reading of this register causes the clearing of status flags */\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the Flash interrupt mode\r
+ * @param NewState : The new state of the flash interrupt mode\r
+ * This parameter can be a value of @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void FLASH_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ FLASH->CR1 |= FLASH_CR1_IE; /* Enables the interrupt sources */\r
+ }\r
+ else\r
+ {\r
+ FLASH->CR1 &= (uint8_t)(~FLASH_CR1_IE); /* Disables the interrupt sources */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Erases one byte in the program or data EEPROM memory\r
+ * @note PointerAttr define is declared in the stm8s.h file to select if \r
+ * the pointer will be declared as near (2 bytes) or far (3 bytes).\r
+ * @param Address : Address of the byte to erase\r
+ * @retval None\r
+ */\r
+void FLASH_EraseByte(uint32_t Address)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_FLASH_ADDRESS_OK(Address));\r
+ \r
+ /* Erase byte */\r
+ *(PointerAttr uint8_t*) (uint16_t)Address = FLASH_CLEAR_BYTE; \r
+\r
+}\r
+\r
+/**\r
+ * @brief Programs one byte in program or data EEPROM memory\r
+ * @note PointerAttr define is declared in the stm8s.h file to select if \r
+ * the pointer will be declared as near (2 bytes) or far (3 bytes).\r
+ * @param Address : Address where the byte will be programmed\r
+ * @param Data : Value to be programmed\r
+ * @retval None\r
+ */\r
+void FLASH_ProgramByte(uint32_t Address, uint8_t Data)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_FLASH_ADDRESS_OK(Address));\r
+ *(PointerAttr uint8_t*) (uint16_t)Address = Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads any byte from flash memory\r
+ * @note PointerAttr define is declared in the stm8s.h file to select if \r
+ * the pointer will be declared as near (2 bytes) or far (3 bytes).\r
+ * @param Address : Address to read\r
+ * @retval Value of the byte\r
+ */\r
+uint8_t FLASH_ReadByte(uint32_t Address)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_FLASH_ADDRESS_OK(Address));\r
+ \r
+ /* Read byte */\r
+ return(*(PointerAttr uint8_t *) (uint16_t)Address); \r
+\r
+}\r
+/**\r
+ * @brief Programs one word (4 bytes) in program or data EEPROM memory\r
+ * @note PointerAttr define is declared in the stm8s.h file to select if \r
+ * the pointer will be declared as near (2 bytes) or far (3 bytes).\r
+ * @param Address : The address where the data will be programmed\r
+ * @param Data : Value to be programmed\r
+ * @retval None\r
+ */\r
+void FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_FLASH_ADDRESS_OK(Address));\r
+\r
+ /* Enable Word Write Once */\r
+ FLASH->CR2 |= FLASH_CR2_WPRG;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NWPRG);\r
+\r
+ /* Write one byte - from lowest address*/\r
+ *((PointerAttr uint8_t*)(uint16_t)Address) = *((uint8_t*)(&Data));\r
+ /* Write one byte*/\r
+ *(((PointerAttr uint8_t*)(uint16_t)Address) + 1) = *((uint8_t*)(&Data)+1); \r
+ /* Write one byte*/ \r
+ *(((PointerAttr uint8_t*)(uint16_t)Address) + 2) = *((uint8_t*)(&Data)+2); \r
+ /* Write one byte - from higher address*/\r
+ *(((PointerAttr uint8_t*)(uint16_t)Address) + 3) = *((uint8_t*)(&Data)+3); \r
+}\r
+\r
+/**\r
+ * @brief Programs option byte\r
+ * @param Address : option byte address to program\r
+ * @param Data : Value to write\r
+ * @retval None\r
+ */\r
+void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));\r
+\r
+ /* Enable write access to option bytes */\r
+ FLASH->CR2 |= FLASH_CR2_OPT;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);\r
+\r
+ /* check if the option byte to program is ROP*/\r
+ if (Address == 0x4800)\r
+ {\r
+ /* Program option byte*/\r
+ *((NEAR uint8_t*)Address) = Data;\r
+ }\r
+ else\r
+ {\r
+ /* Program option byte and his complement */\r
+ *((NEAR uint8_t*)Address) = Data;\r
+ *((NEAR uint8_t*)((uint16_t)(Address + 1))) = (uint8_t)(~Data);\r
+ }\r
+ FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);\r
+\r
+ /* Disable write access to option bytes */\r
+ FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);\r
+ FLASH->NCR2 |= FLASH_NCR2_NOPT;\r
+}\r
+\r
+/**\r
+ * @brief Erases option byte\r
+ * @param Address : Option byte address to erase\r
+ * @retval None\r
+ */\r
+void FLASH_EraseOptionByte(uint16_t Address)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));\r
+\r
+ /* Enable write access to option bytes */\r
+ FLASH->CR2 |= FLASH_CR2_OPT;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NOPT);\r
+\r
+ /* check if the option byte to erase is ROP */\r
+ if (Address == 0x4800)\r
+ {\r
+ /* Erase option byte */\r
+ *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;\r
+ }\r
+ else\r
+ {\r
+ /* Erase option byte and his complement */\r
+ *((NEAR uint8_t*)Address) = FLASH_CLEAR_BYTE;\r
+ *((NEAR uint8_t*)((uint16_t)(Address + (uint16_t)1 ))) = FLASH_SET_BYTE;\r
+ }\r
+ FLASH_WaitForLastOperation(FLASH_MEMTYPE_PROG);\r
+\r
+ /* Disable write access to option bytes */\r
+ FLASH->CR2 &= (uint8_t)(~FLASH_CR2_OPT);\r
+ FLASH->NCR2 |= FLASH_NCR2_NOPT;\r
+}\r
+/**\r
+ * @brief Reads one option byte\r
+ * @param Address option byte address to read.\r
+ * @retval Option byte read value + its complement\r
+ */\r
+uint16_t FLASH_ReadOptionByte(uint16_t Address)\r
+{\r
+ uint8_t value_optbyte, value_optbyte_complement = 0;\r
+ uint16_t res_value = 0;\r
+\r
+ /* Check parameter */\r
+ assert_param(IS_OPTION_BYTE_ADDRESS_OK(Address));\r
+\r
+\r
+ value_optbyte = *((NEAR uint8_t*)Address); /* Read option byte */\r
+ value_optbyte_complement = *(((NEAR uint8_t*)Address) + 1); /* Read option byte complement */\r
+\r
+ /* Read-out protection option byte */\r
+ if (Address == 0x4800) \r
+ {\r
+ res_value = value_optbyte;\r
+ }\r
+ else\r
+ {\r
+ if (value_optbyte == (uint8_t)(~value_optbyte_complement))\r
+ {\r
+ res_value = (uint16_t)((uint16_t)value_optbyte << 8);\r
+ res_value = res_value | (uint16_t)value_optbyte_complement;\r
+ }\r
+ else\r
+ {\r
+ res_value = FLASH_OPTIONBYTE_ERROR;\r
+ }\r
+ }\r
+ return(res_value);\r
+}\r
+\r
+/**\r
+ * @brief Select the Flash behaviour in low power mode\r
+ * @param FLASH_LPMode Low power mode selection\r
+ * This parameter can be any of the @ref FLASH_LPMode_TypeDef values.\r
+ * @retval None\r
+ */\r
+void FLASH_SetLowPowerMode(FLASH_LPMode_TypeDef FLASH_LPMode)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_FLASH_LOW_POWER_MODE_OK(FLASH_LPMode));\r
+\r
+ /* Clears the two bits */\r
+ FLASH->CR1 &= (uint8_t)(~(FLASH_CR1_HALT | FLASH_CR1_AHALT)); \r
+ \r
+ /* Sets the new mode */\r
+ FLASH->CR1 |= (uint8_t)FLASH_LPMode; \r
+}\r
+\r
+/**\r
+ * @brief Sets the fixed programming time\r
+ * @param FLASH_ProgTime Indicates the programming time to be fixed\r
+ * This parameter can be any of the @ref FLASH_ProgramTime_TypeDef values.\r
+ * @retval None\r
+ */\r
+void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime)\r
+{\r
+ /* Check parameter */\r
+ assert_param(IS_FLASH_PROGRAM_TIME_OK(FLASH_ProgTime));\r
+\r
+ FLASH->CR1 &= (uint8_t)(~FLASH_CR1_FIX);\r
+ FLASH->CR1 |= (uint8_t)FLASH_ProgTime;\r
+}\r
+\r
+/**\r
+ * @brief Returns the Flash behaviour type in low power mode\r
+ * @param None\r
+ * @retval FLASH_LPMode_TypeDef Flash behaviour type in low power mode\r
+ */\r
+FLASH_LPMode_TypeDef FLASH_GetLowPowerMode(void)\r
+{\r
+ return((FLASH_LPMode_TypeDef)(FLASH->CR1 & (uint8_t)(FLASH_CR1_HALT | FLASH_CR1_AHALT)));\r
+}\r
+\r
+/**\r
+ * @brief Returns the fixed programming time\r
+ * @param None\r
+ * @retval FLASH_ProgramTime_TypeDef Fixed programming time value\r
+ */\r
+FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void)\r
+{\r
+ return((FLASH_ProgramTime_TypeDef)(FLASH->CR1 & FLASH_CR1_FIX));\r
+}\r
+\r
+/**\r
+ * @brief Returns the Boot memory size in bytes\r
+ * @param None\r
+ * @retval Boot memory size in bytes\r
+ */\r
+uint32_t FLASH_GetBootSize(void)\r
+{\r
+ uint32_t temp = 0;\r
+\r
+ /* Calculates the number of bytes */\r
+ temp = (uint32_t)((uint32_t)FLASH->FPR * (uint32_t)512);\r
+\r
+ /* Correction because size of 127.5 kb doesn't exist */\r
+ if (FLASH->FPR == 0xFF)\r
+ {\r
+ temp += 512;\r
+ }\r
+\r
+ /* Return value */\r
+ return(temp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI flag is set or not.\r
+ * @param FLASH_FLAG : Specifies the flag to check.\r
+ * This parameter can be any of the @ref FLASH_Flag_TypeDef enumeration.\r
+ * @retval FlagStatus : Indicates the state of FLASH_FLAG.\r
+ * This parameter can be any of the @ref FlagStatus enumeration.\r
+ * @note This function can clear the EOP, WR_PG_DIS flags in the IAPSR register.\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(FLASH_Flag_TypeDef FLASH_FLAG)\r
+{\r
+ FlagStatus status = RESET;\r
+ /* Check parameters */\r
+ assert_param(IS_FLASH_FLAGS_OK(FLASH_FLAG));\r
+\r
+ /* Check the status of the specified FLASH flag */\r
+ if ((FLASH->IAPSR & (uint8_t)FLASH_FLAG) != (uint8_t)RESET)\r
+ {\r
+ status = SET; /* FLASH_FLAG is set */\r
+ }\r
+ else\r
+ {\r
+ status = RESET; /* FLASH_FLAG is reset*/\r
+ }\r
+\r
+ /* Return the FLASH_FLAG status */\r
+ return status;\r
+}\r
+\r
+/**\r
+@code\r
+ All the functions defined below must be executed from RAM exclusively, except\r
+ for the FLASH_WaitForLastOperation function which can be executed from Flash.\r
+\r
+ Steps of the execution from RAM differs from one toolchain to another:\r
+ - For Cosmic Compiler:\r
+ 1- Define a segment FLASH_CODE by the mean of " #pragma section (FLASH_CODE)".\r
+ This segment is defined in the stm8s_flash.c file.\r
+ 2- Uncomment the "#define RAM_EXECUTION (1)" line in the stm8s.h file,\r
+ or define it in Cosmic compiler preprocessor to enable the FLASH_CODE segment\r
+ definition.\r
+ 3- In STVD Select Project\Settings\Linker\Category "input" and in the RAM section\r
+ add the FLASH_CODE segment with "-ic" options.\r
+ 4- In main.c file call the _fctcpy() function with first segment character as \r
+ parameter "_fctcpy('F');" to load the declared moveable code segment\r
+ (FLASH_CODE) in RAM before execution.\r
+ 5- By default the _fctcpy function is packaged in the Cosmic machine library,\r
+ so the function prototype "int _fctcopy(char name);" must be added in main.c\r
+ file.\r
+\r
+ - For Raisonance Compiler\r
+ 1- Use the inram keyword in the function declaration to specify that it can be\r
+ executed from RAM.\r
+ This is done within the stm8s_flash.c file, and it's conditioned by \r
+ RAM_EXECUTION definition.\r
+ 2- Uncomment the "#define RAM_EXECUTION (1)" line in the stm8s.h file, or \r
+ define it in Raisonance compiler preprocessor to enable the access for the \r
+ inram functions.\r
+ 3- An inram function code is copied from Flash to RAM by the C startup code. \r
+ In some applications, the RAM area where the code was initially stored may be\r
+ erased or corrupted, so it may be desirable to perform the copy again. \r
+ Depending on the application memory model, the memcpy() or fmemcpy() functions\r
+ should be used to perform the copy.\r
+ \95 In case your project uses the SMALL memory model (code smaller than 64K),\r
+ memcpy()function is recommended to perform the copy\r
+ \95 In case your project uses the LARGE memory model, functions can be \r
+ everywhenre in the 24-bits address space (not limited to the first 64KB of\r
+ code), In this case, the use of memcpy() function will not be appropriate,\r
+ you need to use the specific fmemcpy() function (which copies objects with\r
+ 24-bit addresses).\r
+ - The linker automatically defines 2 symbols for each inram function:\r
+ \95 __address__functionname is a symbol that holds the Flash address \r
+ where the given function code is stored.\r
+ \95 __size__functionname is a symbol that holds the function size in bytes.\r
+ And we already have the function address (which is itself a pointer)\r
+ 4- In main.c file these two steps should be performed for each inram function:\r
+ \95 Import the "__address__functionname" and "__size__functionname" symbols\r
+ as global variables:\r
+ extern int __address__functionname; // Symbol holding the flash address\r
+ extern int __size__functionname; // Symbol holding the function size\r
+ \95 In case of SMALL memory model use, Call the memcpy() function to copy the\r
+ inram function to the RAM destination address:\r
+ memcpy(functionname, // RAM destination address\r
+ (void*)&__address__functionname, // Flash source address\r
+ (int)&__size__functionname); // Code size of the function\r
+ \95 In case of LARGE memory model use, call the fmemcpy() function to copy \r
+ the inram function to the RAM destination address:\r
+ memcpy(functionname, // RAM destination address\r
+ (void @far*)&__address__functionname, // Flash source address\r
+ (int)&__size__functionname); // Code size of the function\r
+\r
+ - For IAR Compiler:\r
+ 1- Use the __ramfunc keyword in the function declaration to specify that it \r
+ can be executed from RAM..\r
+ This is done within the stm8s_flash.c file, and it's conditioned by \r
+ RAM_EXECUTION definition.\r
+ 2- Uncomment the "#define RAM_EXECUTION (1)" line in the stm8s.h file, or \r
+ define it in IAR compiler preprocessor to enable the access for the \r
+ __ramfunc functions.\r
+ \r
+ The FLASH examples given within the STM8S_StdPeriph_Lib package, details all \r
+ the steps described above.\r
+\r
+@endcode\r
+*/\r
+\r
+/**\r
+ * @brief\r
+ *******************************************************************************\r
+ * Execution from RAM enable\r
+ *******************************************************************************\r
+ *\r
+ * To enable execution from RAM you can either uncomment the following define \r
+ * in the stm8s.h file or define it in your toolchain compiler preprocessor\r
+ * - #define RAM_EXECUTION (1) \r
+ */\r
+ \r
+#if defined (_COSMIC_) && defined (RAM_EXECUTION)\r
+ #pragma section (FLASH_CODE)\r
+#endif /* _COSMIC_ && RAM_EXECUTION */\r
+/**\r
+ * @brief Wait for a Flash operation to complete.\r
+ * @note The call and execution of this function must be done from RAM in case\r
+ * of Block operation, otherwise it can be executed from Flash\r
+ * @param FLASH_MemType : Memory type\r
+ * This parameter can be a value of @ref FLASH_MemType_TypeDef\r
+ * @retval FLASH status\r
+ */\r
+IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType)) \r
+{\r
+ uint8_t flagstatus = 0x00;\r
+ uint32_t timeout = OPERATION_TIMEOUT;\r
+ \r
+ /* Wait until operation completion or write protection page occurred */\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined(STM8AF52Ax) || defined(STM8AF62Ax) || defined(STM8AF626x) \r
+ if (FLASH_MemType == FLASH_MEMTYPE_PROG)\r
+ {\r
+ while ((flagstatus == 0x00) && (timeout != 0x00))\r
+ {\r
+ flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_EOP |\r
+ FLASH_IAPSR_WR_PG_DIS));\r
+ timeout--;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ while ((flagstatus == 0x00) && (timeout != 0x00))\r
+ {\r
+ flagstatus = (uint8_t)(FLASH->IAPSR & (uint8_t)(FLASH_IAPSR_HVOFF |\r
+ FLASH_IAPSR_WR_PG_DIS));\r
+ timeout--;\r
+ }\r
+ }\r
+#else /*STM8S103, STM8S903*/\r
+ while ((flagstatus == 0x00) && (timeout != 0x00))\r
+ {\r
+ flagstatus = (uint8_t)(FLASH->IAPSR & (FLASH_IAPSR_EOP | FLASH_IAPSR_WR_PG_DIS));\r
+ timeout--;\r
+ }\r
+\r
+#endif /* STM8S208, STM8S207, STM8S105, STM8AF52Ax, STM8AF62Ax, STM8AF262x */\r
+ \r
+ if (timeout == 0x00 )\r
+ {\r
+ flagstatus = FLASH_STATUS_TIMEOUT;\r
+ }\r
+\r
+ return((FLASH_Status_TypeDef)flagstatus);\r
+}\r
+\r
+/**\r
+ * @brief Erases a block in the program or data memory.\r
+ * @note This function should be called and executed from RAM.\r
+ * @param FLASH_MemType : The type of memory to erase\r
+ * @param BlockNum : Indicates the block number to erase\r
+ * @retval None.\r
+ */\r
+IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType))\r
+{\r
+ uint32_t startaddress = 0;\r
+ \r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined (STM8S903) || defined (STM8AF626x)\r
+ uint32_t PointerAttr *pwFlash;\r
+#elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax) \r
+ uint8_t PointerAttr *pwFlash;\r
+#endif\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));\r
+ if (FLASH_MemType == FLASH_MEMTYPE_PROG)\r
+ {\r
+ assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));\r
+ startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));\r
+ startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;\r
+ }\r
+\r
+ /* Point to the first block address */\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || defined (STM8AF52Ax)\r
+ pwFlash = (PointerAttr uint8_t *)(uint32_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));\r
+#elif defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined (STM8S903) || defined (STM8AF626x)\r
+ pwFlash = (PointerAttr uint32_t *)(uint16_t)(startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE));\r
+#endif /* STM8S208, STM8S207 */\r
+\r
+ /* Enable erase block mode */\r
+ FLASH->CR2 |= FLASH_CR2_ERASE;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NERASE);\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined (STM8S903) || defined (STM8AF626x)\r
+ *pwFlash = (uint32_t)0;\r
+#elif defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined (STM8AF62Ax) || \\r
+ defined (STM8AF52Ax)\r
+ *pwFlash = (uint8_t)0;\r
+ *(pwFlash + 1) = (uint8_t)0;\r
+ *(pwFlash + 2) = (uint8_t)0;\r
+ *(pwFlash + 3) = (uint8_t)0; \r
+#endif\r
+}\r
+\r
+/**\r
+ * @brief Programs a memory block\r
+ * @note This function should be called and executed from RAM.\r
+ * @param FLASH_MemType : The type of memory to program\r
+ * @param BlockNum : The block number\r
+ * @param FLASH_ProgMode : The programming mode.\r
+ * @param Buffer : Pointer to buffer containing source data.\r
+ * @retval None.\r
+ */\r
+IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType, \r
+ FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer))\r
+{\r
+ uint16_t Count = 0;\r
+ uint32_t startaddress = 0;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_MEMORY_TYPE_OK(FLASH_MemType));\r
+ assert_param(IS_FLASH_PROGRAM_MODE_OK(FLASH_ProgMode));\r
+ if (FLASH_MemType == FLASH_MEMTYPE_PROG)\r
+ {\r
+ assert_param(IS_FLASH_PROG_BLOCK_NUMBER_OK(BlockNum));\r
+ startaddress = FLASH_PROG_START_PHYSICAL_ADDRESS;\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_FLASH_DATA_BLOCK_NUMBER_OK(BlockNum));\r
+ startaddress = FLASH_DATA_START_PHYSICAL_ADDRESS;\r
+ }\r
+\r
+ /* Point to the first block address */\r
+ startaddress = startaddress + ((uint32_t)BlockNum * FLASH_BLOCK_SIZE);\r
+\r
+ /* Selection of Standard or Fast programming mode */\r
+ if (FLASH_ProgMode == FLASH_PROGRAMMODE_STANDARD)\r
+ {\r
+ /* Standard programming mode */ /*No need in standard mode */\r
+ FLASH->CR2 |= FLASH_CR2_PRG;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NPRG);\r
+ }\r
+ else\r
+ {\r
+ /* Fast programming mode */\r
+ FLASH->CR2 |= FLASH_CR2_FPRG;\r
+ FLASH->NCR2 &= (uint8_t)(~FLASH_NCR2_NFPRG);\r
+ }\r
+\r
+ /* Copy data bytes from RAM to FLASH memory */\r
+ for (Count = 0; Count < FLASH_BLOCK_SIZE; Count++)\r
+ {\r
+#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)\r
+ *((PointerAttr uint8_t*) (uint16_t)startaddress + Count) = ((uint8_t)(Buffer[Count]));\r
+#elif defined(STM8S103) || defined(STM8S003) || defined (STM8S903)\r
+ *((PointerAttr uint8_t*) (uint16_t)startaddress + Count) = ((uint8_t)(Buffer[Count]));\r
+#endif \r
+ }\r
+}\r
+\r
+#if defined (_COSMIC_) && defined (RAM_EXECUTION)\r
+ /* End of FLASH_CODE section */\r
+ #pragma section ()\r
+#endif /* _COSMIC_ && RAM_EXECUTION */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the GPIO peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_gpio.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/**\r
+ * @addtogroup GPIO_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: Select the GPIO peripheral number (x = A to I).\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */\r
+ GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */\r
+ GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */\r
+ GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx according to the specified parameters.\r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param GPIO_Pin : This parameter contains the pin number, it can be any value\r
+ * of the @ref GPIO_Pin_TypeDef enumeration.\r
+ * @param GPIO_Mode : This parameter can be a value of the\r
+ * @Ref GPIO_Mode_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)\r
+{\r
+ /*----------------------*/\r
+ /* Check the parameters */\r
+ /*----------------------*/\r
+\r
+ assert_param(IS_GPIO_MODE_OK(GPIO_Mode));\r
+ assert_param(IS_GPIO_PIN_OK(GPIO_Pin));\r
+ \r
+ /* Reset corresponding bit to GPIO_Pin in CR2 register */\r
+ GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));\r
+\r
+ /*-----------------------------*/\r
+ /* Input/Output mode selection */\r
+ /*-----------------------------*/\r
+\r
+ if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */\r
+ {\r
+ if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */\r
+ {\r
+ GPIOx->ODR |= (uint8_t)GPIO_Pin;\r
+ } \r
+ else /* Low level */\r
+ {\r
+ GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));\r
+ }\r
+ /* Set Output mode */\r
+ GPIOx->DDR |= (uint8_t)GPIO_Pin;\r
+ } \r
+ else /* Input mode */\r
+ {\r
+ /* Set Input mode */\r
+ GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));\r
+ }\r
+\r
+ /*------------------------------------------------------------------------*/\r
+ /* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */\r
+ /*------------------------------------------------------------------------*/\r
+\r
+ if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */\r
+ {\r
+ GPIOx->CR1 |= (uint8_t)GPIO_Pin;\r
+ } \r
+ else /* Float or Open-Drain */\r
+ {\r
+ GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));\r
+ }\r
+\r
+ /*-----------------------------------------------------*/\r
+ /* Interrupt (Input) or Slope (Output) modes selection */\r
+ /*-----------------------------------------------------*/\r
+\r
+ if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */\r
+ {\r
+ GPIOx->CR2 |= (uint8_t)GPIO_Pin;\r
+ } \r
+ else /* No external interrupt or No slope control */\r
+ {\r
+ GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @note The port must be configured in output mode.\r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param GPIO_PortVal : Specifies the value to be written to the port output\r
+ * data register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t PortVal)\r
+{\r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Writes high level to the specified GPIO pins.\r
+ * @note The port must be configured in output mode. \r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param PortPins : Specifies the pins to be turned high to the port output.\r
+ * data register.\r
+ * @retval None\r
+ */\r
+void GPIO_WriteHigh(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)\r
+{\r
+ GPIOx->ODR |= (uint8_t)PortPins;\r
+}\r
+\r
+/**\r
+ * @brief Writes low level to the specified GPIO pins.\r
+ * @note The port must be configured in output mode. \r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param PortPins : Specifies the pins to be turned low to the port output.\r
+ * data register.\r
+ * @retval None\r
+ */\r
+void GPIO_WriteLow(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)\r
+{\r
+ GPIOx->ODR &= (uint8_t)(~PortPins);\r
+}\r
+\r
+/**\r
+ * @brief Writes reverse level to the specified GPIO pins.\r
+ * @note The port must be configured in output mode.\r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param PortPins : Specifies the pins to be reversed to the port output.\r
+ * data register.\r
+ * @retval None\r
+ */\r
+void GPIO_WriteReverse(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef PortPins)\r
+{\r
+ GPIOx->ODR ^= (uint8_t)PortPins;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @note The port must be configured in input mode. \r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ return ((uint8_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @note The port must be configured in input mode. \r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ return ((uint8_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data pin.\r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param GPIO_Pin : Specifies the pin number.\r
+ * @retval BitStatus : GPIO input pin status.\r
+ */\r
+BitStatus GPIO_ReadInputPin(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)\r
+{\r
+ return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));\r
+}\r
+\r
+/**\r
+ * @brief Configures the external pull-up on GPIOx pins.\r
+ * @param GPIOx : Select the GPIO peripheral number (x = A to I).\r
+ * @param GPIO_Pin : Specifies the pin number\r
+ * @param NewState : The new state of the pull up pin.\r
+ * @retval None\r
+ */\r
+void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_PIN_OK(GPIO_Pin));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE) /* External Pull-Up Set*/\r
+ {\r
+ GPIOx->CR1 |= (uint8_t)GPIO_Pin;\r
+ } else /* External Pull-Up Reset*/\r
+ {\r
+ GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the I2C peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_i2c.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+\r
+/** @defgroup I2C_Private_Defines\r
+ * @{\r
+ */\r
+/* I2C register mask */\r
+#define REGISTER_Mask ((uint16_t)0x3000)\r
+#define REGISTER_SR1_Index ((uint16_t)0x0100)\r
+#define REGISTER_SR2_Index ((uint16_t)0x0200)\r
+/* I2C Interrupt Enable mask */\r
+#define ITEN_Mask ((uint16_t)0x0700)\r
+/* I2C FLAG mask */\r
+#define FLAG_Mask ((uint16_t)0x00FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+\r
+/**\r
+ * @addtogroup I2C_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2C peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(void)\r
+{\r
+ I2C->CR1 = I2C_CR1_RESET_VALUE;\r
+ I2C->CR2 = I2C_CR2_RESET_VALUE;\r
+ I2C->FREQR = I2C_FREQR_RESET_VALUE;\r
+ I2C->OARL = I2C_OARL_RESET_VALUE;\r
+ I2C->OARH = I2C_OARH_RESET_VALUE;\r
+ I2C->ITR = I2C_ITR_RESET_VALUE;\r
+ I2C->CCRL = I2C_CCRL_RESET_VALUE;\r
+ I2C->CCRH = I2C_CCRH_RESET_VALUE;\r
+ I2C->TRISER = I2C_TRISER_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2C according to the specified parameters in standard\r
+ * or fast mode.\r
+ * @param OutputClockFrequencyHz : Specifies the output clock frequency in Hz.\r
+ * @param OwnAddress : Specifies the own address.\r
+ * @param I2C_DutyCycle : Specifies the duty cycle to apply in fast mode.\r
+ * This parameter can be any of the @ref I2C_DutyCycle_TypeDef enumeration.\r
+ * @note This parameter don't have impact when the OutputClockFrequency lower\r
+ * than 100KHz.\r
+ * @param Ack : Specifies the acknowledge mode to apply.\r
+ * This parameter can be any of the @ref I2C_Ack_TypeDef enumeration.\r
+ * @param AddMode : Specifies the acknowledge address to apply.\r
+ * This parameter can be any of the @ref I2C_AddMode_TypeDef enumeration.\r
+ * @param InputClockFrequencyMHz : Specifies the input clock frequency in MHz.\r
+ * @retval None\r
+ */\r
+void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress, \r
+ I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack, \r
+ I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz )\r
+{\r
+ uint16_t result = 0x0004;\r
+ uint16_t tmpval = 0;\r
+ uint8_t tmpccrh = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ACK_OK(Ack));\r
+ assert_param(IS_I2C_ADDMODE_OK(AddMode));\r
+ assert_param(IS_I2C_OWN_ADDRESS_OK(OwnAddress));\r
+ assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle)); \r
+ assert_param(IS_I2C_INPUT_CLOCK_FREQ_OK(InputClockFrequencyMHz));\r
+ assert_param(IS_I2C_OUTPUT_CLOCK_FREQ_OK(OutputClockFrequencyHz));\r
+\r
+\r
+ /*------------------------- I2C FREQ Configuration ------------------------*/\r
+ /* Clear frequency bits */\r
+ I2C->FREQR &= (uint8_t)(~I2C_FREQR_FREQ);\r
+ /* Write new value */\r
+ I2C->FREQR |= InputClockFrequencyMHz;\r
+\r
+ /*--------------------------- I2C CCR Configuration ------------------------*/\r
+ /* Disable I2C to configure TRISER */\r
+ I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);\r
+\r
+ /* Clear CCRH & CCRL */\r
+ I2C->CCRH &= (uint8_t)(~(I2C_CCRH_FS | I2C_CCRH_DUTY | I2C_CCRH_CCR));\r
+ I2C->CCRL &= (uint8_t)(~I2C_CCRL_CCR);\r
+\r
+ /* Detect Fast or Standard mode depending on the Output clock frequency selected */\r
+ if (OutputClockFrequencyHz > I2C_MAX_STANDARD_FREQ) /* FAST MODE */\r
+ {\r
+ /* Set F/S bit for fast mode */\r
+ tmpccrh = I2C_CCRH_FS;\r
+\r
+ if (I2C_DutyCycle == I2C_DUTYCYCLE_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 3));\r
+ }\r
+ else /* I2C_DUTYCYCLE_16_9 */\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t) ((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz * 25));\r
+ /* Set DUTY bit */\r
+ tmpccrh |= I2C_CCRH_DUTY;\r
+ }\r
+\r
+ /* Verify and correct CCR value if below minimum value */\r
+ if (result < (uint16_t)0x01)\r
+ {\r
+ /* Set the minimum allowed value */\r
+ result = (uint16_t)0x0001;\r
+ }\r
+\r
+ /* Set Maximum Rise Time: 300ns max in Fast Mode\r
+ = [300ns/(1/InputClockFrequencyMHz.10e6)]+1\r
+ = [(InputClockFrequencyMHz * 3)/10]+1 */\r
+ tmpval = ((InputClockFrequencyMHz * 3) / 10) + 1;\r
+ I2C->TRISER = (uint8_t)tmpval;\r
+\r
+ }\r
+ else /* STANDARD MODE */\r
+ {\r
+\r
+ /* Calculate standard mode speed */\r
+ result = (uint16_t)((InputClockFrequencyMHz * 1000000) / (OutputClockFrequencyHz << (uint8_t)1));\r
+\r
+ /* Verify and correct CCR value if below minimum value */\r
+ if (result < (uint16_t)0x0004)\r
+ {\r
+ /* Set the minimum allowed value */\r
+ result = (uint16_t)0x0004;\r
+ }\r
+\r
+ /* Set Maximum Rise Time: 1000ns max in Standard Mode\r
+ = [1000ns/(1/InputClockFrequencyMHz.10e6)]+1\r
+ = InputClockFrequencyMHz+1 */\r
+ I2C->TRISER = (uint8_t)(InputClockFrequencyMHz + (uint8_t)1);\r
+\r
+ }\r
+\r
+ /* Write CCR with new calculated value */\r
+ I2C->CCRL = (uint8_t)result;\r
+ I2C->CCRH = (uint8_t)((uint8_t)((uint8_t)(result >> 8) & I2C_CCRH_CCR) | tmpccrh);\r
+\r
+ /* Enable I2C */\r
+ I2C->CR1 |= I2C_CR1_PE;\r
+\r
+ /* Configure I2C acknowledgement */\r
+ I2C_AcknowledgeConfig(Ack);\r
+\r
+ /*--------------------------- I2C OAR Configuration ------------------------*/\r
+ I2C->OARL = (uint8_t)(OwnAddress);\r
+ I2C->OARH = (uint8_t)((uint8_t)(AddMode | I2C_OARH_ADDCONF) |\r
+ (uint8_t)((OwnAddress & (uint16_t)0x0300) >> (uint8_t)7));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C peripheral.\r
+ * @param NewState : Indicate the new I2C peripheral state.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable I2C peripheral */\r
+ I2C->CR1 |= I2C_CR1_PE;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable I2C peripheral */\r
+ I2C->CR1 &= (uint8_t)(~I2C_CR1_PE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C General Call feature.\r
+ * @param NewState : State of the General Call feature.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable General Call */\r
+ I2C->CR1 |= I2C_CR1_ENGC;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable General Call */\r
+ I2C->CR1 &= (uint8_t)(~I2C_CR1_ENGC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2C communication START condition.\r
+ * @note CCR must be programmed, i.e. I2C_Init function must have been called\r
+ * with a valid I2C_ClockSpeed\r
+ * @param NewState : Enable or disable the start condition.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_GenerateSTART(FunctionalState NewState)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2C->CR2 |= I2C_CR2_START;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2C->CR2 &= (uint8_t)(~I2C_CR2_START);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2C communication STOP condition.\r
+ * @param NewState : Enable or disable the stop condition.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_GenerateSTOP(FunctionalState NewState)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2C->CR2 |= I2C_CR2_STOP;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2C->CR2 &= (uint8_t)(~I2C_CR2_STOP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables I2C software reset.\r
+ * @param NewState : Specifies the new state of the I2C software reset.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2C->CR2 |= I2C_CR2_SWRST;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2C->CR2 &= (uint8_t)(~I2C_CR2_SWRST);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the I2C clock stretching.\r
+ * @param NewState : Specifies the new state of the I2C Clock stretching.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+\r
+void I2C_StretchClockCmd(FunctionalState NewState)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Clock Stretching Enable */\r
+ I2C->CR1 &= (uint8_t)(~I2C_CR1_NOSTRETCH);\r
+\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Clock Stretching Disable (Slave mode) */\r
+ I2C->CR1 |= I2C_CR1_NOSTRETCH;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable or Disable the I2C acknowledge and position acknowledge feature.\r
+ * @note This function must be called before data reception start\r
+ * @param Ack : Specifies the acknowledge mode to apply.\r
+ * This parameter can be any of the @ref I2C_Ack_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_I2C_ACK_OK(Ack));\r
+\r
+ if (Ack == I2C_ACK_NONE)\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2C->CR2 &= (uint8_t)(~I2C_CR2_ACK);\r
+ }\r
+ else\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2C->CR2 |= I2C_CR2_ACK;\r
+\r
+ if (Ack == I2C_ACK_CURR)\r
+ {\r
+ /* Configure (N)ACK on current byte */\r
+ I2C->CR2 &= (uint8_t)(~I2C_CR2_POS);\r
+ }\r
+ else\r
+ {\r
+ /* Configure (N)ACK on next byte */\r
+ I2C->CR2 |= I2C_CR2_POS;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupt.\r
+ * @param ITName : Name of the interrupt to enable or disable.\r
+ * This parameter can be any of the @ref I2C_IT_TypeDef enumeration.\r
+ * @param NewState : State of the interrupt to apply.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState)\r
+{\r
+\r
+ /* Check functions parameters */\r
+ assert_param(IS_I2C_INTERRUPT_OK(I2C_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2C->ITR |= (uint8_t)I2C_IT;\r
+ }\r
+ else /* NewState == DISABLE */\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2C->ITR &= (uint8_t)(~(uint8_t)I2C_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2C_DutyCycle : Specifies the duty cycle to apply.\r
+ * This parameter can be any of the @ref I2C_DutyCycle_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle)\r
+{\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_I2C_DUTYCYCLE_OK(I2C_DutyCycle));\r
+\r
+ if (I2C_DutyCycle == I2C_DUTYCYCLE_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh = 16/9 */\r
+ I2C->CCRH |= I2C_CCRH_DUTY;\r
+ }\r
+ else /* I2C_DUTYCYCLE_2 */\r
+ {\r
+ /* I2C fast mode Tlow/Thigh = 2 */\r
+ I2C->CCRH &= (uint8_t)(~I2C_CCRH_DUTY);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data.\r
+ * @param None\r
+ * @retval uint8_t : The value of the received byte data.\r
+ */\r
+uint8_t I2C_ReceiveData(void)\r
+{\r
+ /* Return the data present in the DR register */\r
+ return ((uint8_t)I2C->DR);\r
+}\r
+\r
+/**\r
+ * @brief Transmits the 7-bit address (to select the) slave device.\r
+ * @param Address : Specifies the slave address which will be transmitted.\r
+ * @param Direction : Specifies whether the I2C device will be a Transmitter or a Receiver.\r
+ * This parameter can be any of the @ref I2C_Direction_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_I2C_ADDRESS_OK(Address));\r
+ assert_param(IS_I2C_DIRECTION_OK(Direction));\r
+\r
+ /* Clear bit0 (direction) just in case */\r
+ Address &= (uint8_t)0xFE;\r
+\r
+ /* Send the Address + Direction */\r
+ I2C->DR = (uint8_t)(Address | (uint8_t)Direction);\r
+}\r
+\r
+/**\r
+ * @brief Send a byte by writing in the DR register.\r
+ * @param Data : Byte to be sent.\r
+ * @retval None\r
+ */\r
+void I2C_SendData(uint8_t Data)\r
+{\r
+ /* Write in the DR register the data to be sent */\r
+ I2C->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ *\r
+ ****************************************************************************************\r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ *\r
+ *\r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1, SR2 and SR3) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags\r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applications as well as for startup\r
+ * activity since the events are fully described in the product reference manual\r
+ * (RM0016).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state.\r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ *\r
+ * @note\r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2C_IRQHandler() which is called when the I2C interurpts occur.\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the\r
+ * I2C_IRQHandler() function in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and\r
+ * source and return to correct communication status.\r
+ *\r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both SR1\r
+ * & SR3 status registers in a single word (uint16_t) (Status Register 3 value\r
+ * is shifted left by 8 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
+ * The returned value could be compared to events already defined in the\r
+ * library (stm8s_i2c.h) or to custom values defined by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no\r
+ * other flags are set or just when the needed flags are set like\r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this\r
+ * function if user decides to check only regular communication flags (and\r
+ * ignores error flags).\r
+ *\r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of\r
+ * one single flag (ie. I2C_FLAG_RXNE ...).\r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events\r
+ * are monitored through multiple flags).\r
+ * - Limitations:\r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one\r
+ * single event.\r
+ *\r
+ * For detailed description of Events, please refer to section I2C_Events in\r
+ * stm8s_i2c.h file.\r
+ *\r
+ */\r
+/**\r
+ *\r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2C Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2C_EVENT: specifies the event to be checked.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+ *\r
+ * @note: For detailed description of Events, please refer to section\r
+ * I2C_Events in stm8s_i2c.h file.\r
+ *\r
+ * @retval An ErrorStatus enumeration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event)\r
+{\r
+ __IO uint16_t lastevent = 0x00;\r
+ uint8_t flag1 = 0x00 ;\r
+ uint8_t flag2 = 0x00;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_EVENT_OK(I2C_Event));\r
+\r
+ if (I2C_Event == I2C_EVENT_SLAVE_ACK_FAILURE)\r
+ {\r
+ lastevent = I2C->SR2 & I2C_SR2_AF;\r
+ }\r
+ else\r
+ {\r
+ flag1 = I2C->SR1;\r
+ flag2 = I2C->SR3;\r
+ lastevent = ((uint16_t)((uint16_t)flag2 << (uint16_t)8) | (uint16_t)flag1);\r
+ }\r
+ /* Check whether the last event is equal to I2C_EVENT */\r
+ if (((uint16_t)lastevent & (uint16_t)I2C_Event) == (uint16_t)I2C_Event)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ *\r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+/**\r
+ * @brief Returns the last I2C Event.\r
+ *\r
+ * @note: For detailed description of Events, please refer to section\r
+ * I2C_Events in stm8s_i2c.h file.\r
+ *\r
+ * @retval The last event\r
+ * This parameter can be any of the @ref I2C_Event_TypeDef enumeration.\r
+ */\r
+I2C_Event_TypeDef I2C_GetLastEvent(void)\r
+{\r
+ __IO uint16_t lastevent = 0;\r
+ uint16_t flag1 = 0;\r
+ uint16_t flag2 = 0;\r
+\r
+ if ((I2C->SR2 & I2C_SR2_AF) != 0x00)\r
+ {\r
+ lastevent = I2C_EVENT_SLAVE_ACK_FAILURE;\r
+ }\r
+ else\r
+ {\r
+ /* Read the I2C status register */\r
+ flag1 = I2C->SR1;\r
+ flag2 = I2C->SR3;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = ((uint16_t)((uint16_t)flag2 << 8) | (uint16_t)flag1);\r
+ }\r
+ /* Return status */\r
+ return (I2C_Event_TypeDef)lastevent;\r
+}\r
+\r
+/**\r
+ *\r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2C_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_GENERALCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRANSMITTERRECEIVER: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSBUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MASTERSLAVE: Master/Slave flag\r
+ * @arg I2C_FLAG_WAKEUPFROMHALT: Wake up from HALT flag \r
+ * @arg I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BUSERROR: Bus error flag\r
+ * @arg I2C_FLAG_TXEMPTY: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNOTEMPTY: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPDETECTION: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_HEADERSENT: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_TRANSFERFINISHED: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDRESSSENTMATCHED: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_FLAG_STARTDETECTION: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag)\r
+{\r
+ uint8_t tempreg = 0;\r
+ uint8_t regindex = 0;\r
+ FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_FLAG_OK(I2C_Flag));\r
+\r
+ /* Read flag register index */\r
+ regindex = (uint8_t)((uint16_t)I2C_Flag >> 8);\r
+ /* Check SRx index */\r
+ switch (regindex)\r
+ {\r
+ /* Returns whether the status register to check is SR1 */\r
+ case 0x01:\r
+ tempreg = (uint8_t)I2C->SR1;\r
+ break;\r
+\r
+ /* Returns whether the status register to check is SR2 */\r
+ case 0x02:\r
+ tempreg = (uint8_t)I2C->SR2;\r
+ break;\r
+\r
+ /* Returns whether the status register to check is SR3 */\r
+ case 0x03:\r
+ tempreg = (uint8_t)I2C->SR3;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if ((tempreg & (uint8_t)I2C_Flag ) != 0)\r
+ {\r
+ /* Flag is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Flag is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clear flags\r
+ * @param I2C_Flag : Specifies the flag to clear\r
+ * This parameter can be any combination of the following values:\r
+ * - I2C_FLAG_WAKEUPFROMHALT: Wakeup from Halt\r
+ * - I2C_FLAG_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)\r
+ * - I2C_FLAG_ACKNOWLEDGEFAILURE: Acknowledge failure flag\r
+ * - I2C_FLAG_ARBITRATIONLOSS: Arbitration lost flag (Master mode)\r
+ * - I2C_FLAG_BUSERROR: Bus error flag.\r
+ * @note Notes:\r
+ * - STOPF (STOP detection) is cleared by software\r
+ * sequence: a read operation to I2C_SR1 register\r
+ * (I2C_GetFlagStatus()) followed by a write operation\r
+ * to I2C_CR2 register.\r
+ * - ADD10 (10-bit header sent) is cleared by software\r
+ * sequence: a read operation to I2C_SR1\r
+ * (I2C_GetFlagStatus()) followed by writing the\r
+ * second byte of the address in DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software\r
+ * sequence: a read operation to I2C_SR1 register\r
+ * (I2C_GetFlagStatus()) followed by a read/write to\r
+ * I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence:\r
+ * a read operation to I2C_SR1 register\r
+ * (I2C_GetFlagStatus()) followed by a read operation to\r
+ * I2C_SR3 register ((void)(I2C->SR3)).\r
+ * - SB (Start Bit) is cleared software sequence: a read\r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus())\r
+ * followed by a write operation to I2C_DR register\r
+ * (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG)\r
+{\r
+ uint16_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_CLEAR_FLAG_OK(I2C_FLAG));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = (uint16_t)I2C_FLAG & FLAG_Mask;\r
+ /* Clear the selected I2C flag */\r
+ I2C->SR2 = (uint8_t)((uint16_t)(~flagpos));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2C_ITPendingBit: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt\r
+ * - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun flag (Slave mode)\r
+ * - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure flag\r
+ * - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost flag (Master mode)\r
+ * - I2C_ITPENDINGBIT_BUSERROR: Bus error flag\r
+ * - I2C_ITPENDINGBIT_TXEMPTY: Data register empty flag (Transmitter)\r
+ * - I2C_ITPENDINGBIT_RXNOTEMPTY: Data register not empty (Receiver) flag\r
+ * - I2C_ITPENDINGBIT_STOPDETECTION: Stop detection flag (Slave mode)\r
+ * - I2C_ITPENDINGBIT_HEADERSENT: 10-bit header sent flag (Master mode)\r
+ * - I2C_ITPENDINGBIT_TRANSFERFINISHED: Byte transfer finished flag\r
+ * - I2C_ITPENDINGBIT_ADDRESSSENTMATCHED: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\93ENDAD\94\r
+ * - I2C_ITPENDINGBIT_STARTDETECTION: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_ITPendingBit\r
+ * This parameter can be any of the @ref ITStatus enumeration.\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ __IO uint8_t enablestatus = 0;\r
+ uint16_t tempregister = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ITPENDINGBIT_OK(I2C_ITPendingBit));\r
+\r
+ tempregister = (uint8_t)( ((uint16_t)((uint16_t)I2C_ITPendingBit & ITEN_Mask)) >> 8);\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint8_t)(I2C->ITR & ( uint8_t)tempregister);\r
+\r
+ if ((uint16_t)((uint16_t)I2C_ITPendingBit & REGISTER_Mask) == REGISTER_SR1_Index)\r
+ {\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2C->SR1 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2C->SR2 & (uint8_t)I2C_ITPendingBit) != RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Clear IT pending bit\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * - I2C_ITPENDINGBIT_WAKEUPFROMHALT: Wakeup from Halt\r
+ * - I2C_ITPENDINGBIT_OVERRUNUNDERRUN: Overrun/Underrun interrupt (Slave mode)\r
+ * - I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE: Acknowledge failure interrupt\r
+ * - I2C_ITPENDINGBIT_ARBITRATIONLOSS: Arbitration lost interrupt (Master mode)\r
+ * - I2C_ITPENDINGBIT_BUSERROR: Bus error interrupt\r
+ *\r
+ * Notes:\r
+ * - STOPF (STOP detection) is cleared by software\r
+ * sequence: a read operation to I2C_SR1 register\r
+ * (I2C_GetITStatus()) followed by a write operation to\r
+ * I2C_CR2 register (I2C_AcknowledgeConfig() to configure\r
+ * the I2C peripheral Acknowledge).\r
+ * - ADD10 (10-bit header sent) is cleared by software\r
+ * sequence: a read operation to I2C_SR1\r
+ * (I2C_GetITStatus()) followed by writing the second\r
+ * byte of the address in I2C_DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software\r
+ * sequence: a read operation to I2C_SR1 register\r
+ * (I2C_GetITStatus()) followed by a read/write to\r
+ * I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence:\r
+ * a read operation to I2C_SR1 register (I2C_GetITStatus())\r
+ * followed by a read operation to I2C_SR3 register\r
+ * ((void)(I2C->SR3)).\r
+ * - SB (Start Bit) is cleared by software sequence: a\r
+ * read operation to I2C_SR1 register (I2C_GetITStatus())\r
+ * followed by a write operation to I2C_DR register\r
+ * (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit)\r
+{\r
+ uint16_t flagpos = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_CLEAR_ITPENDINGBIT_OK(I2C_ITPendingBit));\r
+\r
+ /* Get the I2C flag position */\r
+ flagpos = (uint16_t)I2C_ITPendingBit & FLAG_Mask;\r
+\r
+ /* Clear the selected I2C flag */\r
+ I2C->SR2 = (uint8_t)((uint16_t)~flagpos);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_itc.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the ITC peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_itc.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup ITC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Utility function used to read CC register.\r
+ * @param None\r
+ * @retval CPU CC register value\r
+ */\r
+uint8_t ITC_GetCPUCC(void)\r
+{\r
+#ifdef _COSMIC_\r
+ _asm("push cc");\r
+ _asm("pop a");\r
+ return; /* Ignore compiler warning, the returned value is in A register */\r
+#elif defined _RAISONANCE_ /* _RAISONANCE_ */\r
+ return _getCC_();\r
+#else /* _IAR_ */\r
+ asm("push cc");\r
+ asm("pop a"); /* Ignore compiler warning, the returned value is in A register */\r
+#endif /* _COSMIC_*/\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/** @addtogroup ITC_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ITC registers to their default reset value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ITC_DeInit(void)\r
+{\r
+ ITC->ISPR1 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR2 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR3 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR4 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR5 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR6 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR7 = ITC_SPRX_RESET_VALUE;\r
+ ITC->ISPR8 = ITC_SPRX_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register.\r
+ * @param None\r
+ * @retval The interrupt software priority bits value.\r
+ */\r
+uint8_t ITC_GetSoftIntStatus(void)\r
+{\r
+ return (uint8_t)(ITC_GetCPUCC() & CPU_CC_I1I0);\r
+}\r
+\r
+/**\r
+ * @brief Gets the software priority of the specified interrupt source.\r
+ * @param IrqNum : Specifies the peripheral interrupt source.\r
+ * @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source.\r
+ */\r
+ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)\r
+{\r
+\r
+ uint8_t Value = 0;\r
+ uint8_t Mask = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));\r
+\r
+ /* Define the mask corresponding to the bits position in the SPR register */\r
+ Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U));\r
+\r
+ switch (IrqNum)\r
+ {\r
+ case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */\r
+ case ITC_IRQ_AWU:\r
+ case ITC_IRQ_CLK:\r
+ case ITC_IRQ_PORTA:\r
+ Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */\r
+ break;\r
+ case ITC_IRQ_PORTB:\r
+ case ITC_IRQ_PORTC:\r
+ case ITC_IRQ_PORTD:\r
+ case ITC_IRQ_PORTE:\r
+ Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */\r
+ break;\r
+#if defined(STM8S208) || defined(STM8AF52Ax)\r
+ case ITC_IRQ_CAN_RX:\r
+ case ITC_IRQ_CAN_TX:\r
+#endif /*STM8S208 or STM8AF52Ax */\r
+\r
+#ifdef STM8S903\r
+ case ITC_IRQ_PORTF:\r
+#endif /*STM8S903*/\r
+\r
+ case ITC_IRQ_SPI:\r
+ case ITC_IRQ_TIM1_OVF:\r
+ Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */\r
+ break;\r
+ case ITC_IRQ_TIM1_CAPCOM:\r
+#ifdef STM8S903\r
+ case ITC_IRQ_TIM5_OVFTRI:\r
+ case ITC_IRQ_TIM5_CAPCOM:\r
+#else\r
+ case ITC_IRQ_TIM2_OVF:\r
+ case ITC_IRQ_TIM2_CAPCOM:\r
+#endif /*STM8S903*/\r
+\r
+ case ITC_IRQ_TIM3_OVF:\r
+ Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */\r
+ break;\r
+ case ITC_IRQ_TIM3_CAPCOM:\r
+ case ITC_IRQ_UART1_TX:\r
+ case ITC_IRQ_UART1_RX:\r
+ case ITC_IRQ_I2C:\r
+ Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */\r
+ break;\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)\r
+ case ITC_IRQ_UART2_TX:\r
+ case ITC_IRQ_UART2_RX:\r
+#endif /*STM8S105 or STM8AF626x*/\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \\r
+ defined(STM8AF62Ax)\r
+ case ITC_IRQ_UART3_TX:\r
+ case ITC_IRQ_UART3_RX:\r
+ case ITC_IRQ_ADC2:\r
+#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+ case ITC_IRQ_ADC1:\r
+#endif /*STM8S105, STM8S103 or STM8S905 or STM8AF626x */\r
+\r
+#ifdef STM8S903\r
+ case ITC_IRQ_TIM6_OVFTRI:\r
+#else\r
+ case ITC_IRQ_TIM4_OVF:\r
+#endif /*STM8S903*/\r
+ Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */\r
+ break;\r
+ case ITC_IRQ_EEPROM_EEC:\r
+ Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u);\r
+\r
+ return((ITC_PriorityLevel_TypeDef)Value);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Sets the software priority of the specified interrupt source.\r
+ * @note - The modification of the software priority is only possible when\r
+ * the interrupts are disabled.\r
+ * - The normal behavior is to disable the interrupt before calling\r
+ * this function, and re-enable it after.\r
+ * - The priority level 0 cannot be set (see product specification\r
+ * for more details).\r
+ * @param IrqNum : Specifies the peripheral interrupt source.\r
+ * @param PriorityValue : Specifies the software priority value to set,\r
+ * can be a value of @ref ITC_PriorityLevel_TypeDef .\r
+ * @retval None\r
+*/\r
+void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue)\r
+{\r
+\r
+ uint8_t Mask = 0;\r
+ uint8_t NewPriority = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));\r
+ assert_param(IS_ITC_PRIORITY_OK(PriorityValue));\r
+\r
+ /* Check if interrupts are disabled */\r
+ assert_param(IS_ITC_INTERRUPTS_DISABLED);\r
+\r
+ /* Define the mask corresponding to the bits position in the SPR register */\r
+ /* The mask is reversed in order to clear the 2 bits after more easily */\r
+ Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)));\r
+\r
+ /* Define the new priority to write */\r
+ NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U));\r
+\r
+ switch (IrqNum)\r
+ {\r
+\r
+ case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */\r
+ case ITC_IRQ_AWU:\r
+ case ITC_IRQ_CLK:\r
+ case ITC_IRQ_PORTA:\r
+ ITC->ISPR1 &= Mask;\r
+ ITC->ISPR1 |= NewPriority;\r
+ break;\r
+\r
+ case ITC_IRQ_PORTB:\r
+ case ITC_IRQ_PORTC:\r
+ case ITC_IRQ_PORTD:\r
+ case ITC_IRQ_PORTE:\r
+ ITC->ISPR2 &= Mask;\r
+ ITC->ISPR2 |= NewPriority;\r
+ break;\r
+\r
+#if defined(STM8S208) || defined(STM8AF52Ax)\r
+ case ITC_IRQ_CAN_RX:\r
+ case ITC_IRQ_CAN_TX:\r
+#endif /*STM8S208 or STM8AF52Ax */\r
+\r
+#ifdef STM8S903\r
+ case ITC_IRQ_PORTF:\r
+#endif /*STM8S903*/\r
+ case ITC_IRQ_SPI:\r
+ case ITC_IRQ_TIM1_OVF:\r
+ ITC->ISPR3 &= Mask;\r
+ ITC->ISPR3 |= NewPriority;\r
+ break;\r
+\r
+ case ITC_IRQ_TIM1_CAPCOM:\r
+#ifdef STM8S903\r
+ case ITC_IRQ_TIM5_OVFTRI:\r
+ case ITC_IRQ_TIM5_CAPCOM:\r
+#else\r
+ case ITC_IRQ_TIM2_OVF:\r
+ case ITC_IRQ_TIM2_CAPCOM:\r
+#endif /*STM8S903*/\r
+\r
+ case ITC_IRQ_TIM3_OVF:\r
+ ITC->ISPR4 &= Mask;\r
+ ITC->ISPR4 |= NewPriority;\r
+ break;\r
+\r
+ case ITC_IRQ_TIM3_CAPCOM:\r
+ case ITC_IRQ_UART1_TX:\r
+ case ITC_IRQ_UART1_RX:\r
+ case ITC_IRQ_I2C:\r
+ ITC->ISPR5 &= Mask;\r
+ ITC->ISPR5 |= NewPriority;\r
+ break;\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)\r
+ case ITC_IRQ_UART2_TX:\r
+ case ITC_IRQ_UART2_RX:\r
+#endif /*STM8S105 or STM8AF626x */\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \\r
+ defined(STM8AF62Ax)\r
+ case ITC_IRQ_UART3_TX:\r
+ case ITC_IRQ_UART3_RX:\r
+ case ITC_IRQ_ADC2:\r
+#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+ case ITC_IRQ_ADC1:\r
+#endif /*STM8S105, STM8S103 or STM8S905 or STM8AF626x */\r
+\r
+#ifdef STM8S903\r
+ case ITC_IRQ_TIM6_OVFTRI:\r
+#else\r
+ case ITC_IRQ_TIM4_OVF:\r
+#endif /*STM8S903*/\r
+ ITC->ISPR6 &= Mask;\r
+ ITC->ISPR6 |= NewPriority;\r
+ break;\r
+\r
+ case ITC_IRQ_EEPROM_EEC:\r
+ ITC->ISPR7 &= Mask;\r
+ ITC->ISPR7 |= NewPriority;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the IWDG peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_iwdg.h"\r
+\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/** @addtogroup IWDG_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to Prescaler and Reload registers.\r
+ * @param IWDG_WriteAccess : New state of write access to Prescaler and Reload\r
+ * registers. This parameter can be a value of @ref IWDG_WriteAccess_TypeDef.\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITEACCESS_MODE_OK(IWDG_WriteAccess));\r
+\r
+ IWDG->KR = (uint8_t)IWDG_WriteAccess; /* Write Access */\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @note Write access should be enabled\r
+ * @param IWDG_Prescaler : Specifies the IWDG Prescaler value.\r
+ * This parameter can be a value of @ref IWDG_Prescaler_TypeDef.\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER_OK(IWDG_Prescaler));\r
+\r
+ IWDG->PR = (uint8_t)IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @note Write access should be enabled\r
+ * @param IWDG_Reload : Reload register value.\r
+ * This parameter must be a number between 0 and 0xFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint8_t IWDG_Reload)\r
+{\r
+ IWDG->RLR = IWDG_Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter\r
+ * @note Write access should be enabled\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = IWDG_KEY_REFRESH;\r
+}\r
+\r
+/**\r
+ * @brief Enables IWDG.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = IWDG_KEY_ENABLE;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_rst.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the RST peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+#include "stm8s_rst.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private Constants ---------------------------------------------------------*/\r
+/* Public functions ----------------------------------------------------------*/\r
+/**\r
+ * @addtogroup RST_Public_Functions\r
+ * @{\r
+ */\r
+\r
+\r
+/**\r
+ * @brief Checks whether the specified RST flag is set or not.\r
+ * @param RST_Flag : specify the reset flag to check.\r
+ * This parameter can be a value of @ref RST_FLAG_TypeDef.\r
+ * @retval FlagStatus: status of the given RST flag.\r
+ */\r
+FlagStatus RST_GetFlagStatus(RST_Flag_TypeDef RST_Flag)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RST_FLAG_OK(RST_Flag));\r
+\r
+ /* Get flag status */\r
+\r
+ return ((FlagStatus)((uint8_t)RST->SR & (uint8_t)RST_Flag));\r
+}\r
+\r
+/**\r
+ * @brief Clears the specified RST flag.\r
+ * @param RST_Flag : specify the reset flag to clear.\r
+ * This parameter can be a value of @ref RST_FLAG_TypeDef.\r
+ * @retval None\r
+ */\r
+void RST_ClearFlag(RST_Flag_TypeDef RST_Flag)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RST_FLAG_OK(RST_Flag));\r
+\r
+ RST->SR = (uint8_t)RST_Flag;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_spi.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the SPI peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_spi.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+ \r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup SPI_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SPI_DeInit(void)\r
+{\r
+ SPI->CR1 = SPI_CR1_RESET_VALUE;\r
+ SPI->CR2 = SPI_CR2_RESET_VALUE;\r
+ SPI->ICR = SPI_ICR_RESET_VALUE;\r
+ SPI->SR = SPI_SR_RESET_VALUE;\r
+ SPI->CRCPR = SPI_CRCPR_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPI according to the specified parameters.\r
+ * @param FirstBit : This parameter can be any of the \r
+ * @ref SPI_FirstBit_TypeDef enumeration.\r
+ * @param BaudRatePrescaler : This parameter can be any of the \r
+ * @ref SPI_BaudRatePrescaler_TypeDef enumeration.\r
+ * @param Mode : This parameter can be any of the \r
+ * @ref SPI_Mode_TypeDef enumeration.\r
+ * @param ClockPolarity : This parameter can be any of the \r
+ * @ref SPI_ClockPolarity_TypeDef enumeration.\r
+ * @param ClockPhase : This parameter can be any of the \r
+ * @ref SPI_ClockPhase_TypeDef enumeration.\r
+ * @param Data_Direction : This parameter can be any of the \r
+ * @ref SPI_DataDirection_TypeDef enumeration.\r
+ * @param Slave_Management : This parameter can be any of the \r
+ * @ref SPI_NSS_TypeDef enumeration.\r
+ * @param CRCPolynomial : Configures the CRC polynomial.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, uint8_t CRCPolynomial)\r
+{\r
+ /* Check structure elements */\r
+ assert_param(IS_SPI_FIRSTBIT_OK(FirstBit));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER_OK(BaudRatePrescaler));\r
+ assert_param(IS_SPI_MODE_OK(Mode));\r
+ assert_param(IS_SPI_POLARITY_OK(ClockPolarity));\r
+ assert_param(IS_SPI_PHASE_OK(ClockPhase));\r
+ assert_param(IS_SPI_DATA_DIRECTION_OK(Data_Direction));\r
+ assert_param(IS_SPI_SLAVEMANAGEMENT_OK(Slave_Management));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL_OK(CRCPolynomial));\r
+\r
+ /* Frame Format, BaudRate, Clock Polarity and Phase configuration */\r
+ SPI->CR1 = (uint8_t)((uint8_t)((uint8_t)FirstBit | BaudRatePrescaler) |\r
+ (uint8_t)((uint8_t)ClockPolarity | ClockPhase));\r
+\r
+ /* Data direction configuration: BDM, BDOE and RXONLY bits */\r
+ SPI->CR2 = (uint8_t)((uint8_t)(Data_Direction) | (uint8_t)(Slave_Management));\r
+\r
+ if (Mode == SPI_MODE_MASTER)\r
+ {\r
+ SPI->CR2 |= (uint8_t)SPI_CR2_SSI;\r
+ }\r
+ else\r
+ {\r
+ SPI->CR2 &= (uint8_t)~(SPI_CR2_SSI);\r
+ }\r
+\r
+ /* Master/Slave mode configuration */\r
+ SPI->CR1 |= (uint8_t)(Mode);\r
+\r
+ /* CRC configuration */\r
+ SPI->CRCPR = (uint8_t)CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SPI peripheral.\r
+ * @param NewState New state of the SPI peripheral.\r
+ * This parameter can be: ENABLE or DISABLE\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SPI->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/\r
+ }\r
+ else\r
+ {\r
+ SPI->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified interrupts.\r
+ * @param SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.\r
+ * @param NewState: The new state of the specified SPI interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)\r
+{\r
+ uint8_t itpos = 0;\r
+ /* Check function parameters */\r
+ assert_param(IS_SPI_CONFIG_IT_OK(SPI_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SPI->ICR |= itpos; /* Enable interrupt*/\r
+ }\r
+ else\r
+ {\r
+ SPI->ICR &= (uint8_t)(~itpos); /* Disable interrupt*/\r
+ }\r
+}\r
+/**\r
+ * @brief Transmits a Data through the SPI peripheral.\r
+ * @param Data : Byte to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_SendData(uint8_t Data)\r
+{\r
+ SPI->DR = Data; /* Write in the DR register the data to be sent*/\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPI peripheral.\r
+ * @param None\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t SPI_ReceiveData(void)\r
+{\r
+ return ((uint8_t)SPI->DR); /* Return the data in the DR register*/\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin.\r
+ * @param NewState Indicates the new state of the SPI Software slave management.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SPI->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/\r
+ }\r
+ else\r
+ {\r
+ SPI->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables the transmit of the CRC value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(void)\r
+{\r
+ SPI->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.\r
+ * @param NewState Indicates the new state of the SPI CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRCCmd(FunctionalState NewState)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ SPI->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/\r
+ }\r
+ else\r
+ {\r
+ SPI->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value.\r
+ * @param SPI_CRC Specifies the CRC register to be read.\r
+ * @retval The selected CRC register value.\r
+ */\r
+uint8_t SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)\r
+{\r
+ uint8_t crcreg = 0;\r
+\r
+ /* Check function parameters */\r
+ assert_param(IS_SPI_CRC_OK(SPI_CRC));\r
+\r
+ if (SPI_CRC != SPI_CRC_RX)\r
+ {\r
+ crcreg = SPI->TXCRCR; /* Get the Tx CRC register*/\r
+ }\r
+ else\r
+ {\r
+ crcreg = SPI->RXCRCR; /* Get the Rx CRC register*/\r
+ }\r
+\r
+ /* Return the selected CRC register status*/\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Reset the Rx CRCR and Tx CRCR registers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SPI_ResetCRC(void)\r
+{\r
+ /* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)\r
+ bit in SPI_CR2 is written to 1 (enable) */\r
+ SPI_CalculateCRCCmd(ENABLE);\r
+\r
+ /* Previous function disable the SPI */\r
+ SPI_Cmd(ENABLE);\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value.\r
+ * @param None\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint8_t SPI_GetCRCPolynomial(void)\r
+{\r
+ return SPI->CRCPR; /* Return the CRC polynomial register */\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bi-directional mode.\r
+ * @param SPI_Direction Specifies the data transfer direction in bi-directional mode.\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)\r
+{\r
+ /* Check function parameters */\r
+ assert_param(IS_SPI_DIRECTION_OK(SPI_Direction));\r
+\r
+ if (SPI_Direction != SPI_DIRECTION_RX)\r
+ {\r
+ SPI->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/\r
+ }\r
+ else\r
+ {\r
+ SPI->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI flag is set or not.\r
+ * @param SPI_FLAG : Specifies the flag to check.\r
+ * This parameter can be any of the @ref SPI_FLAG_TypeDef enumeration.\r
+ * @retval FlagStatus : Indicates the state of SPI_FLAG.\r
+ * This parameter can be any of the @ref FlagStatus enumeration.\r
+ */\r
+\r
+FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)\r
+{\r
+ FlagStatus status = RESET;\r
+ /* Check parameters */\r
+ assert_param(IS_SPI_FLAGS_OK(SPI_FLAG));\r
+\r
+ /* Check the status of the specified SPI flag */\r
+ if ((SPI->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)\r
+ {\r
+ status = SET; /* SPI_FLAG is set */\r
+ }\r
+ else\r
+ {\r
+ status = RESET; /* SPI_FLAG is reset*/\r
+ }\r
+\r
+ /* Return the SPI_FLAG status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPI flags.\r
+ * @param SPI_FLAG : Specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - SPI_FLAG_CRCERR\r
+ * - SPI_FLAG_WKUP\r
+ * @note - OVR (OverRun Error) interrupt pending bit is cleared by software\r
+ * sequence:\r
+ * a read operation to SPI_DR register (SPI_ReceiveData()) followed by\r
+ * a read operation to SPI_SR register (SPI_GetFlagStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by\r
+ * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)\r
+{\r
+ assert_param(IS_SPI_CLEAR_FLAGS_OK(SPI_FLAG));\r
+ /* Clear the flag bit */\r
+ SPI->SR = (uint8_t)(~SPI_FLAG);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified interrupt has occurred or not.\r
+ * @param SPI_IT: Specifies the SPI interrupt pending bit to check.\r
+ * This parameter can be one of the following values:\r
+ * - SPI_IT_CRCERR\r
+ * - SPI_IT_WKUP\r
+ * - SPI_IT_OVR\r
+ * - SPI_IT_MODF\r
+ * - SPI_IT_RXNE\r
+ * - SPI_IT_TXE\r
+ * @retval ITStatus : Indicates the state of the SPI_IT.\r
+ * This parameter can be any of the @ref ITStatus enumeration.\r
+ */\r
+ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ uint8_t itpos = 0;\r
+ uint8_t itmask1 = 0;\r
+ uint8_t itmask2 = 0;\r
+ uint8_t enablestatus = 0;\r
+ assert_param(IS_SPI_GET_IT_OK(SPI_IT));\r
+ /* Get the SPI IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));\r
+\r
+ /* Get the SPI IT mask */\r
+ itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);\r
+ /* Set the IT mask */\r
+ itmask2 = (uint8_t)((uint8_t)1 << itmask1);\r
+ /* Get the SPI_ITPENDINGBIT enable bit status */\r
+ enablestatus = (uint8_t)((uint8_t)SPI->SR & itmask2);\r
+ /* Check the status of the specified SPI interrupt */\r
+ if (((SPI->ICR & itpos) != RESET) && enablestatus)\r
+ {\r
+ /* SPI_ITPENDINGBIT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_ITPENDINGBIT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+ /* Return the SPI_ITPENDINGBIT status */\r
+ return pendingbitstatus;\r
+}\r
+/**\r
+ * @brief Clears the interrupt pending bits.\r
+ * @param SPI_IT: Specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - SPI_IT_CRCERR\r
+ * - SPI_IT_WKUP\r
+ * @note - OVR (OverRun Error) interrupt pending bit is cleared by software sequence:\r
+ * a read operation to SPI_DR register (SPI_ReceiveData()) followed by\r
+ * a read operation to SPI_SR register (SPI_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by\r
+ * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)\r
+{\r
+ uint8_t itpos = 0;\r
+ assert_param(IS_SPI_CLEAR_IT_OK(SPI_IT));\r
+\r
+ /* Clear SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */\r
+\r
+ /* Get the SPI pending bit index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));\r
+ /* Clear the pending bit */\r
+ SPI->SR = (uint8_t)(~itpos);\r
+\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim1.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim1.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter);\r
+static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter);\r
+static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter);\r
+static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter);\r
+\r
+/**\r
+ * @addtogroup TIM1_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM1 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM1_DeInit(void)\r
+{\r
+ TIM1->CR1 = TIM1_CR1_RESET_VALUE;\r
+ TIM1->CR2 = TIM1_CR2_RESET_VALUE;\r
+ TIM1->SMCR = TIM1_SMCR_RESET_VALUE;\r
+ TIM1->ETR = TIM1_ETR_RESET_VALUE;\r
+ TIM1->IER = TIM1_IER_RESET_VALUE;\r
+ TIM1->SR2 = TIM1_SR2_RESET_VALUE;\r
+ /* Disable channels */\r
+ TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;\r
+ TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;\r
+ /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */\r
+ TIM1->CCMR1 = 0x01;\r
+ TIM1->CCMR2 = 0x01;\r
+ TIM1->CCMR3 = 0x01;\r
+ TIM1->CCMR4 = 0x01;\r
+ /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */\r
+ TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;\r
+ TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;\r
+ TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;\r
+ TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;\r
+ TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;\r
+ TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;\r
+ TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;\r
+ TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;\r
+ TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;\r
+ TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;\r
+ TIM1->ARRH = TIM1_ARRH_RESET_VALUE;\r
+ TIM1->ARRL = TIM1_ARRL_RESET_VALUE;\r
+ TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;\r
+ TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;\r
+ TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;\r
+ TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;\r
+ TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;\r
+ TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;\r
+ TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;\r
+ TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;\r
+ TIM1->OISR = TIM1_OISR_RESET_VALUE;\r
+ TIM1->EGR = 0x01; /* TIM1_EGR_UG */\r
+ TIM1->DTR = TIM1_DTR_RESET_VALUE;\r
+ TIM1->BKR = TIM1_BKR_RESET_VALUE;\r
+ TIM1->RCR = TIM1_RCR_RESET_VALUE;\r
+ TIM1->SR1 = TIM1_SR1_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 Time Base Unit according to the specified parameters.\r
+ * @param TIM1_Prescaler specifies the Prescaler value.\r
+ * @param TIM1_CounterMode specifies the counter mode from @ref TIM1_CounterMode_TypeDef .\r
+ * @param TIM1_Period specifies the Period value.\r
+ * @param TIM1_RepetitionCounter specifies the Repetition counter value\r
+ * @retval None\r
+ */\r
+void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,\r
+ TIM1_CounterMode_TypeDef TIM1_CounterMode,\r
+ uint16_t TIM1_Period,\r
+ uint8_t TIM1_RepetitionCounter)\r
+{\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));\r
+\r
+ /* Set the Autoreload value */\r
+ TIM1->ARRH = (uint8_t)(TIM1_Period >> 8);\r
+ TIM1->ARRL = (uint8_t)(TIM1_Period);\r
+\r
+ /* Set the Prescaler value */\r
+ TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8);\r
+ TIM1->PSCRL = (uint8_t)(TIM1_Prescaler);\r
+\r
+ /* Select the Counter Mode */\r
+ TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR)))\r
+ | (uint8_t)(TIM1_CounterMode));\r
+\r
+ /* Set the Repetition Counter value */\r
+ TIM1->RCR = TIM1_RepetitionCounter;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 Channel1 according to the specified parameters.\r
+ * @param TIM1_OCMode specifies the Output Compare mode from \r
+ * @ref TIM1_OCMode_TypeDef.\r
+ * @param TIM1_OutputState specifies the Output State from \r
+ * @ref TIM1_OutputState_TypeDef.\r
+ * @param TIM1_OutputNState specifies the Complementary Output State \r
+ * from @ref TIM1_OutputNState_TypeDef.\r
+ * @param TIM1_Pulse specifies the Pulse width value.\r
+ * @param TIM1_OCPolarity specifies the Output Compare Polarity from \r
+ * @ref TIM1_OCPolarity_TypeDef.\r
+ * @param TIM1_OCNPolarity specifies the Complementary Output Compare Polarity\r
+ * from @ref TIM1_OCNPolarity_TypeDef.\r
+ * @param TIM1_OCIdleState specifies the Output Compare Idle State from \r
+ * @ref TIM1_OCIdleState_TypeDef.\r
+ * @param TIM1_OCNIdleState specifies the Complementary Output Compare Idle \r
+ * State from @ref TIM1_OCIdleState_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,\r
+ TIM1_OutputState_TypeDef TIM1_OutputState,\r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState,\r
+ uint16_t TIM1_Pulse,\r
+ TIM1_OCPolarity_TypeDef TIM1_OCPolarity,\r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,\r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState,\r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));\r
+ assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));\r
+ assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+ assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));\r
+ assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , \r
+ the Output N State, the Output Polarity & the Output N Polarity*/\r
+ TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE \r
+ | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));\r
+ /* Set the Output State & Set the Output N State & Set the Output Polarity &\r
+ Set the Output N Polarity */\r
+ TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E)\r
+ | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE))\r
+ | (uint8_t)( (uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC1P)\r
+ | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP)));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | \r
+ (uint8_t)TIM1_OCMode);\r
+\r
+ /* Reset the Output Idle state & the Output N Idle state bits */\r
+ TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));\r
+ /* Set the Output Idle state & the Output N Idle state configuration */\r
+ TIM1->OISR |= (uint8_t)((uint8_t)( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | \r
+ (uint8_t)( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8);\r
+ TIM1->CCR1L = (uint8_t)(TIM1_Pulse);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 Channel2 according to the specified parameters.\r
+ * @param TIM1_OCMode specifies the Output Compare mode from\r
+ * @ref TIM1_OCMode_TypeDef.\r
+ * @param TIM1_OutputState specifies the Output State from \r
+ * @ref TIM1_OutputState_TypeDef.\r
+ * @param TIM1_OutputNState specifies the Complementary Output State from \r
+ * @ref TIM1_OutputNState_TypeDef.\r
+ * @param TIM1_Pulse specifies the Pulse width value.\r
+ * @param TIM1_OCPolarity specifies the Output Compare Polarity from \r
+ * @ref TIM1_OCPolarity_TypeDef.\r
+ * @param TIM1_OCNPolarity specifies the Complementary Output Compare Polarity\r
+ * from @ref TIM1_OCNPolarity_TypeDef.\r
+ * @param TIM1_OCIdleState specifies the Output Compare Idle State from \r
+ * @ref TIM1_OCIdleState_TypeDef.\r
+ * @param TIM1_OCNIdleState specifies the Complementary Output Compare Idle \r
+ * State from @ref TIM1_OCIdleState_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,\r
+ TIM1_OutputState_TypeDef TIM1_OutputState,\r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState,\r
+ uint16_t TIM1_Pulse,\r
+ TIM1_OCPolarity_TypeDef TIM1_OCPolarity,\r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,\r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState,\r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));\r
+ assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));\r
+ assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+ assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));\r
+ assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , \r
+ the Output N State, the Output Polarity & the Output N Polarity*/\r
+ TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | \r
+ TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));\r
+\r
+ /* Set the Output State & Set the Output N State & Set the Output Polarity &\r
+ Set the Output N Polarity */\r
+ TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E ) | \r
+ (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE )) | \r
+ (uint8_t)((uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC2P ) | \r
+ (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP )));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | \r
+ (uint8_t)TIM1_OCMode);\r
+\r
+ /* Reset the Output Idle state & the Output N Idle state bits */\r
+ TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));\r
+ /* Set the Output Idle state & the Output N Idle state configuration */\r
+ TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) | \r
+ (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState));\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8);\r
+ TIM1->CCR2L = (uint8_t)(TIM1_Pulse);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 Channel3 according to the specified parameters.\r
+ * @param TIM1_OCMode specifies the Output Compare mode from \r
+ * @ref TIM1_OCMode_TypeDef.\r
+ * @param TIM1_OutputState specifies the Output State \r
+ * from @ref TIM1_OutputState_TypeDef.\r
+ * @param TIM1_OutputNState specifies the Complementary Output State\r
+ * from @ref TIM1_OutputNState_TypeDef.\r
+ * @param TIM1_Pulse specifies the Pulse width value.\r
+ * @param TIM1_OCPolarity specifies the Output Compare Polarity from \r
+ * @ref TIM1_OCPolarity_TypeDef.\r
+ * @param TIM1_OCNPolarity specifies the Complementary Output Compare \r
+ * Polarity from @ref TIM1_OCNPolarity_TypeDef.\r
+ * @param TIM1_OCIdleState specifies the Output Compare Idle State\r
+ * from @ref TIM1_OCIdleState_TypeDef.\r
+ * @param TIM1_OCNIdleState specifies the Complementary Output Compare \r
+ * Idle State from @ref TIM1_OCIdleState_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,\r
+ TIM1_OutputState_TypeDef TIM1_OutputState,\r
+ TIM1_OutputNState_TypeDef TIM1_OutputNState,\r
+ uint16_t TIM1_Pulse,\r
+ TIM1_OCPolarity_TypeDef TIM1_OCPolarity,\r
+ TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,\r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState,\r
+ TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));\r
+ assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));\r
+ assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+ assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));\r
+ assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , \r
+ the Output N State, the Output Polarity & the Output N Polarity*/\r
+ TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | \r
+ TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));\r
+ /* Set the Output State & Set the Output N State & Set the Output Polarity &\r
+ Set the Output N Polarity */\r
+ TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC3E ) |\r
+ (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE )) | \r
+ (uint8_t)((uint8_t)(TIM1_OCPolarity & TIM1_CCER2_CC3P ) | \r
+ (uint8_t)(TIM1_OCNPolarity & TIM1_CCER2_CC3NP )));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | \r
+ (uint8_t)TIM1_OCMode);\r
+\r
+ /* Reset the Output Idle state & the Output N Idle state bits */\r
+ TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));\r
+ /* Set the Output Idle state & the Output N Idle state configuration */\r
+ TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) | \r
+ (uint8_t)(TIM1_OISR_OIS3N & TIM1_OCNIdleState));\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);\r
+ TIM1->CCR3L = (uint8_t)(TIM1_Pulse);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 Channel4 according to the specified parameters.\r
+ * @param TIM1_OCMode specifies the Output Compare mode from \r
+ * @ref TIM1_OCMode_TypeDef.\r
+ * @param TIM1_OutputState specifies the Output State\r
+ * from @ref TIM1_OutputState_TypeDef.\r
+ * @param TIM1_Pulse specifies the Pulse width value.\r
+ * @param TIM1_OCPolarity specifies the Output Compare Polarity\r
+ * from @ref TIM1_OCPolarity_TypeDef.\r
+ * @param TIM1_OCIdleState specifies the Output Compare Idle State\r
+ * from @ref TIM1_OCIdleState_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,\r
+ TIM1_OutputState_TypeDef TIM1_OutputState,\r
+ uint16_t TIM1_Pulse,\r
+ TIM1_OCPolarity_TypeDef TIM1_OCPolarity,\r
+ TIM1_OCIdleState_TypeDef TIM1_OCIdleState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));\r
+ assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+ assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));\r
+\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ TIM1->CCER2 &= (uint8_t)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));\r
+ /* Set the Output State & the Output Polarity */\r
+ TIM1->CCER2 |= (uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC4E ) | \r
+ (uint8_t)(TIM1_OCPolarity & TIM1_CCER2_CC4P ));\r
+\r
+ /* Reset the Output Compare Bit and Set the Output Compare Mode */\r
+ TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) | \r
+ TIM1_OCMode);\r
+\r
+ /* Set the Output Idle state */\r
+ if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)\r
+ {\r
+ TIM1->OISR |= (uint8_t)(~TIM1_CCER2_CC4P);\r
+ }\r
+ else\r
+ {\r
+ TIM1->OISR &= (uint8_t)(~TIM1_OISR_OIS4);\r
+ }\r
+\r
+ /* Set the Pulse value */\r
+ TIM1->CCR4H = (uint8_t)(TIM1_Pulse >> 8);\r
+ TIM1->CCR4L = (uint8_t)(TIM1_Pulse);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the Break feature, dead time, Lock level, the OSSI,\r
+ * and the AOE(automatic output enable).\r
+ * @param TIM1_OSSIState specifies the OSSIS State from @ref TIM1_OSSIState_TypeDef.\r
+ * @param TIM1_LockLevel specifies the lock level from @ref TIM1_LockLevel_TypeDef.\r
+ * @param TIM1_DeadTime specifies the dead time value.\r
+ * @param TIM1_Break specifies the Break state @ref TIM1_BreakState_TypeDef.\r
+ * @param TIM1_BreakPolarity specifies the Break polarity from \r
+ * @ref TIM1_BreakPolarity_TypeDef.\r
+ * @param TIM1_AutomaticOutput specifies the Automatic Output configuration \r
+ * from @ref TIM1_AutomaticOutput_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,\r
+ TIM1_LockLevel_TypeDef TIM1_LockLevel,\r
+ uint8_t TIM1_DeadTime,\r
+ TIM1_BreakState_TypeDef TIM1_Break,\r
+ TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,\r
+ TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));\r
+ assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));\r
+ assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));\r
+ assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));\r
+ assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));\r
+\r
+ TIM1->DTR = (uint8_t)(TIM1_DeadTime);\r
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,\r
+ the dead time value and the Automatic Output Enable Bit */\r
+\r
+ TIM1->BKR = (uint8_t)((uint8_t)(TIM1_OSSIState | (uint8_t)TIM1_LockLevel) | \r
+ (uint8_t)((uint8_t)(TIM1_Break | (uint8_t)TIM1_BreakPolarity) | \r
+ (uint8_t)TIM1_AutomaticOutput));\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM1 peripheral according to the specified parameters.\r
+ * @param TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef.\r
+ * @param TIM1_ICPolarity specifies the Input capture polarity from \r
+ * TIM1_ICPolarity_TypeDef .\r
+ * @param TIM1_ICSelection specifies the Input capture source selection from \r
+ * TIM1_ICSelection_TypeDef.\r
+ * @param TIM1_ICPrescaler specifies the Input capture Prescaler from\r
+ * TIM1_ICPSC_TypeDef.\r
+ * @param TIM1_ICFilter specifies the Input capture filter value.\r
+ * @retval None\r
+ */\r
+void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,\r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity,\r
+ TIM1_ICSelection_TypeDef TIM1_ICSelection,\r
+ TIM1_ICPSC_TypeDef TIM1_ICPrescaler,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));\r
+ assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));\r
+ assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));\r
+ assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));\r
+\r
+ if (TIM1_Channel == TIM1_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM1_ICPolarity,\r
+ (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICPrescaler);\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM1_ICPolarity,\r
+ (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICPrescaler);\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_3)\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config((uint8_t)TIM1_ICPolarity,\r
+ (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC3Prescaler(TIM1_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI4 Configuration */\r
+ TI4_Config((uint8_t)TIM1_ICPolarity,\r
+ (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC4Prescaler(TIM1_ICPrescaler);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 peripheral in PWM Input Mode according to the \r
+ * specified parameters.\r
+ * @param TIM1_Channel specifies the input capture channel from \r
+ * @ref TIM1_Channel_TypeDef.\r
+ * @param TIM1_ICPolarity specifies the Input capture polarity from \r
+ * @ref TIM1_ICPolarity_TypeDef .\r
+ * @param TIM1_ICSelection specifies the Input capture source selection from\r
+ * @ref TIM1_ICSelection_TypeDef.\r
+ * @param TIM1_ICPrescaler specifies the Input capture Prescaler from \r
+ * @ref TIM1_ICPSC_TypeDef.\r
+ * @param TIM1_ICFilter specifies the Input capture filter value.\r
+ * @retval None\r
+ */\r
+void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,\r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity,\r
+ TIM1_ICSelection_TypeDef TIM1_ICSelection,\r
+ TIM1_ICPSC_TypeDef TIM1_ICPrescaler,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+ uint8_t icpolarity = TIM1_ICPOLARITY_RISING;\r
+ uint8_t icselection = TIM1_ICSELECTION_DIRECTTI;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_PWMI_CHANNEL_OK(TIM1_Channel));\r
+ assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));\r
+ assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM1_ICPolarity != TIM1_ICPOLARITY_FALLING)\r
+ {\r
+ icpolarity = TIM1_ICPOLARITY_FALLING;\r
+ }\r
+ else\r
+ {\r
+ icpolarity = TIM1_ICPOLARITY_RISING;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM1_ICSelection == TIM1_ICSELECTION_DIRECTTI)\r
+ {\r
+ icselection = TIM1_ICSELECTION_INDIRECTTI;\r
+ }\r
+ else\r
+ {\r
+ icselection = TIM1_ICSELECTION_DIRECTTI;\r
+ }\r
+\r
+ if (TIM1_Channel == TIM1_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config(icpolarity, icselection, TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,\r
+ (uint8_t)TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC2Prescaler(TIM1_ICPrescaler);\r
+\r
+ /* TI1 Configuration */\r
+ TI1_Config(icpolarity, icselection, TIM1_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM1_SetIC1Prescaler(TIM1_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral.\r
+ * @param NewState new state of the TIM1 peripheral.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR1 |= TIM1_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral Main Outputs.\r
+ * @param NewState new state of the TIM1 peripheral.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_CtrlPWMOutputs(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the MOE Bit */\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->BKR |= TIM1_BKR_MOE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM1 interrupts.\r
+ * @param NewState new state of the TIM1 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @param TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * - TIM1_IT_UPDATE: TIM1 update Interrupt source\r
+ * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+ * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+ * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+ * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+ * - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source\r
+ * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source\r
+ * - TIM1_IT_BREAK: TIM1 Break Interrupt source\r
+ * @param NewState new state of the TIM1 peripheral.\r
+ * @retval None\r
+ */\r
+void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IT_OK(TIM1_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM1->IER |= (uint8_t)TIM1_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 internal Clock.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM1_InternalClockConfig(void)\r
+{\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS);\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 External clock Mode1.\r
+ * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPSC_OFF\r
+ * - TIM1_EXTTRGPSC_DIV2\r
+ * - TIM1_EXTTRGPSC_DIV4\r
+ * - TIM1_EXTTRGPSC_DIV8.\r
+ * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPOLARITY_INVERTED\r
+ * - TIM1_EXTTRGPOLARITY_NONINVERTED\r
+ * @param ExtTRGFilter specifies the External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,\r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,\r
+ uint8_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));\r
+ assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Select the External clock mode1 & Select the Trigger selection : ETRF */\r
+ TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(uint8_t)(TIM1_SMCR_SMS | TIM1_SMCR_TS )))\r
+ | (uint8_t)((uint8_t)TIM1_SLAVEMODE_EXTERNAL1 | TIM1_TS_ETRF ));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 External clock Mode2.\r
+ * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPSC_OFF\r
+ * - TIM1_EXTTRGPSC_DIV2\r
+ * - TIM1_EXTTRGPSC_DIV4\r
+ * - TIM1_EXTTRGPSC_DIV8.\r
+ * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPOLARITY_INVERTED\r
+ * - TIM1_EXTTRGPOLARITY_NONINVERTED\r
+ * @param ExtTRGFilter specifies the External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,\r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,\r
+ uint8_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));\r
+ assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));\r
+\r
+ /* Configure the ETR Clock source */\r
+ TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);\r
+\r
+ /* Enable the External clock mode2 */\r
+ TIM1->ETR |= TIM1_ETR_ECE;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 External Trigger.\r
+ * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPSC_OFF\r
+ * - TIM1_EXTTRGPSC_DIV2\r
+ * - TIM1_EXTTRGPSC_DIV4\r
+ * - TIM1_EXTTRGPSC_DIV8.\r
+ * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EXTTRGPOLARITY_INVERTED\r
+ * - TIM1_EXTTRGPOLARITY_NONINVERTED\r
+ * @param ExtTRGFilter specifies the External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,\r
+ TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,\r
+ uint8_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_EXT_TRG_FILTER_OK(ExtTRGFilter));\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ TIM1->ETR |= (uint8_t)((uint8_t)(TIM1_ExtTRGPrescaler | (uint8_t)TIM1_ExtTRGPolarity )|\r
+ (uint8_t)ExtTRGFilter );\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Trigger as External Clock.\r
+ * @param TIM1_TIxExternalCLKSource specifies Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector\r
+ * - TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1\r
+ * - TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2\r
+ * @param TIM1_ICPolarity specifies the TIx Polarity.\r
+ * This parameter can be:\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * @param ICFilter specifies the filter value.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,\r
+ TIM1_ICPolarity_TypeDef TIM1_ICPolarity,\r
+ uint8_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));\r
+ assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));\r
+ assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));\r
+\r
+ /* Configure the TIM1 Input Clock Source */\r
+ if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)\r
+ {\r
+ TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);\r
+ }\r
+\r
+ /* Select the Trigger source */\r
+ TIM1_SelectInputTrigger((TIM1_TS_TypeDef)TIM1_TIxExternalCLKSource);\r
+\r
+ /* Select the External clock mode1 */\r
+ TIM1->SMCR |= (uint8_t)(TIM1_SLAVEMODE_EXTERNAL1);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM1 Input Trigger source.\r
+ * @param TIM1_InputTriggerSource specifies Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_TS_TI1F_ED: TI1 Edge Detector\r
+ * - TIM1_TS_TI1FP1: Filtered Timer Input 1\r
+ * - TIM1_TS_TI2FP2: Filtered Timer Input 2\r
+ * - TIM1_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));\r
+\r
+ /* Select the Tgigger Source */\r
+ TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM1 Update event.\r
+ * @param NewState new state of the TIM1 peripheral Preload register. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+\r
+void TIM1_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR1 |= TIM1_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM1 Update Request Interrupt source.\r
+ * @param TIM1_UpdateSource specifies the Update source.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_UPDATESOURCE_REGULAR\r
+ * - TIM1_UPDATESOURCE_GLOBAL\r
+ * @retval None\r
+ */\r
+void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)\r
+ {\r
+ TIM1->CR1 |= TIM1_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM1\92s Hall sensor interface.\r
+ * @param NewState new state of the TIM1 Hall sensor interface.This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_SelectHallSensor(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the TI1S Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR2 |= TIM1_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM1\92s One Pulse Mode.\r
+ * @param TIM1_OPMode specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_OPMODE_SINGLE\r
+ * - TIM1_OPMODE_REPETITIVE\r
+ * @retval None\r
+ */\r
+void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)\r
+ {\r
+ TIM1->CR1 |= TIM1_CR1_OPM;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM);\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM1 Trigger Output Mode.\r
+ * @param TIM1_TRGOSource specifies the Trigger Output source.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_TRGOSOURCE_RESET\r
+ * - TIM1_TRGOSOURCE_ENABLE\r
+ * - TIM1_TRGOSOURCE_UPDATE\r
+ * - TIM1_TRGOSource_OC1\r
+ * - TIM1_TRGOSOURCE_OC1REF\r
+ * - TIM1_TRGOSOURCE_OC2REF\r
+ * - TIM1_TRGOSOURCE_OC3REF\r
+ * @retval None\r
+ */\r
+void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));\r
+ \r
+ /* Reset the MMS Bits & Select the TRGO source */\r
+ TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) | \r
+ (uint8_t) TIM1_TRGOSource);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM1 Slave Mode.\r
+ * @param TIM1_SlaveMode specifies the TIM1 Slave Mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_SLAVEMODE_RESET\r
+ * - TIM1_SLAVEMODE_GATED\r
+ * - TIM1_SLAVEMODE_TRIGGER\r
+ * - TIM1_SLAVEMODE_EXTERNAL1\r
+ * @retval None\r
+ */\r
+void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));\r
+\r
+ /* Reset the SMS Bits */ /* Select the Slave Mode */\r
+ TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) |\r
+ (uint8_t)TIM1_SlaveMode);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM1 Master/Slave Mode.\r
+ * @param NewState new state of the synchronization between TIM1 and its slaves\r
+ * (through TRGO). This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_SelectMasterSlaveMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the MSM Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->SMCR |= TIM1_SMCR_MSM;\r
+ }\r
+ else\r
+ {\r
+ TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Encoder Interface.\r
+ * @param TIM1_EncoderMode specifies the TIM1 Encoder Mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge\r
+ * depending on TI2FP2 level.\r
+ * - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge\r
+ * depending on TI1FP1 level.\r
+ * - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and\r
+ * TI2FP2 edges depending on the level of the other input.\r
+ * @param TIM1_IC1Polarity specifies the IC1 Polarity.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @param TIM1_IC2Polarity specifies the IC2 Polarity.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @retval None\r
+ */\r
+void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,\r
+ TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,\r
+ TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)\r
+{\r
+\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));\r
+ assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));\r
+ assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);\r
+ }\r
+\r
+ if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);\r
+ }\r
+ /* Set the encoder Mode */\r
+ TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS))\r
+ | (uint8_t) TIM1_EncoderMode);\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS)) \r
+ | (uint8_t) CCMR_TIxDirect_Set);\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS))\r
+ | (uint8_t) CCMR_TIxDirect_Set);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Prescaler.\r
+ * @param Prescaler specifies the Prescaler Register value\r
+ * This parameter must be a value between 0x0000 and 0xFFFF\r
+ * @param TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.\r
+ * - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.\r
+ * @retval None\r
+ */\r
+\r
+void TIM1_PrescalerConfig(uint16_t Prescaler,\r
+ TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM1->PSCRH = (uint8_t)(Prescaler >> 8);\r
+ TIM1->PSCRL = (uint8_t)(Prescaler);\r
+\r
+ /* Set or reset the UG Bit */\r
+ TIM1->EGR = (uint8_t)TIM1_PSCReloadMode;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIM1 Counter Mode to be used.\r
+ * @param TIM1_CounterMode specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode\r
+ * - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode\r
+ * - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1\r
+ * - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2\r
+ * - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));\r
+\r
+\r
+ /* Reset the CMS and DIR Bits & Set the Counter Mode */\r
+ TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR)))\r
+ | (uint8_t)TIM1_CounterMode);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Forces the TIM1 Channel1 output waveform to active or inactive level.\r
+ * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF\r
+ * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))|\r
+ (uint8_t)TIM1_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Forces the TIM1 Channel2 output waveform to active or inactive level.\r
+ * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF\r
+ * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))\r
+ | (uint8_t)TIM1_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Forces the TIM1 Channel3 output waveform to active or inactive level.\r
+ * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF\r
+ * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));\r
+\r
+ /* Reset the OCM Bits */ /* Configure The Forced output Mode */\r
+ TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) \r
+ | (uint8_t)TIM1_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Forces the TIM1 Channel4 output waveform to active or inactive level.\r
+ * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF\r
+ * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) \r
+ | (uint8_t)TIM1_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables TIM1 peripheral Preload register on ARR.\r
+ * @param NewState new state of the TIM1 peripheral Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR1 |= TIM1_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM1 peripheral Commutation event.\r
+ * @param NewState new state of the Commutation event.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_SelectCOM(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the COMS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR2 |= TIM1_CR2_COMS;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR2 &= (uint8_t)(~TIM1_CR2_COMS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.\r
+ * @param NewState new state of the Capture Compare Preload Control bit.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_CCPreloadControl(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the CCPC Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CR2 |= TIM1_CR2_CCPC;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral Preload Register on CCR1.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC1PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC1PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR1 |= TIM1_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral Preload Register on CCR2.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC2PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC2PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR2 |= TIM1_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral Preload Register on CCR3.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC3PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC3PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR3 |= TIM1_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 peripheral Preload Register on CCR4.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+\r
+void TIM1_OC4PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC4PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR4 |= TIM1_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Capture Compare 1 Fast feature.\r
+ * @param NewState new state of the Output Compare Fast Enable bit.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC1FastConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC1FE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR1 |= TIM1_CCMR_OCxFE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Capture Compare 2 Fast feature.\r
+ * @param NewState new state of the Output Compare Fast Enable bit.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+\r
+void TIM1_OC2FastConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC2FE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR2 |= TIM1_CCMR_OCxFE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Capture Compare 3 Fast feature.\r
+ * @param NewState new state of the Output Compare Fast Enable bit.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC3FastConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC3FE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR3 |= TIM1_CCMR_OCxFE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Capture Compare 4 Fast feature.\r
+ * @param NewState new state of the Output Compare Fast Enable bit.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_OC4FastConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC4FE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCMR4 |= TIM1_CCMR_OCxFE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxFE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 event to be generated by software.\r
+ * @param TIM1_EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source\r
+ * - TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source\r
+ * - TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source\r
+ * - TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source\r
+ * - TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source\r
+ * - TIM1_EVENTSOURCE_COM: TIM1 COM Event source\r
+ * - TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source\r
+ * - TIM1_EventSourceBreak: TIM1 Break Event source\r
+ * @retval None\r
+ */\r
+void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM1->EGR = (uint8_t)TIM1_EventSource;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 1 polarity.\r
+ * @param TIM1_OCPolarity specifies the OC1 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 1N polarity.\r
+ * @param TIM1_OCNPolarity specifies the OC1N Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCNPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCNPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1NP;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 2 polarity.\r
+ * @param TIM1_OCPolarity specifies the OC2 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 2N polarity.\r
+ * @param TIM1_OCNPolarity specifies the OC2N Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCNPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCNPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2NP;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 3 polarity.\r
+ * @param TIM1_OCPolarity specifies the OC3 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 3N polarity.\r
+ * @param TIM1_OCNPolarity specifies the OC3N Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCNPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCNPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3NP;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM1 Channel 4 polarity.\r
+ * @param TIM1_OCPolarity specifies the OC4 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM1_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));\r
+\r
+ /* Set or Reset the CC4P Bit */\r
+ if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC4P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).\r
+ * @param TIM1_Channel specifies the TIM1 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_CHANNEL_1: TIM1 Channel1\r
+ * - TIM1_CHANNEL_2: TIM1 Channel2\r
+ * - TIM1_CHANNEL_3: TIM1 Channel3\r
+ * - TIM1_CHANNEL_4: TIM1 Channel4\r
+ * @param NewState specifies the TIM1 Channel CCxE bit new state.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (TIM1_Channel == TIM1_CHANNEL_1)\r
+ {\r
+ /* Set or Reset the CC1E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1E;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);\r
+ }\r
+\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_2)\r
+ {\r
+ /* Set or Reset the CC2E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2E;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);\r
+ }\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_3)\r
+ {\r
+ /* Set or Reset the CC3E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3E;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC4E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC4E;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).\r
+ * @param TIM1_Channel specifies the TIM1 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_CHANNEL_1: TIM1 Channel1\r
+ * - TIM1_CHANNEL_2: TIM1 Channel2\r
+ * - TIM1_CHANNEL_3: TIM1 Channel3\r
+ * @param NewState specifies the TIM1 Channel CCxNE bit new state.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL_OK(TIM1_Channel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (TIM1_Channel == TIM1_CHANNEL_1)\r
+ {\r
+ /* Set or Reset the CC1NE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1NE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE);\r
+ }\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_2)\r
+ {\r
+ /* Set or Reset the CC2NE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2NE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC3NE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3NE;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM1 Output Compare Mode. This function disables the\r
+ * selected channel before changing the Output Compare Mode. User has to\r
+ * enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.\r
+ * @param TIM1_Channel specifies the TIM1 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_CHANNEL_1: TIM1 Channel1\r
+ * - TIM1_CHANNEL_2: TIM1 Channel2\r
+ * - TIM1_CHANNEL_3: TIM1 Channel3\r
+ * - TIM1_CHANNEL_4: TIM1 Channel4\r
+ * @param TIM1_OCMode specifies the TIM1 Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * - TIM1_OCMODE_TIMING\r
+ * - TIM1_OCMODE_ACTIVE\r
+ * - TIM1_OCMODE_TOGGLE\r
+ * - TIM1_OCMODE_PWM1\r
+ * - TIM1_OCMODE_PWM2\r
+ * - TIM1_FORCEDACTION_ACTIVE\r
+ * - TIM1_FORCEDACTION_INACTIVE\r
+ * @retval None\r
+ */\r
+void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));\r
+ assert_param(IS_TIM1_OCM_OK(TIM1_OCMode));\r
+\r
+ if (TIM1_Channel == TIM1_CHANNEL_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) \r
+ | (uint8_t)TIM1_OCMode);\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_2)\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))\r
+ | (uint8_t)TIM1_OCMode);\r
+ }\r
+ else if (TIM1_Channel == TIM1_CHANNEL_3)\r
+ {\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) \r
+ | (uint8_t)TIM1_OCMode);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) \r
+ | (uint8_t)TIM1_OCMode);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Counter Register value.\r
+ * @param Counter specifies the Counter register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetCounter(uint16_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM1->CNTRH = (uint8_t)(Counter >> 8);\r
+ TIM1->CNTRL = (uint8_t)(Counter);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Autoreload Register value.\r
+ * @param Autoreload specifies the Autoreload register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetAutoreload(uint16_t Autoreload)\r
+{\r
+\r
+ /* Set the Autoreload Register value */\r
+ TIM1->ARRH = (uint8_t)(Autoreload >> 8);\r
+ TIM1->ARRL = (uint8_t)(Autoreload);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Capture Compare1 Register value.\r
+ * @param Compare1 specifies the Capture Compare1 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetCompare1(uint16_t Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIM1->CCR1H = (uint8_t)(Compare1 >> 8);\r
+ TIM1->CCR1L = (uint8_t)(Compare1);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Capture Compare2 Register value.\r
+ * @param Compare2 specifies the Capture Compare2 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetCompare2(uint16_t Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIM1->CCR2H = (uint8_t)(Compare2 >> 8);\r
+ TIM1->CCR2L = (uint8_t)(Compare2);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Capture Compare3 Register value.\r
+ * @param Compare3 specifies the Capture Compare3 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetCompare3(uint16_t Compare3)\r
+{\r
+ /* Set the Capture Compare3 Register value */\r
+ TIM1->CCR3H = (uint8_t)(Compare3 >> 8);\r
+ TIM1->CCR3L = (uint8_t)(Compare3);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Capture Compare4 Register value.\r
+ * @param Compare4 specifies the Capture Compare4 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM1_SetCompare4(uint16_t Compare4)\r
+{\r
+ /* Set the Capture Compare4 Register value */\r
+ TIM1->CCR4H = (uint8_t)(Compare4 >> 8);\r
+ TIM1->CCR4L = (uint8_t)(Compare4);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Input Capture 1 prescaler.\r
+ * @param TIM1_IC1Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPSC_DIV1: no prescaler\r
+ * - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC1Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC)) \r
+ | (uint8_t)TIM1_IC1Prescaler);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM1 Input Capture 2 prescaler.\r
+ * @param TIM1_IC2Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPSC_DIV1: no prescaler\r
+ * - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC2Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC))\r
+ | (uint8_t)TIM1_IC2Prescaler);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM1 Input Capture 3 prescaler.\r
+ * @param TIM1_IC3Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPSC_DIV1: no prescaler\r
+ * - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC3Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits & Set the IC1PSC value */\r
+ TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | \r
+ (uint8_t)TIM1_IC3Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM1 Input Capture 4 prescaler.\r
+ * @param TIM1_IC4Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPSC_DIV1: no prescaler\r
+ * - TIM1_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM1_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM1_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC4Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits & Set the IC1PSC value */\r
+ TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |\r
+ (uint8_t)TIM1_IC4Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Input Capture 1 value.\r
+ * @param None\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM1_GetCapture1(void)\r
+{\r
+ /* Get the Capture 1 Register value */\r
+\r
+ uint16_t tmpccr1 = 0;\r
+ uint8_t tmpccr1l=0, tmpccr1h=0;\r
+\r
+ tmpccr1h = TIM1->CCR1H;\r
+ tmpccr1l = TIM1->CCR1L;\r
+\r
+ tmpccr1 = (uint16_t)(tmpccr1l);\r
+ tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);\r
+ /* Get the Capture 1 Register value */\r
+ return (uint16_t)tmpccr1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Input Capture 2 value.\r
+ * @param None\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM1_GetCapture2(void)\r
+{\r
+ /* Get the Capture 2 Register value */\r
+\r
+ uint16_t tmpccr2 = 0;\r
+ uint8_t tmpccr2l=0, tmpccr2h=0;\r
+\r
+ tmpccr2h = TIM1->CCR2H;\r
+ tmpccr2l = TIM1->CCR2L;\r
+\r
+ tmpccr2 = (uint16_t)(tmpccr2l);\r
+ tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);\r
+ /* Get the Capture 2 Register value */\r
+ return (uint16_t)tmpccr2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Input Capture 3 value.\r
+ * @param None\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint16_t TIM1_GetCapture3(void)\r
+{\r
+ /* Get the Capture 3 Register value */\r
+ uint16_t tmpccr3 = 0;\r
+ uint8_t tmpccr3l=0, tmpccr3h=0;\r
+\r
+ tmpccr3h = TIM1->CCR3H;\r
+ tmpccr3l = TIM1->CCR3L;\r
+\r
+ tmpccr3 = (uint16_t)(tmpccr3l);\r
+ tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);\r
+ /* Get the Capture 3 Register value */\r
+ return (uint16_t)tmpccr3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Input Capture 4 value.\r
+ * @param None\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint16_t TIM1_GetCapture4(void)\r
+{\r
+ /* Get the Capture 4 Register value */\r
+ uint16_t tmpccr4 = 0;\r
+ uint8_t tmpccr4l=0, tmpccr4h=0;\r
+\r
+ tmpccr4h = TIM1->CCR4H;\r
+ tmpccr4l = TIM1->CCR4L;\r
+\r
+ tmpccr4 = (uint16_t)(tmpccr4l);\r
+ tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8);\r
+ /* Get the Capture 4 Register value */\r
+ return (uint16_t)tmpccr4;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Counter value.\r
+ * @param None\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM1_GetCounter(void)\r
+{\r
+ uint16_t tmpcntr = 0;\r
+ \r
+ tmpcntr = ((uint16_t)TIM1->CNTRH << 8);\r
+ \r
+ /* Get the Counter Register value */\r
+ return (uint16_t)(tmpcntr | (uint16_t)(TIM1->CNTRL));\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM1 Prescaler value.\r
+ * @param None\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM1_GetPrescaler(void)\r
+{\r
+ uint16_t temp = 0;\r
+ \r
+ temp = ((uint16_t)TIM1->PSCRH << 8);\r
+ \r
+ /* Get the Prescaler Register value */\r
+ return (uint16_t)( temp | (uint16_t)(TIM1->PSCRL));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM1 flag is set or not.\r
+ * @param TIM1_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FLAG_UPDATE: TIM1 update Flag\r
+ * - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag\r
+ * - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag\r
+ * - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag\r
+ * - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag\r
+ * - TIM1_FLAG_COM: TIM1 Commutation Flag\r
+ * - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag\r
+ * - TIM1_FLAG_BREAK: TIM1 Break Flag\r
+ * - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag\r
+ * - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag\r
+ * - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag\r
+ * - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag\r
+ * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint8_t tim1_flag_l = 0, tim1_flag_h = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_GET_FLAG_OK(TIM1_FLAG));\r
+\r
+ tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG);\r
+ tim1_flag_h = (uint8_t)((uint16_t)TIM1_FLAG >> 8);\r
+\r
+ if ((tim1_flag_l | (uint8_t)(TIM1->SR2 & tim1_flag_h)) != 0)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (FlagStatus)(bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM1\92s pending flags.\r
+ * @param TIM1_FLAG specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_FLAG_UPDATE: TIM1 update Flag\r
+ * - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag\r
+ * - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag\r
+ * - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag\r
+ * - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag\r
+ * - TIM1_FLAG_COM: TIM1 Commutation Flag\r
+ * - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag\r
+ * - TIM1_FLAG_BREAK: TIM1 Break Flag\r
+ * - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag\r
+ * - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag\r
+ * - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag\r
+ * - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag\r
+ * @retval None.\r
+ */\r
+void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_CLEAR_FLAG_OK(TIM1_FLAG));\r
+\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG));\r
+ TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) & \r
+ (uint8_t)0x1E);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM1 interrupt has occurred or not.\r
+ * @param TIM1_IT specifies the TIM1 interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_IT_UPDATE: TIM1 update Interrupt source\r
+ * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+ * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+ * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+ * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+ * - TIM1_IT_COM: TIM1 Commutation Interrupt source\r
+ * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source\r
+ * - TIM1_IT_BREAK: TIM1 Break Interrupt source\r
+ * @retval ITStatus The new state of the TIM1_IT(SET or RESET).\r
+ */\r
+ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint8_t TIM1_itStatus = 0, TIM1_itEnable = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_GET_IT_OK(TIM1_IT));\r
+\r
+ TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT);\r
+\r
+ TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT);\r
+\r
+ if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (ITStatus)(bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM1's interrupt pending bits.\r
+ * @param TIM1_IT specifies the pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_IT_UPDATE: TIM1 update Interrupt source\r
+ * - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source\r
+ * - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source\r
+ * - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source\r
+ * - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source\r
+ * - TIM1_IT_COM: TIM1 Commutation Interrupt source\r
+ * - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source\r
+ * - TIM1_IT_BREAK: TIM1 Break Interrupt source\r
+ * @retval None.\r
+ */\r
+void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM1_IT_OK(TIM1_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT);\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIM1_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @param TIM1_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to\r
+ * be connected to IC1.\r
+ * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to\r
+ * be connected to IC2.\r
+ * @param TIM1_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(uint8_t TIM1_ICPolarity,\r
+ uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | \r
+ (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);\r
+ }\r
+\r
+ /* Set the CCE Bit */\r
+ TIM1->CCER1 |= TIM1_CCER1_CC1E;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIM1_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @param TIM1_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to\r
+ * be connected to IC2.\r
+ * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to\r
+ * be connected to IC1.\r
+ * @param TIM1_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(uint8_t TIM1_ICPolarity,\r
+ uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) \r
+ | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));\r
+ /* Select the Polarity */\r
+ if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM1->CCER1 |= TIM1_CCER1_CC2E;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIM1_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @param TIM1_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to\r
+ * be connected to IC3.\r
+ * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to\r
+ * be connected to IC4.\r
+ * @param TIM1_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(uint8_t TIM1_ICPolarity,\r
+ uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) \r
+ | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM1->CCER2 |= TIM1_CCER2_CC3E;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIM1_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICPOLARITY_FALLING\r
+ * - TIM1_ICPOLARITY_RISING\r
+ * @param TIM1_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to\r
+ * be connected to IC4.\r
+ * - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to\r
+ * be connected to IC3.\r
+ * @param TIM1_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(uint8_t TIM1_ICPolarity,\r
+ uint8_t TIM1_ICSelection,\r
+ uint8_t TIM1_ICFilter)\r
+{\r
+\r
+ /* Disable the Channel 4: Reset the CCE Bit */\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))\r
+ | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)\r
+ {\r
+ TIM1->CCER2 |= TIM1_CCER2_CC4P;\r
+ }\r
+ else\r
+ {\r
+ TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);\r
+ }\r
+\r
+ /* Set the CCE Bit */\r
+ TIM1->CCER2 |= TIM1_CCER2_CC4E;\r
+}\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim2.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim2.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TI1_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);\r
+static void TI2_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);\r
+static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection, uint8_t TIM2_ICFilter);\r
+/**\r
+ * @addtogroup TIM2_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM2 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM2_DeInit(void)\r
+{\r
+\r
+ TIM2->CR1 = (uint8_t)TIM2_CR1_RESET_VALUE;\r
+ TIM2->IER = (uint8_t)TIM2_IER_RESET_VALUE;\r
+ TIM2->SR2 = (uint8_t)TIM2_SR2_RESET_VALUE;\r
+\r
+ /* Disable channels */\r
+ TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;\r
+ TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;\r
+\r
+\r
+ /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */\r
+ TIM2->CCER1 = (uint8_t)TIM2_CCER1_RESET_VALUE;\r
+ TIM2->CCER2 = (uint8_t)TIM2_CCER2_RESET_VALUE;\r
+ TIM2->CCMR1 = (uint8_t)TIM2_CCMR1_RESET_VALUE;\r
+ TIM2->CCMR2 = (uint8_t)TIM2_CCMR2_RESET_VALUE;\r
+ TIM2->CCMR3 = (uint8_t)TIM2_CCMR3_RESET_VALUE;\r
+ TIM2->CNTRH = (uint8_t)TIM2_CNTRH_RESET_VALUE;\r
+ TIM2->CNTRL = (uint8_t)TIM2_CNTRL_RESET_VALUE;\r
+ TIM2->PSCR = (uint8_t)TIM2_PSCR_RESET_VALUE;\r
+ TIM2->ARRH = (uint8_t)TIM2_ARRH_RESET_VALUE;\r
+ TIM2->ARRL = (uint8_t)TIM2_ARRL_RESET_VALUE;\r
+ TIM2->CCR1H = (uint8_t)TIM2_CCR1H_RESET_VALUE;\r
+ TIM2->CCR1L = (uint8_t)TIM2_CCR1L_RESET_VALUE;\r
+ TIM2->CCR2H = (uint8_t)TIM2_CCR2H_RESET_VALUE;\r
+ TIM2->CCR2L = (uint8_t)TIM2_CCR2L_RESET_VALUE;\r
+ TIM2->CCR3H = (uint8_t)TIM2_CCR3H_RESET_VALUE;\r
+ TIM2->CCR3L = (uint8_t)TIM2_CCR3L_RESET_VALUE;\r
+ TIM2->SR1 = (uint8_t)TIM2_SR1_RESET_VALUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM2 Time Base Unit according to the specified parameters.\r
+ * @param TIM2_Prescaler specifies the Prescaler from TIM2_Prescaler_TypeDef.\r
+ * @param TIM2_Period specifies the Period value.\r
+ * @retval None\r
+ */\r
+void TIM2_TimeBaseInit( TIM2_Prescaler_TypeDef TIM2_Prescaler,\r
+ uint16_t TIM2_Period)\r
+{\r
+ /* Set the Prescaler value */\r
+ TIM2->PSCR = (uint8_t)(TIM2_Prescaler);\r
+ /* Set the Autoreload value */\r
+ TIM2->ARRH = (uint8_t)(TIM2_Period >> 8);\r
+ TIM2->ARRL = (uint8_t)(TIM2_Period);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM2 Channel1 according to the specified parameters.\r
+ * @param TIM2_OCMode specifies the Output Compare mode from @ref TIM2_OCMode_TypeDef.\r
+ * @param TIM2_OutputState specifies the Output State from @ref TIM2_OutputState_TypeDef.\r
+ * @param TIM2_Pulse specifies the Pulse width value.\r
+ * @param TIM2_OCPolarity specifies the Output Compare Polarity from @ref TIM2_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,\r
+ TIM2_OutputState_TypeDef TIM2_OutputState,\r
+ uint16_t TIM2_Pulse,\r
+ TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));\r
+ assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */\r
+ TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC1E | TIM2_CCER1_CC1P));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER1_CC1E ) | \r
+ (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC1P));\r
+\r
+ /* Reset the Output Compare Bits & Set the Ouput Compare Mode */\r
+ TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM)) |\r
+ (uint8_t)TIM2_OCMode);\r
+\r
+ /* Set the Pulse value */\r
+ TIM2->CCR1H = (uint8_t)(TIM2_Pulse >> 8);\r
+ TIM2->CCR1L = (uint8_t)(TIM2_Pulse);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM2 Channel2 according to the specified parameters.\r
+ * @param TIM2_OCMode specifies the Output Compare mode from @ref TIM2_OCMode_TypeDef.\r
+ * @param TIM2_OutputState specifies the Output State from @ref TIM2_OutputState_TypeDef.\r
+ * @param TIM2_Pulse specifies the Pulse width value.\r
+ * @param TIM2_OCPolarity specifies the Output Compare Polarity from @ref TIM2_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,\r
+ TIM2_OutputState_TypeDef TIM2_OutputState,\r
+ uint16_t TIM2_Pulse,\r
+ TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));\r
+ assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */\r
+ TIM2->CCER1 &= (uint8_t)(~( TIM2_CCER1_CC2E | TIM2_CCER1_CC2P ));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM2->CCER1 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER1_CC2E ) |\r
+ (uint8_t)(TIM2_OCPolarity & TIM2_CCER1_CC2P));\r
+\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM)) | \r
+ (uint8_t)TIM2_OCMode);\r
+\r
+\r
+ /* Set the Pulse value */\r
+ TIM2->CCR2H = (uint8_t)(TIM2_Pulse >> 8);\r
+ TIM2->CCR2L = (uint8_t)(TIM2_Pulse);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM2 Channel3 according to the specified parameters.\r
+ * @param TIM2_OCMode specifies the Output Compare mode from @ref TIM2_OCMode_TypeDef.\r
+ * @param TIM2_OutputState specifies the Output State from @ref TIM2_OutputState_TypeDef.\r
+ * @param TIM2_Pulse specifies the Pulse width value.\r
+ * @param TIM2_OCPolarity specifies the Output Compare Polarity from @ref TIM2_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM2_OC3Init(TIM2_OCMode_TypeDef TIM2_OCMode,\r
+ TIM2_OutputState_TypeDef TIM2_OutputState,\r
+ uint16_t TIM2_Pulse,\r
+ TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_MODE_OK(TIM2_OCMode));\r
+ assert_param(IS_TIM2_OUTPUT_STATE_OK(TIM2_OutputState));\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */\r
+ TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E | TIM2_CCER2_CC3P));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM2->CCER2 |= (uint8_t)((uint8_t)(TIM2_OutputState & TIM2_CCER2_CC3E) | \r
+ (uint8_t)(TIM2_OCPolarity & TIM2_CCER2_CC3P));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |\r
+ (uint8_t)TIM2_OCMode);\r
+\r
+ /* Set the Pulse value */\r
+ TIM2->CCR3H = (uint8_t)(TIM2_Pulse >> 8);\r
+ TIM2->CCR3L = (uint8_t)(TIM2_Pulse);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM2 peripheral according to the specified parameters.\r
+ * @param TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.\r
+ * @param TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.\r
+ * @param TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.\r
+ * @param TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.\r
+ * @param TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,\r
+ TIM2_ICPolarity_TypeDef TIM2_ICPolarity,\r
+ TIM2_ICSelection_TypeDef TIM2_ICSelection,\r
+ TIM2_ICPSC_TypeDef TIM2_ICPrescaler,\r
+ uint8_t TIM2_ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));\r
+ assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));\r
+ assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));\r
+ assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));\r
+ assert_param(IS_TIM2_IC_FILTER_OK(TIM2_ICFilter));\r
+\r
+ if (TIM2_Channel == TIM2_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM2_ICPolarity,\r
+ (uint8_t)TIM2_ICSelection,\r
+ (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC1Prescaler(TIM2_ICPrescaler);\r
+ }\r
+ else if (TIM2_Channel == TIM2_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM2_ICPolarity,\r
+ (uint8_t)TIM2_ICSelection,\r
+ (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC2Prescaler(TIM2_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config((uint8_t)TIM2_ICPolarity,\r
+ (uint8_t)TIM2_ICSelection,\r
+ (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC3Prescaler(TIM2_ICPrescaler);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 peripheral in PWM Input Mode according to the specified parameters.\r
+ * @param TIM2_Channel specifies the Input Capture Channel from @ref TIM2_Channel_TypeDef.\r
+ * @param TIM2_ICPolarity specifies the Input Capture Polarity from @ref TIM2_ICPolarity_TypeDef.\r
+ * @param TIM2_ICSelection specifies the Input Capture Selection from @ref TIM2_ICSelection_TypeDef.\r
+ * @param TIM2_ICPrescaler specifies the Input Capture Prescaler from @ref TIM2_ICPSC_TypeDef.\r
+ * @param TIM2_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,\r
+ TIM2_ICPolarity_TypeDef TIM2_ICPolarity,\r
+ TIM2_ICSelection_TypeDef TIM2_ICSelection,\r
+ TIM2_ICPSC_TypeDef TIM2_ICPrescaler,\r
+ uint8_t TIM2_ICFilter)\r
+{\r
+ uint8_t icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;\r
+ uint8_t icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_PWMI_CHANNEL_OK(TIM2_Channel));\r
+ assert_param(IS_TIM2_IC_POLARITY_OK(TIM2_ICPolarity));\r
+ assert_param(IS_TIM2_IC_SELECTION_OK(TIM2_ICSelection));\r
+ assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_ICPrescaler));\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM2_ICPolarity != TIM2_ICPOLARITY_FALLING)\r
+ {\r
+ icpolarity = (uint8_t)TIM2_ICPOLARITY_FALLING;\r
+ }\r
+ else\r
+ {\r
+ icpolarity = (uint8_t)TIM2_ICPOLARITY_RISING;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM2_ICSelection == TIM2_ICSELECTION_DIRECTTI)\r
+ {\r
+ icselection = (uint8_t)TIM2_ICSELECTION_INDIRECTTI;\r
+ }\r
+ else\r
+ {\r
+ icselection = (uint8_t)TIM2_ICSELECTION_DIRECTTI;\r
+ }\r
+\r
+ if (TIM2_Channel == TIM2_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,\r
+ (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC1Prescaler(TIM2_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config(icpolarity, icselection, TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC2Prescaler(TIM2_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM2_ICPolarity, (uint8_t)TIM2_ICSelection,\r
+ (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC2Prescaler(TIM2_ICPrescaler);\r
+\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)icpolarity, icselection, (uint8_t)TIM2_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM2_SetIC1Prescaler(TIM2_ICPrescaler);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM2 peripheral.\r
+ * @param NewState new state of the TIM2 peripheral. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM2 interrupts.\r
+ * @param NewState new state of the TIM2 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @param TIM2_IT specifies the TIM2 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * - TIM2_IT_UPDATE: TIM2 update Interrupt source\r
+ * - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source\r
+ * - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source\r
+ * - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source\r
+ * @param NewState new state of the TIM2 peripheral.\r
+ * @retval None\r
+ */\r
+void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_IT_OK(TIM2_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM2->IER |= (uint8_t)TIM2_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM2->IER &= (uint8_t)(~TIM2_IT);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM2 Update event.\r
+ * @param NewState new state of the TIM2 peripheral Preload register. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CR1 |= (uint8_t)TIM2_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CR1 &= (uint8_t)(~TIM2_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM2 Update Request Interrupt source.\r
+ * @param TIM2_UpdateSource specifies the Update source.\r
+ * This parameter can be one of the following values\r
+ * - TIM2_UPDATESOURCE_REGULAR\r
+ * - TIM2_UPDATESOURCE_GLOBAL\r
+ * @retval None\r
+ */\r
+void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)\r
+ {\r
+ TIM2->CR1 |= (uint8_t)TIM2_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CR1 &= (uint8_t)(~TIM2_CR1_URS);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM2\92s One Pulse Mode.\r
+ * @param TIM2_OPMode specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values\r
+ * - TIM2_OPMODE_SINGLE\r
+ * - TIM2_OPMODE_REPETITIVE\r
+ * @retval None\r
+ */\r
+void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)\r
+ {\r
+ TIM2->CR1 |= (uint8_t)TIM2_CR1_OPM;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CR1 &= (uint8_t)(~TIM2_CR1_OPM);\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 Prescaler.\r
+ * @param Prescaler specifies the Prescaler Register value\r
+ * This parameter can be one of the following values\r
+ * - TIM2_PRESCALER_1\r
+ * - TIM2_PRESCALER_2\r
+ * - TIM2_PRESCALER_4\r
+ * - TIM2_PRESCALER_8\r
+ * - TIM2_PRESCALER_16\r
+ * - TIM2_PRESCALER_32\r
+ * - TIM2_PRESCALER_64\r
+ * - TIM2_PRESCALER_128\r
+ * - TIM2_PRESCALER_256\r
+ * - TIM2_PRESCALER_512\r
+ * - TIM2_PRESCALER_1024\r
+ * - TIM2_PRESCALER_2048\r
+ * - TIM2_PRESCALER_4096\r
+ * - TIM2_PRESCALER_8192\r
+ * - TIM2_PRESCALER_16384\r
+ * - TIM2_PRESCALER_32768\r
+ * @param TIM2_PSCReloadMode specifies the TIM2 Prescaler Reload mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM2_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded\r
+ * immediately.\r
+ * - TIM2_PSCRELOADMODE_UPDATE: The Prescaler is loaded at\r
+ * the update event.\r
+ * @retval None\r
+ */\r
+void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,\r
+ TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));\r
+ assert_param(IS_TIM2_PRESCALER_OK(Prescaler));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM2->PSCR = (uint8_t)Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ TIM2->EGR = (uint8_t)TIM2_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM2 Channel1 output waveform to active or inactive level.\r
+ * @param TIM2_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_FORCEDACTION_ACTIVE: Force active level on OC1REF\r
+ * - TIM2_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM)) \r
+ | (uint8_t)TIM2_ForcedAction);\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM2 Channel2 output waveform to active or inactive level.\r
+ * @param TIM2_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_FORCEDACTION_ACTIVE: Force active level on OC2REF\r
+ * - TIM2_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM)) \r
+ | (uint8_t)TIM2_ForcedAction);\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM2 Channel3 output waveform to active or inactive level.\r
+ * @param TIM2_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_FORCEDACTION_ACTIVE: Force active level on OC3REF\r
+ * - TIM2_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))\r
+ | (uint8_t)TIM2_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables TIM2 peripheral Preload register on ARR.\r
+ * @param NewState new state of the TIM2 peripheral Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CR1 |= (uint8_t)TIM2_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CR1 &= (uint8_t)(~TIM2_CR1_ARPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM2 peripheral Preload Register on CCR1.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_OC1PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC1PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCMR1 |= (uint8_t)TIM2_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCMR1 &= (uint8_t)(~TIM2_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM2 peripheral Preload Register on CCR2.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_OC2PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC2PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCMR2 |= (uint8_t)TIM2_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCMR2 &= (uint8_t)(~TIM2_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM2 peripheral Preload Register on CCR3.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_OC3PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC3PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCMR3 |= (uint8_t)TIM2_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCMR3 &= (uint8_t)(~TIM2_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 event to be generated by software.\r
+ * @param TIM2_EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_EVENTSOURCE_UPDATE: TIM2 update Event source\r
+ * - TIM2_EVENTSOURCE_CC1: TIM2 Capture Compare 1 Event source\r
+ * - TIM2_EVENTSOURCE_CC2: TIM2 Capture Compare 2 Event source\r
+ * - TIM2_EVENTSOURCE_CC3: TIM2 Capture Compare 3 Event source\r
+ * @retval None\r
+ */\r
+void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM2->EGR = (uint8_t)TIM2_EventSource;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 Channel 1 polarity.\r
+ * @param TIM2_OCPolarity specifies the OC1 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM2_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)\r
+ {\r
+ TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 Channel 2 polarity.\r
+ * @param TIM2_OCPolarity specifies the OC2 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM2_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)\r
+ {\r
+ TIM2->CCER1 |= TIM2_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM2 Channel 3 polarity.\r
+ * @param TIM2_OCPolarity specifies the OC3 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM2_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)\r
+ {\r
+ TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM2 Capture Compare Channel x.\r
+ * @param TIM2_Channel specifies the TIM2 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_CHANNEL_1: TIM2 Channel1\r
+ * - TIM2_CHANNEL_2: TIM2 Channel2\r
+ * - TIM2_CHANNEL_3: TIM2 Channel3\r
+ * @param NewState specifies the TIM2 Channel CCxE bit new state.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (TIM2_Channel == TIM2_CHANNEL_1)\r
+ {\r
+ /* Set or Reset the CC1E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC1E;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);\r
+ }\r
+\r
+ }\r
+ else if (TIM2_Channel == TIM2_CHANNEL_2)\r
+ {\r
+ /* Set or Reset the CC2E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCER1 |= (uint8_t)TIM2_CCER1_CC2E;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC3E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM2->CCER2 |= (uint8_t)TIM2_CCER2_CC3E;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM2 Output Compare Mode. This function disables the\r
+ * selected channel before changing the Output Compare Mode. User has to\r
+ * enable this channel using TIM2_CCxCmd and TIM2_CCxNCmd functions.\r
+ * @param TIM2_Channel specifies the TIM2 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_CHANNEL_1: TIM2 Channel1\r
+ * - TIM2_CHANNEL_2: TIM2 Channel2\r
+ * - TIM2_CHANNEL_3: TIM2 Channel3\r
+ * @param TIM2_OCMode specifies the TIM2 Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * - TIM2_OCMODE_TIMING\r
+ * - TIM2_OCMODE_ACTIVE\r
+ * - TIM2_OCMODE_TOGGLE\r
+ * - TIM2_OCMODE_PWM1\r
+ * - TIM2_OCMODE_PWM2\r
+ * - TIM2_FORCEDACTION_ACTIVE\r
+ * - TIM2_FORCEDACTION_INACTIVE\r
+ * @retval None\r
+ */\r
+void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));\r
+ assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));\r
+\r
+ if (TIM2_Channel == TIM2_CHANNEL_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_OCM))\r
+ | (uint8_t)TIM2_OCMode);\r
+ }\r
+ else if (TIM2_Channel == TIM2_CHANNEL_2)\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_OCM))\r
+ | (uint8_t)TIM2_OCMode);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM))\r
+ | (uint8_t)TIM2_OCMode);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Counter Register value.\r
+ * @param Counter specifies the Counter register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM2_SetCounter(uint16_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM2->CNTRH = (uint8_t)(Counter >> 8);\r
+ TIM2->CNTRL = (uint8_t)(Counter);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Autoreload Register value.\r
+ * @param Autoreload specifies the Autoreload register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM2_SetAutoreload(uint16_t Autoreload)\r
+{\r
+\r
+ /* Set the Autoreload Register value */\r
+ TIM2->ARRH = (uint8_t)(Autoreload >> 8);\r
+ TIM2->ARRL = (uint8_t)(Autoreload);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Capture Compare1 Register value.\r
+ * @param Compare1 specifies the Capture Compare1 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM2_SetCompare1(uint16_t Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIM2->CCR1H = (uint8_t)(Compare1 >> 8);\r
+ TIM2->CCR1L = (uint8_t)(Compare1);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Capture Compare2 Register value.\r
+ * @param Compare2 specifies the Capture Compare2 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM2_SetCompare2(uint16_t Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIM2->CCR2H = (uint8_t)(Compare2 >> 8);\r
+ TIM2->CCR2L = (uint8_t)(Compare2);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Capture Compare3 Register value.\r
+ * @param Compare3 specifies the Capture Compare3 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM2_SetCompare3(uint16_t Compare3)\r
+{\r
+ /* Set the Capture Compare3 Register value */\r
+ TIM2->CCR3H = (uint8_t)(Compare3 >> 8);\r
+ TIM2->CCR3L = (uint8_t)(Compare3);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM2 Input Capture 1 Prescaler.\r
+ * @param TIM2_IC1Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPSC_DIV1: no prescaler\r
+ * - TIM2_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM2_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM2_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC1Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits &Set the IC1PSC value */\r
+ TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~TIM2_CCMR_ICxPSC))\r
+ | (uint8_t)TIM2_IC1Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM2 Input Capture 2 prescaler.\r
+ * @param TIM2_IC2Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPSC_DIV1: no prescaler\r
+ * - TIM2_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM2_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM2_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC2Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits &Set the IC1PSC value */\r
+ TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~TIM2_CCMR_ICxPSC))\r
+ | (uint8_t)TIM2_IC2Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM2 Input Capture 3 prescaler.\r
+ * @param TIM2_IC3Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPSC_DIV1: no prescaler\r
+ * - TIM2_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM2_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM2_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC3Prescaler));\r
+ /* Reset the IC1PSC Bits &Set the IC1PSC value */\r
+ TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_ICxPSC))\r
+ | (uint8_t)TIM2_IC3Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM2 Input Capture 1 value.\r
+ * @param None\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM2_GetCapture1(void)\r
+{\r
+ /* Get the Capture 1 Register value */\r
+ uint16_t tmpccr1 = 0;\r
+ uint8_t tmpccr1l=0, tmpccr1h=0;\r
+\r
+ tmpccr1h = TIM2->CCR1H;\r
+ tmpccr1l = TIM2->CCR1L;\r
+\r
+ tmpccr1 = (uint16_t)(tmpccr1l);\r
+ tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);\r
+ /* Get the Capture 1 Register value */\r
+ return (uint16_t)tmpccr1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM2 Input Capture 2 value.\r
+ * @param None\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM2_GetCapture2(void)\r
+{\r
+ /* Get the Capture 2 Register value */\r
+ uint16_t tmpccr2 = 0;\r
+ uint8_t tmpccr2l=0, tmpccr2h=0;\r
+\r
+ tmpccr2h = TIM2->CCR2H;\r
+ tmpccr2l = TIM2->CCR2L;\r
+\r
+ tmpccr2 = (uint16_t)(tmpccr2l);\r
+ tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);\r
+ /* Get the Capture 2 Register value */\r
+ return (uint16_t)tmpccr2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM2 Input Capture 3 value.\r
+ * @param None\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint16_t TIM2_GetCapture3(void)\r
+{\r
+ /* Get the Capture 3 Register value */\r
+ uint16_t tmpccr3 = 0;\r
+ uint8_t tmpccr3l=0, tmpccr3h=0;\r
+\r
+ tmpccr3h = TIM2->CCR3H;\r
+ tmpccr3l = TIM2->CCR3L;\r
+\r
+ tmpccr3 = (uint16_t)(tmpccr3l);\r
+ tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);\r
+ /* Get the Capture 3 Register value */\r
+ return (uint16_t)tmpccr3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM2 Counter value.\r
+ * @param None\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM2_GetCounter(void)\r
+{\r
+ uint16_t tmpcntr = 0;\r
+ \r
+ tmpcntr = ((uint16_t)TIM2->CNTRH << 8);\r
+ /* Get the Counter Register value */\r
+ return (uint16_t)( tmpcntr| (uint16_t)(TIM2->CNTRL));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Gets the TIM2 Prescaler value.\r
+ * @param None\r
+ * @retval Prescaler Register configuration value @ref TIM2_Prescaler_TypeDef.\r
+ */\r
+TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return (TIM2_Prescaler_TypeDef)(TIM2->PSCR);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM2 flag is set or not.\r
+ * @param TIM2_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_FLAG_UPDATE: TIM2 update Flag\r
+ * - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag\r
+ * - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag\r
+ * - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag\r
+ * - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag\r
+ * - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag\r
+ * - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag\r
+ * @retval FlagStatus The new state of TIM2_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint8_t tim2_flag_l = 0, tim2_flag_h = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_GET_FLAG_OK(TIM2_FLAG));\r
+\r
+ tim2_flag_l = (uint8_t)(TIM2->SR1 & (uint8_t)TIM2_FLAG);\r
+ tim2_flag_h = (uint8_t)((uint16_t)TIM2_FLAG >> 8);\r
+\r
+ if ((tim2_flag_l | (uint8_t)(TIM2->SR2 & tim2_flag_h)) != (uint8_t)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (FlagStatus)bitstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM2\92s pending flags.\r
+ * @param TIM2_FLAG specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_FLAG_UPDATE: TIM2 update Flag\r
+ * - TIM2_FLAG_CC1: TIM2 Capture Compare 1 Flag\r
+ * - TIM2_FLAG_CC2: TIM2 Capture Compare 2 Flag\r
+ * - TIM2_FLAG_CC3: TIM2 Capture Compare 3 Flag\r
+ * - TIM2_FLAG_CC1OF: TIM2 Capture Compare 1 over capture Flag\r
+ * - TIM2_FLAG_CC2OF: TIM2 Capture Compare 2 over capture Flag\r
+ * - TIM2_FLAG_CC3OF: TIM2 Capture Compare 3 over capture Flag\r
+ * @retval None.\r
+ */\r
+void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));\r
+\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM2->SR1 = (uint8_t)(~((uint8_t)(TIM2_FLAG)));\r
+ TIM2->SR2 = (uint8_t)(~((uint8_t)((uint8_t)TIM2_FLAG >> 8)));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Checks whether the TIM2 interrupt has occurred or not.\r
+ * @param TIM2_IT specifies the TIM2 interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_IT_UPDATE: TIM2 update Interrupt source\r
+ * - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source\r
+ * - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source\r
+ * - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source\r
+ * @retval ITStatus The new state of the TIM2_IT(SET or RESET).\r
+ */\r
+\r
+ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint8_t TIM2_itStatus = 0, TIM2_itEnable = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));\r
+\r
+ TIM2_itStatus = (uint8_t)(TIM2->SR1 & TIM2_IT);\r
+\r
+ TIM2_itEnable = (uint8_t)(TIM2->IER & TIM2_IT);\r
+\r
+ if ((TIM2_itStatus != (uint8_t)RESET ) && (TIM2_itEnable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (ITStatus)(bitstatus);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM2's interrupt pending bits.\r
+ * @param TIM2_IT specifies the pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_IT_UPDATE: TIM2 update Interrupt source\r
+ * - TIM2_IT_CC1: TIM2 Capture Compare 1 Interrupt source\r
+ * - TIM2_IT_CC2: TIM2 Capture Compare 2 Interrupt source\r
+ * - TIM2_IT_CC3: TIM2 Capture Compare 3 Interrupt source\r
+ * @retval None.\r
+ */\r
+void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM2_IT_OK(TIM2_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM2->SR1 = (uint8_t)(~TIM2_IT);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIM2_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPOLARITY_FALLING\r
+ * - TIM2_ICPOLARITY_RISING\r
+ * @param TIM2_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 1 is selected to\r
+ * be connected to IC1.\r
+ * - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 1 is selected to\r
+ * be connected to IC2.\r
+ * @param TIM2_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(uint8_t TIM2_ICPolarity,\r
+ uint8_t TIM2_ICSelection,\r
+ uint8_t TIM2_ICFilter)\r
+{\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM2->CCMR1 = (uint8_t)((uint8_t)(TIM2->CCMR1 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF )))\r
+ | (uint8_t)(((TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)\r
+ {\r
+ TIM2->CCER1 |= TIM2_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC1P);\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM2->CCER1 |= TIM2_CCER1_CC1E;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIM2_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPOLARITY_FALLING\r
+ * - TIM2_ICPOLARITY_RISING\r
+ * @param TIM2_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 2 is selected to\r
+ * be connected to IC2.\r
+ * - TIM2_ICSELECTION_INDIRECTTI: TIM2 Input 2 is selected to\r
+ * be connected to IC1.\r
+ * @param TIM2_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(uint8_t TIM2_ICPolarity,\r
+ uint8_t TIM2_ICSelection,\r
+ uint8_t TIM2_ICFilter)\r
+{\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM2->CCMR2 = (uint8_t)((uint8_t)(TIM2->CCMR2 & (uint8_t)(~(uint8_t)( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) \r
+ | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));\r
+\r
+\r
+ /* Select the Polarity */\r
+ if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)\r
+ {\r
+ TIM2->CCER1 |= TIM2_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER1 &= (uint8_t)(~TIM2_CCER1_CC2P);\r
+ }\r
+\r
+ /* Set the CCE Bit */\r
+ TIM2->CCER1 |= TIM2_CCER1_CC2E;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIM2_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICPOLARITY_FALLING\r
+ * - TIM2_ICPOLARITY_RISING\r
+ * @param TIM2_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM2_ICSELECTION_DIRECTTI: TIM2 Input 3 is selected to\r
+ * be connected to IC3.\r
+ * @param TIM2_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(uint8_t TIM2_ICPolarity, uint8_t TIM2_ICSelection,\r
+ uint8_t TIM2_ICFilter)\r
+{\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF))) \r
+ | (uint8_t)(( (TIM2_ICSelection)) | ((uint8_t)( TIM2_ICFilter << 4))));\r
+\r
+\r
+ /* Select the Polarity */\r
+ if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)\r
+ {\r
+ TIM2->CCER2 |= TIM2_CCER2_CC3P;\r
+ }\r
+ else\r
+ {\r
+ TIM2->CCER2 &= (uint8_t)(~TIM2_CCER2_CC3P);\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM2->CCER2 |= TIM2_CCER2_CC3E;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim3.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM3 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim3.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TI1_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);\r
+static void TI2_Config(uint8_t TIM3_ICPolarity, uint8_t TIM3_ICSelection, uint8_t TIM3_ICFilter);\r
+/**\r
+ * @addtogroup TIM3_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM3 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM3_DeInit(void)\r
+{\r
+\r
+ TIM3->CR1 = (uint8_t)TIM3_CR1_RESET_VALUE;\r
+ TIM3->IER = (uint8_t)TIM3_IER_RESET_VALUE;\r
+ TIM3->SR2 = (uint8_t)TIM3_SR2_RESET_VALUE;\r
+\r
+ /* Disable channels */\r
+ TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;\r
+\r
+ /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */\r
+ TIM3->CCER1 = (uint8_t)TIM3_CCER1_RESET_VALUE;\r
+ TIM3->CCMR1 = (uint8_t)TIM3_CCMR1_RESET_VALUE;\r
+ TIM3->CCMR2 = (uint8_t)TIM3_CCMR2_RESET_VALUE;\r
+ TIM3->CNTRH = (uint8_t)TIM3_CNTRH_RESET_VALUE;\r
+ TIM3->CNTRL = (uint8_t)TIM3_CNTRL_RESET_VALUE;\r
+ TIM3->PSCR = (uint8_t)TIM3_PSCR_RESET_VALUE;\r
+ TIM3->ARRH = (uint8_t)TIM3_ARRH_RESET_VALUE;\r
+ TIM3->ARRL = (uint8_t)TIM3_ARRL_RESET_VALUE;\r
+ TIM3->CCR1H = (uint8_t)TIM3_CCR1H_RESET_VALUE;\r
+ TIM3->CCR1L = (uint8_t)TIM3_CCR1L_RESET_VALUE;\r
+ TIM3->CCR2H = (uint8_t)TIM3_CCR2H_RESET_VALUE;\r
+ TIM3->CCR2L = (uint8_t)TIM3_CCR2L_RESET_VALUE;\r
+ TIM3->SR1 = (uint8_t)TIM3_SR1_RESET_VALUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM3 Time Base Unit according to the specified parameters.\r
+ * @param TIM3_Prescaler specifies the Prescaler from TIM3_Prescaler_TypeDef.\r
+ * @param TIM3_Period specifies the Period value.\r
+ * @retval None\r
+ */\r
+void TIM3_TimeBaseInit( TIM3_Prescaler_TypeDef TIM3_Prescaler,\r
+ uint16_t TIM3_Period)\r
+{\r
+ /* Set the Prescaler value */\r
+ TIM3->PSCR = (uint8_t)(TIM3_Prescaler);\r
+ /* Set the Autoreload value */\r
+ TIM3->ARRH = (uint8_t)(TIM3_Period >> 8);\r
+ TIM3->ARRL = (uint8_t)(TIM3_Period);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM3 Channel1 according to the specified parameters.\r
+ * @param TIM3_OCMode specifies the Output Compare mode from @ref TIM3_OCMode_TypeDef.\r
+ * @param TIM3_OutputState specifies the Output State from @ref TIM3_OutputState_TypeDef.\r
+ * @param TIM3_Pulse specifies the Pulse width value.\r
+ * @param TIM3_OCPolarity specifies the Output Compare Polarity from @ref TIM3_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,\r
+ TIM3_OutputState_TypeDef TIM3_OutputState,\r
+ uint16_t TIM3_Pulse,\r
+ TIM3_OCPolarity_TypeDef TIM3_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));\r
+ assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));\r
+ assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */\r
+ TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC1E | TIM3_CCER1_CC1P));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState & TIM3_CCER1_CC1E ) | (uint8_t)(TIM3_OCPolarity & TIM3_CCER1_CC1P ));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);\r
+\r
+ /* Set the Pulse value */\r
+ TIM3->CCR1H = (uint8_t)(TIM3_Pulse >> 8);\r
+ TIM3->CCR1L = (uint8_t)(TIM3_Pulse);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM3 Channel2 according to the specified parameters.\r
+ * @param TIM3_OCMode specifies the Output Compare mode from @ref TIM3_OCMode_TypeDef.\r
+ * @param TIM3_OutputState specifies the Output State from @ref TIM3_OutputState_TypeDef.\r
+ * @param TIM3_Pulse specifies the Pulse width value.\r
+ * @param TIM3_OCPolarity specifies the Output Compare Polarity from @ref TIM3_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,\r
+ TIM3_OutputState_TypeDef TIM3_OutputState,\r
+ uint16_t TIM3_Pulse,\r
+ TIM3_OCPolarity_TypeDef TIM3_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_OC_MODE_OK(TIM3_OCMode));\r
+ assert_param(IS_TIM3_OUTPUT_STATE_OK(TIM3_OutputState));\r
+ assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));\r
+\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */\r
+ TIM3->CCER1 &= (uint8_t)(~( TIM3_CCER1_CC2E | TIM3_CCER1_CC2P ));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM3->CCER1 |= (uint8_t)((uint8_t)(TIM3_OutputState & TIM3_CCER1_CC2E ) | (uint8_t)(TIM3_OCPolarity & TIM3_CCER1_CC2P ));\r
+\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);\r
+\r
+\r
+ /* Set the Pulse value */\r
+ TIM3->CCR2H = (uint8_t)(TIM3_Pulse >> 8);\r
+ TIM3->CCR2L = (uint8_t)(TIM3_Pulse);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM3 peripheral according to the specified parameters.\r
+ * @param TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.\r
+ * @param TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.\r
+ * @param TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.\r
+ * @param TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.\r
+ * @param TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,\r
+ TIM3_ICPolarity_TypeDef TIM3_ICPolarity,\r
+ TIM3_ICSelection_TypeDef TIM3_ICSelection,\r
+ TIM3_ICPSC_TypeDef TIM3_ICPrescaler,\r
+ uint8_t TIM3_ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));\r
+ assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));\r
+ assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));\r
+ assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));\r
+ assert_param(IS_TIM3_IC_FILTER_OK(TIM3_ICFilter));\r
+\r
+ if (TIM3_Channel != TIM3_CHANNEL_2)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM3_ICPolarity,\r
+ (uint8_t)TIM3_ICSelection,\r
+ (uint8_t)TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC1Prescaler(TIM3_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM3_ICPolarity,\r
+ (uint8_t)TIM3_ICSelection,\r
+ (uint8_t)TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC2Prescaler(TIM3_ICPrescaler);\r
+ }\r
+}\r
+/**\r
+ * @brief Configures the TIM3 peripheral in PWM Input Mode according to the specified parameters.\r
+ * @param TIM3_Channel specifies the Input Capture Channel from @ref TIM3_Channel_TypeDef.\r
+ * @param TIM3_ICPolarity specifies the Input Capture Polarity from @ref TIM3_ICPolarity_TypeDef.\r
+ * @param TIM3_ICSelection specifies the Input Capture Selection from @ref TIM3_ICSelection_TypeDef.\r
+ * @param TIM3_ICPrescaler specifies the Input Capture Prescaler from @ref TIM3_ICPSC_TypeDef.\r
+ * @param TIM3_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,\r
+ TIM3_ICPolarity_TypeDef TIM3_ICPolarity,\r
+ TIM3_ICSelection_TypeDef TIM3_ICSelection,\r
+ TIM3_ICPSC_TypeDef TIM3_ICPrescaler,\r
+ uint8_t TIM3_ICFilter)\r
+{\r
+ uint8_t icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;\r
+ uint8_t icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_PWMI_CHANNEL_OK(TIM3_Channel));\r
+ assert_param(IS_TIM3_IC_POLARITY_OK(TIM3_ICPolarity));\r
+ assert_param(IS_TIM3_IC_SELECTION_OK(TIM3_ICSelection));\r
+ assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_ICPrescaler));\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM3_ICPolarity != TIM3_ICPOLARITY_FALLING)\r
+ {\r
+ icpolarity = (uint8_t)TIM3_ICPOLARITY_FALLING;\r
+ }\r
+ else\r
+ {\r
+ icpolarity = (uint8_t)TIM3_ICPOLARITY_RISING;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM3_ICSelection == TIM3_ICSELECTION_DIRECTTI)\r
+ {\r
+ icselection = (uint8_t)TIM3_ICSELECTION_INDIRECTTI;\r
+ }\r
+ else\r
+ {\r
+ icselection = (uint8_t)TIM3_ICSELECTION_DIRECTTI;\r
+ }\r
+\r
+ if (TIM3_Channel != TIM3_CHANNEL_2)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,\r
+ (uint8_t)TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC1Prescaler(TIM3_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config(icpolarity, icselection, TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC2Prescaler(TIM3_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM3_ICPolarity, (uint8_t)TIM3_ICSelection,\r
+ (uint8_t)TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC2Prescaler(TIM3_ICPrescaler);\r
+\r
+ /* TI1 Configuration */\r
+ TI1_Config(icpolarity, icselection, TIM3_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM3_SetIC1Prescaler(TIM3_ICPrescaler);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM3 peripheral.\r
+ * @param NewState new state of the TIM3 peripheral. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CR1 |= (uint8_t)TIM3_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CR1 &= (uint8_t)(~TIM3_CR1_CEN);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM3 interrupts.\r
+ * @param NewState new state of the TIM3 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @param TIM3_IT specifies the TIM3 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * - TIM3_IT_UPDATE: TIM3 update Interrupt source\r
+ * - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source\r
+ * - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source\r
+ * - TIM3_IT_CC3: TIM3 Capture Compare 3 Interrupt source\r
+ * @param NewState new state of the TIM3 peripheral. * @retval None\r
+ */\r
+void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_IT_OK(TIM3_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM3->IER |= (uint8_t)TIM3_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM3->IER &= (uint8_t)(~TIM3_IT);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM3 Update event.\r
+ * @param NewState new state of the TIM3 peripheral Preload register. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CR1 |= TIM3_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CR1 &= (uint8_t)(~TIM3_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM3 Update Request Interrupt source.\r
+ * @param TIM3_UpdateSource specifies the Update source.\r
+ * This parameter can be one of the following values\r
+ * - TIM3_UPDATESOURCE_REGULAR\r
+ * - TIM3_UPDATESOURCE_GLOBAL\r
+ * @retval None\r
+ */\r
+void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)\r
+ {\r
+ TIM3->CR1 |= TIM3_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CR1 &= (uint8_t)(~TIM3_CR1_URS);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM3\92s One Pulse Mode.\r
+ * @param TIM3_OPMode specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values\r
+ * - TIM3_OPMODE_SINGLE\r
+ * - TIM3_OPMODE_REPETITIVE\r
+ * @retval None\r
+ */\r
+void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)\r
+ {\r
+ TIM3->CR1 |= TIM3_CR1_OPM;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CR1 &= (uint8_t)(~TIM3_CR1_OPM);\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM3 Prescaler.\r
+ * @param Prescaler specifies the Prescaler Register value\r
+ * This parameter can be one of the following values\r
+ * - TIM3_PRESCALER_1\r
+ * - TIM3_PRESCALER_2\r
+ * - TIM3_PRESCALER_4\r
+ * - TIM3_PRESCALER_8\r
+ * - TIM3_PRESCALER_16\r
+ * - TIM3_PRESCALER_32\r
+ * - TIM3_PRESCALER_64\r
+ * - TIM3_PRESCALER_128\r
+ * - TIM3_PRESCALER_256\r
+ * - TIM3_PRESCALER_512\r
+ * - TIM3_PRESCALER_1024\r
+ * - TIM3_PRESCALER_2048\r
+ * - TIM3_PRESCALER_4096\r
+ * - TIM3_PRESCALER_8192\r
+ * - TIM3_PRESCALER_16384\r
+ * - TIM3_PRESCALER_32768\r
+ * @param TIM3_PSCReloadMode specifies the TIM3 Prescaler Reload mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM3_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded\r
+ * immediatly.\r
+ * - TIM3_PSCRELOADMODE_UPDATE: The Prescaler is loaded at\r
+ * the update event.\r
+ * @retval None\r
+ */\r
+void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,\r
+ TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));\r
+ assert_param(IS_TIM3_PRESCALER_OK(Prescaler));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM3->PSCR = (uint8_t)Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ TIM3->EGR = (uint8_t)TIM3_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM3 Channel1 output waveform to active or inactive level.\r
+ * @param TIM3_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_FORCEDACTION_ACTIVE: Force active level on OC1REF\r
+ * - TIM3_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_ForcedAction);\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM3 Channel2 output waveform to active or inactive level.\r
+ * @param TIM3_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_FORCEDACTION_ACTIVE: Force active level on OC2REF\r
+ * - TIM3_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));\r
+\r
+ /* Reset the OCM Bits & Configure the Forced output Mode */\r
+ TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables TIM3 peripheral Preload register on ARR.\r
+ * @param NewState new state of the TIM3 peripheral Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CR1 |= TIM3_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CR1 &= (uint8_t)(~TIM3_CR1_ARPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM3 peripheral Preload Register on CCR1.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_OC1PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC1PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CCMR1 |= TIM3_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCMR1 &= (uint8_t)(~TIM3_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM3 peripheral Preload Register on CCR2.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_OC2PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC2PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CCMR2 |= TIM3_CCMR_OCxPE;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCMR2 &= (uint8_t)(~TIM3_CCMR_OCxPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM3 event to be generated by software.\r
+ * @param TIM3_EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_EVENTSOURCE_UPDATE: TIM3 update Event source\r
+ * - TIM3_EVENTSOURCE_CC1: TIM3 Capture Compare 1 Event source\r
+ * - TIM3_EVENTSOURCE_CC2: TIM3 Capture Compare 2 Event source\r
+ * @retval None\r
+ */\r
+void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM3->EGR = (uint8_t)TIM3_EventSource;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM3 Channel 1 polarity.\r
+ * @param TIM3_OCPolarity specifies the OC1 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM3_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM3 Channel 2 polarity.\r
+ * @param TIM3_OCPolarity specifies the OC2 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM3_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM3 Capture Compare Channel x.\r
+ * @param TIM3_Channel specifies the TIM3 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_CHANNEL_1: TIM3 Channel1\r
+ * - TIM3_CHANNEL_2: TIM3 Channel2\r
+ * @param NewState specifies the TIM3 Channel CCxE bit new state.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (TIM3_Channel == TIM3_CHANNEL_1)\r
+ {\r
+ /* Set or Reset the CC1E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC1E;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);\r
+ }\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC2E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC2E;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);\r
+ }\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM3 Output Compare Mode. This function disables the\r
+ * selected channel before changing the Output Compare Mode. User has to\r
+ * enable this channel using TIM3_CCxCmd and TIM3_CCxNCmd functions.\r
+ * @param TIM3_Channel specifies the TIM3 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_CHANNEL_1: TIM3 Channel1\r
+ * - TIM3_CHANNEL_2: TIM3 Channel2\r
+ * @param TIM3_OCMode specifies the TIM3 Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * - TIM3_OCMODE_TIMING\r
+ * - TIM3_OCMODE_ACTIVE\r
+ * - TIM3_OCMODE_TOGGLE\r
+ * - TIM3_OCMODE_PWM1\r
+ * - TIM3_OCMODE_PWM2\r
+ * - TIM3_FORCEDACTION_ACTIVE\r
+ * - TIM3_FORCEDACTION_INACTIVE\r
+ * @retval None\r
+ */\r
+void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));\r
+ assert_param(IS_TIM3_OCM_OK(TIM3_OCMode));\r
+\r
+ if (TIM3_Channel == TIM3_CHANNEL_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_OCM)) | (uint8_t)TIM3_OCMode);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM3 Counter Register value.\r
+ * @param Counter specifies the Counter register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM3_SetCounter(uint16_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM3->CNTRH = (uint8_t)(Counter >> 8);\r
+ TIM3->CNTRL = (uint8_t)(Counter);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM3 Autoreload Register value.\r
+ * @param Autoreload specifies the Autoreload register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM3_SetAutoreload(uint16_t Autoreload)\r
+{\r
+ /* Set the Autoreload Register value */\r
+ TIM3->ARRH = (uint8_t)(Autoreload >> 8);\r
+ TIM3->ARRL = (uint8_t)(Autoreload);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM3 Capture Compare1 Register value.\r
+ * @param Compare1 specifies the Capture Compare1 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM3_SetCompare1(uint16_t Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIM3->CCR1H = (uint8_t)(Compare1 >> 8);\r
+ TIM3->CCR1L = (uint8_t)(Compare1);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM3 Capture Compare2 Register value.\r
+ * @param Compare2 specifies the Capture Compare2 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM3_SetCompare2(uint16_t Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIM3->CCR2H = (uint8_t)(Compare2 >> 8);\r
+ TIM3->CCR2L = (uint8_t)(Compare2);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM3 Input Capture 1 prescaler.\r
+ * @param TIM3_IC1Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICPSC_DIV1: no prescaler\r
+ * - TIM3_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM3_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM3_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC1Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits & Set the IC1PSC value */\r
+ TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC1Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM3 Input Capture 2 prescaler.\r
+ * @param TIM3_IC2Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICPSC_DIV1: no prescaler\r
+ * - TIM3_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM3_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM3_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC2Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits & Set the IC1PSC value */\r
+ TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~TIM3_CCMR_ICxPSC)) | (uint8_t)TIM3_IC2Prescaler);\r
+}\r
+/**\r
+ * @brief Gets the TIM3 Input Capture 1 value.\r
+ * @param None\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM3_GetCapture1(void)\r
+{\r
+ /* Get the Capture 1 Register value */\r
+ uint16_t tmpccr1 = 0;\r
+ uint8_t tmpccr1l=0, tmpccr1h=0;\r
+\r
+ tmpccr1h = TIM3->CCR1H;\r
+ tmpccr1l = TIM3->CCR1L;\r
+\r
+ tmpccr1 = (uint16_t)(tmpccr1l);\r
+ tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);\r
+ /* Get the Capture 1 Register value */\r
+ return (uint16_t)tmpccr1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM3 Input Capture 2 value.\r
+ * @param None\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM3_GetCapture2(void)\r
+{\r
+ /* Get the Capture 2 Register value */\r
+ uint16_t tmpccr2 = 0;\r
+ uint8_t tmpccr2l=0, tmpccr2h=0;\r
+\r
+ tmpccr2h = TIM3->CCR2H;\r
+ tmpccr2l = TIM3->CCR2L;\r
+\r
+ tmpccr2 = (uint16_t)(tmpccr2l);\r
+ tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);\r
+ /* Get the Capture 2 Register value */\r
+ return (uint16_t)tmpccr2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM3 Counter value.\r
+ * @param None\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM3_GetCounter(void)\r
+{\r
+ uint16_t tmpcntr = 0;\r
+ \r
+ tmpcntr = ((uint16_t)TIM3->CNTRH << 8);\r
+ /* Get the Counter Register value */\r
+ return (uint16_t)( tmpcntr| (uint16_t)(TIM3->CNTRL));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Gets the TIM3 Prescaler value.\r
+ * @param None\r
+ * @retval Prescaler Register configuration value @ref TIM3_Prescaler_TypeDef.\r
+ */\r
+TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return (TIM3_Prescaler_TypeDef)(TIM3->PSCR);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM3 flag is set or not.\r
+ * @param TIM3_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_FLAG_UPDATE: TIM3 update Flag\r
+ * - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag\r
+ * - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag\r
+ * - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag\r
+ * - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag\r
+ * @retval FlagStatus The new state of TIM3_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint8_t tim3_flag_l = 0, tim3_flag_h = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_GET_FLAG_OK(TIM3_FLAG));\r
+\r
+ tim3_flag_l = (uint8_t)(TIM3->SR1 & (uint8_t)TIM3_FLAG);\r
+ tim3_flag_h = (uint8_t)((uint16_t)TIM3_FLAG >> 8);\r
+\r
+ if (((tim3_flag_l) | (uint8_t)(TIM3->SR2 & tim3_flag_h)) != (uint8_t)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (FlagStatus)bitstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM3\92s pending flags.\r
+ * @param TIM3_FLAG specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_FLAG_UPDATE: TIM3 update Flag\r
+ * - TIM3_FLAG_CC1: TIM3 Capture Compare 1 Flag\r
+ * - TIM3_FLAG_CC2: TIM3 Capture Compare 2 Flag\r
+ * - TIM3_FLAG_CC1OF: TIM3 Capture Compare 1 over capture Flag\r
+ * - TIM3_FLAG_CC2OF: TIM3 Capture Compare 2 over capture Flag\r
+ * @retval None.\r
+ */\r
+void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_CLEAR_FLAG_OK(TIM3_FLAG));\r
+\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM3->SR1 = (uint8_t)(~((uint8_t)(TIM3_FLAG)));\r
+ TIM3->SR2 = (uint8_t)(~((uint8_t)((uint16_t)TIM3_FLAG >> 8)));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Checks whether the TIM3 interrupt has occurred or not.\r
+ * @param TIM3_IT specifies the TIM3 interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_IT_UPDATE: TIM3 update Interrupt source\r
+ * - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source\r
+ * - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source\r
+ * @retval ITStatus The new state of the TIM3_IT(SET or RESET).\r
+ */\r
+\r
+ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint8_t TIM3_itStatus = 0, TIM3_itEnable = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_GET_IT_OK(TIM3_IT));\r
+\r
+ TIM3_itStatus = (uint8_t)(TIM3->SR1 & TIM3_IT);\r
+\r
+ TIM3_itEnable = (uint8_t)(TIM3->IER & TIM3_IT);\r
+\r
+ if ((TIM3_itStatus != (uint8_t)RESET ) && (TIM3_itEnable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (ITStatus)(bitstatus);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM3's interrupt pending bits.\r
+ * @param TIM3_IT specifies the pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_IT_UPDATE: TIM3 update Interrupt source\r
+ * - TIM3_IT_CC1: TIM3 Capture Compare 1 Interrupt source\r
+ * - TIM3_IT_CC2: TIM3 Capture Compare 2 Interrupt source\r
+ * @retval None.\r
+ */\r
+void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM3_IT_OK(TIM3_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM3->SR1 = (uint8_t)(~TIM3_IT);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIM3_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICPOLARITY_FALLING\r
+ * - TIM3_ICPOLARITY_RISING\r
+ * @param TIM3_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 1 is selected to\r
+ * be connected to IC1.\r
+ * - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 1 is selected to\r
+ * be connected to IC2.\r
+ * @param TIM3_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(uint8_t TIM3_ICPolarity,\r
+ uint8_t TIM3_ICSelection,\r
+ uint8_t TIM3_ICFilter)\r
+{\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM3->CCMR1 = (uint8_t)((uint8_t)(TIM3->CCMR1 & (uint8_t)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF))) | (uint8_t)(( (TIM3_ICSelection)) | ((uint8_t)( TIM3_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC1P;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC1P);\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM3->CCER1 |= TIM3_CCER1_CC1E;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIM3_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICPOLARITY_FALLING\r
+ * - TIM3_ICPOLARITY_RISING\r
+ * @param TIM3_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM3_ICSELECTION_DIRECTTI: TIM3 Input 2 is selected to\r
+ * be connected to IC2.\r
+ * - TIM3_ICSELECTION_INDIRECTTI: TIM3 Input 2 is selected to\r
+ * be connected to IC1.\r
+ * @param TIM3_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(uint8_t TIM3_ICPolarity,\r
+ uint8_t TIM3_ICSelection,\r
+ uint8_t TIM3_ICFilter)\r
+{\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM3->CCMR2 = (uint8_t)((uint8_t)(TIM3->CCMR2 & (uint8_t)(~( TIM3_CCMR_CCxS |\r
+ TIM3_CCMR_ICxF ))) | (uint8_t)(( (TIM3_ICSelection)) | \r
+ ((uint8_t)( TIM3_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)\r
+ {\r
+ TIM3->CCER1 |= TIM3_CCER1_CC2P;\r
+ }\r
+ else\r
+ {\r
+ TIM3->CCER1 &= (uint8_t)(~TIM3_CCER1_CC2P);\r
+ }\r
+\r
+ /* Set the CCE Bit */\r
+ TIM3->CCER1 |= TIM3_CCER1_CC2E;\r
+\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim4.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM4 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim4.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/**\r
+ * @addtogroup TIM4_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM4 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM4_DeInit(void)\r
+{\r
+ TIM4->CR1 = TIM4_CR1_RESET_VALUE;\r
+ TIM4->IER = TIM4_IER_RESET_VALUE;\r
+ TIM4->CNTR = TIM4_CNTR_RESET_VALUE;\r
+ TIM4->PSCR = TIM4_PSCR_RESET_VALUE;\r
+ TIM4->ARR = TIM4_ARR_RESET_VALUE;\r
+ TIM4->SR1 = TIM4_SR1_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM4 Time Base Unit according to the specified parameters.\r
+ * @param TIM4_Prescaler specifies the Prescaler from TIM4_Prescaler_TypeDef.\r
+ * @param TIM4_Period specifies the Period value.\r
+ * @retval None\r
+ */\r
+void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period)\r
+{\r
+ /* Check TIM4 prescaler value */\r
+ assert_param(IS_TIM4_PRESCALER_OK(TIM4_Prescaler));\r
+ /* Set the Prescaler value */\r
+ TIM4->PSCR = (uint8_t)(TIM4_Prescaler);\r
+ /* Set the Autoreload value */\r
+ TIM4->ARR = (uint8_t)(TIM4_Period);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM4 peripheral.\r
+ * @param NewState new state of the TIM4 peripheral. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM4_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM4->CR1 |= TIM4_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM4 interrupts.\r
+ * @param NewState new state of the TIM4 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @param TIM4_IT specifies the TIM4 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * - TIM4_IT_UPDATE: TIM4 update Interrupt source\r
+ * @param NewState new state of the TIM4 peripheral.\r
+ * @retval None\r
+ */\r
+void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_IT_OK(TIM4_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM4->IER |= (uint8_t)TIM4_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM4->IER &= (uint8_t)(~TIM4_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM4 Update event.\r
+ * @param NewState new state of the TIM4 peripheral Preload register. This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM4_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM4->CR1 |= TIM4_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM4 Update Request Interrupt source.\r
+ * @param TIM4_UpdateSource specifies the Update source.\r
+ * This parameter can be one of the following values\r
+ * - TIM4_UPDATESOURCE_REGULAR\r
+ * - TIM4_UPDATESOURCE_GLOBAL\r
+ * @retval None\r
+ */\r
+void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_UPDATE_SOURCE_OK(TIM4_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM4_UpdateSource != TIM4_UPDATESOURCE_GLOBAL)\r
+ {\r
+ TIM4->CR1 |= TIM4_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM4\92s One Pulse Mode.\r
+ * @param TIM4_OPMode specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values\r
+ * - TIM4_OPMODE_SINGLE\r
+ * - TIM4_OPMODE_REPETITIVE\r
+ * @retval None\r
+ */\r
+void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_OPM_MODE_OK(TIM4_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM4_OPMode != TIM4_OPMODE_REPETITIVE)\r
+ {\r
+ TIM4->CR1 |= TIM4_CR1_OPM;\r
+ }\r
+ else\r
+ {\r
+ TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM4 Prescaler.\r
+ * @param Prescaler specifies the Prescaler Register value\r
+ * This parameter can be one of the following values\r
+ * - TIM4_PRESCALER_1\r
+ * - TIM4_PRESCALER_2\r
+ * - TIM4_PRESCALER_4\r
+ * - TIM4_PRESCALER_8\r
+ * - TIM4_PRESCALER_16\r
+ * - TIM4_PRESCALER_32\r
+ * - TIM4_PRESCALER_64\r
+ * - TIM4_PRESCALER_128\r
+ * @param TIM4_PSCReloadMode specifies the TIM4 Prescaler Reload mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM4_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded\r
+ * immediatly.\r
+ * - TIM4_PSCRELOADMODE_UPDATE: The Prescaler is loaded at\r
+ * the update event.\r
+ * @retval None\r
+ */\r
+void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_PRESCALER_RELOAD_OK(TIM4_PSCReloadMode));\r
+ assert_param(IS_TIM4_PRESCALER_OK(Prescaler));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM4->PSCR = (uint8_t)Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ TIM4->EGR = (uint8_t)TIM4_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIM4 peripheral Preload register on ARR.\r
+ * @param NewState new state of the TIM4 peripheral Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM4_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM4->CR1 |= TIM4_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM4 event to be generated by software.\r
+ * @param TIM4_EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM4_EVENTSOURCE_UPDATE: TIM4 update Event source\r
+ * @retval None\r
+ */\r
+void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_EVENT_SOURCE_OK(TIM4_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM4->EGR = (uint8_t)(TIM4_EventSource);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM4 Counter Register value.\r
+ * @param Counter specifies the Counter register new value.\r
+ * This parameter is between 0x00 and 0xFF.\r
+ * @retval None\r
+ */\r
+void TIM4_SetCounter(uint8_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM4->CNTR = (uint8_t)(Counter);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM4 Autoreload Register value.\r
+ * @param Autoreload specifies the Autoreload register new value.\r
+ * This parameter is between 0x00 and 0xFF.\r
+ * @retval None\r
+ */\r
+void TIM4_SetAutoreload(uint8_t Autoreload)\r
+{\r
+ /* Set the Autoreload Register value */\r
+ TIM4->ARR = (uint8_t)(Autoreload);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM4 Counter value.\r
+ * @param None\r
+ * @retval Counter Register value.\r
+ */\r
+uint8_t TIM4_GetCounter(void)\r
+{\r
+ /* Get the Counter Register value */\r
+ return (uint8_t)(TIM4->CNTR);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM4 Prescaler value.\r
+ * @param None\r
+ * @retval Prescaler Register configuration value.\r
+ */\r
+TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return (TIM4_Prescaler_TypeDef)(TIM4->PSCR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM4 flag is set or not.\r
+ * @param TIM4_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM4_FLAG_UPDATE: TIM4 update Flag\r
+ * @retval FlagStatus The new state of TIM4_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));\r
+\r
+ if ((TIM4->SR1 & (uint8_t)TIM4_FLAG) != 0)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return ((FlagStatus)bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM4\92s pending flags.\r
+ * @param TIM4_FLAG specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM4_FLAG_UPDATE: TIM4 update Flag\r
+ * @retval None.\r
+ */\r
+void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));\r
+\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM4->SR1 = (uint8_t)(~TIM4_FLAG);\r
+\r
+}\r
+/**\r
+ * @brief Checks whether the TIM4 interrupt has occurred or not.\r
+ * @param TIM4_IT specifies the TIM4 interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM4_IT_UPDATE: TIM4 update Interrupt source\r
+ * @retval ITStatus The new state of the TIM4_IT (SET or RESET).\r
+ */\r
+\r
+ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+\r
+ uint8_t itstatus = 0x0, itenable = 0x0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_IT_OK(TIM4_IT));\r
+\r
+ itstatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);\r
+\r
+ itenable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);\r
+\r
+ if ((itstatus != (uint8_t)RESET ) && (itenable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = (ITStatus)SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (ITStatus)RESET;\r
+ }\r
+ return ((ITStatus)bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM4's interrupt pending bits.\r
+ * @param TIM4_IT specifies the pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM4_IT_UPDATE: TIM4 update Interrupt source\r
+ * @retval None.\r
+ */\r
+void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM4_IT_OK(TIM4_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM4->SR1 = (uint8_t)(~TIM4_IT);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim5.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM5 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim5.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+static void TI1_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);\r
+static void TI2_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);\r
+static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter);\r
+/**\r
+ * @addtogroup TIM5_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM5 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM5_DeInit(void)\r
+{\r
+\r
+ TIM5->CR1 = (uint8_t)TIM5_CR1_RESET_VALUE;\r
+ TIM5->CR2 = TIM5_CR2_RESET_VALUE;\r
+ TIM5->SMCR = TIM5_SMCR_RESET_VALUE;\r
+ TIM5->IER = (uint8_t)TIM5_IER_RESET_VALUE;\r
+ TIM5->SR2 = (uint8_t)TIM5_SR2_RESET_VALUE;\r
+\r
+ /* Disable channels */\r
+ TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;\r
+ TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;\r
+\r
+\r
+ /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */\r
+ TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE;\r
+ TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE;\r
+ TIM5->CCMR1 = (uint8_t)TIM5_CCMR1_RESET_VALUE;\r
+ TIM5->CCMR2 = (uint8_t)TIM5_CCMR2_RESET_VALUE;\r
+ TIM5->CCMR3 = (uint8_t)TIM5_CCMR3_RESET_VALUE;\r
+ TIM5->CNTRH = (uint8_t)TIM5_CNTRH_RESET_VALUE;\r
+ TIM5->CNTRL = (uint8_t)TIM5_CNTRL_RESET_VALUE;\r
+ TIM5->PSCR = (uint8_t)TIM5_PSCR_RESET_VALUE;\r
+ TIM5->ARRH = (uint8_t)TIM5_ARRH_RESET_VALUE;\r
+ TIM5->ARRL = (uint8_t)TIM5_ARRL_RESET_VALUE;\r
+ TIM5->CCR1H = (uint8_t)TIM5_CCR1H_RESET_VALUE;\r
+ TIM5->CCR1L = (uint8_t)TIM5_CCR1L_RESET_VALUE;\r
+ TIM5->CCR2H = (uint8_t)TIM5_CCR2H_RESET_VALUE;\r
+ TIM5->CCR2L = (uint8_t)TIM5_CCR2L_RESET_VALUE;\r
+ TIM5->CCR3H = (uint8_t)TIM5_CCR3H_RESET_VALUE;\r
+ TIM5->CCR3L = (uint8_t)TIM5_CCR3L_RESET_VALUE;\r
+ TIM5->SR1 = (uint8_t)TIM5_SR1_RESET_VALUE;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM5 Time Base Unit according to the specified parameters.\r
+ * @param TIM5_Prescaler specifies the Prescaler from TIM5_Prescaler_TypeDef.\r
+ * @param TIM5_Period specifies the Period value.\r
+ * @retval None\r
+ */\r
+void TIM5_TimeBaseInit( TIM5_Prescaler_TypeDef TIM5_Prescaler,\r
+ uint16_t TIM5_Period)\r
+{\r
+ /* Set the Prescaler value */\r
+ TIM5->PSCR = (uint8_t)(TIM5_Prescaler);\r
+ /* Set the Autoreload value */\r
+ TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ;\r
+ TIM5->ARRL = (uint8_t)(TIM5_Period);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM5 Channel1 according to the specified parameters.\r
+ * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef.\r
+ * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef.\r
+ * @param TIM5_Pulse specifies the Pulse width value.\r
+ * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,\r
+ TIM5_OutputState_TypeDef TIM5_OutputState,\r
+ uint16_t TIM5_Pulse,\r
+ TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));\r
+ assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */\r
+ TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC1E | TIM5_CCER1_CC1P));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC1E )| \r
+ (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC1P));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) | \r
+ (uint8_t)TIM5_OCMode);\r
+\r
+ /* Set the Pulse value */\r
+ TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8);\r
+ TIM5->CCR1L = (uint8_t)(TIM5_Pulse);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM5 Channel2 according to the specified parameters.\r
+ * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef.\r
+ * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef.\r
+ * @param TIM5_Pulse specifies the Pulse width value.\r
+ * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,\r
+ TIM5_OutputState_TypeDef TIM5_OutputState,\r
+ uint16_t TIM5_Pulse,\r
+ TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));\r
+ assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+\r
+\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */\r
+ TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC2E | TIM5_CCER1_CC2P ));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC2E )| \\r
+ (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC2P));\r
+\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) |\r
+ (uint8_t)TIM5_OCMode);\r
+\r
+\r
+ /* Set the Pulse value */\r
+ TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8);\r
+ TIM5->CCR2L = (uint8_t)(TIM5_Pulse);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM5 Channel3 according to the specified parameters.\r
+ * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef.\r
+ * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef.\r
+ * @param TIM5_Pulse specifies the Pulse width value.\r
+ * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef.\r
+ * @retval None\r
+ */\r
+void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode,\r
+ TIM5_OutputState_TypeDef TIM5_OutputState,\r
+ uint16_t TIM5_Pulse,\r
+ TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode));\r
+ assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState));\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+ /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */\r
+ TIM5->CCER2 &= (uint8_t)(~( TIM5_CCER2_CC3E | TIM5_CCER2_CC3P));\r
+ /* Set the Output State & Set the Output Polarity */\r
+ TIM5->CCER2 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER2_CC3E )|\r
+ (uint8_t)(TIM5_OCPolarity & TIM5_CCER2_CC3P ));\r
+\r
+ /* Reset the Output Compare Bits & Set the Output Compare Mode */\r
+ TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) | (uint8_t)TIM5_OCMode);\r
+\r
+ /* Set the Pulse value */\r
+ TIM5->CCR3H = (uint8_t)(TIM5_Pulse >> 8);\r
+ TIM5->CCR3L = (uint8_t)(TIM5_Pulse);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the TIM5 peripheral according to the specified parameters.\r
+ * @param TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.\r
+ * @param TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.\r
+ * @param TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.\r
+ * @param TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.\r
+ * @param TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,\r
+ TIM5_ICPolarity_TypeDef TIM5_ICPolarity,\r
+ TIM5_ICSelection_TypeDef TIM5_ICSelection,\r
+ TIM5_ICPSC_TypeDef TIM5_ICPrescaler,\r
+ uint8_t TIM5_ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));\r
+ assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));\r
+ assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));\r
+ assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));\r
+ assert_param(IS_TIM5_IC_FILTER_OK(TIM5_ICFilter));\r
+\r
+ if (TIM5_Channel == TIM5_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM5_ICPolarity,\r
+ (uint8_t)TIM5_ICSelection,\r
+ (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC1Prescaler(TIM5_ICPrescaler);\r
+ }\r
+ else if (TIM5_Channel == TIM5_CHANNEL_2)\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM5_ICPolarity,\r
+ (uint8_t)TIM5_ICSelection,\r
+ (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC2Prescaler(TIM5_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI3 Configuration */\r
+ TI3_Config((uint8_t)TIM5_ICPolarity,\r
+ (uint8_t)TIM5_ICSelection,\r
+ (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC3Prescaler(TIM5_ICPrescaler);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters.\r
+ * @param TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef.\r
+ * @param TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef.\r
+ * @param TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef.\r
+ * @param TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef.\r
+ * @param TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F).\r
+ * @retval None\r
+ */\r
+void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,\r
+ TIM5_ICPolarity_TypeDef TIM5_ICPolarity,\r
+ TIM5_ICSelection_TypeDef TIM5_ICSelection,\r
+ TIM5_ICPSC_TypeDef TIM5_ICPrescaler,\r
+ uint8_t TIM5_ICFilter)\r
+{\r
+ uint8_t icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;\r
+ uint8_t icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_PWMI_CHANNEL_OK(TIM5_Channel));\r
+ assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity));\r
+ assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection));\r
+ assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler));\r
+\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM5_ICPolarity != TIM5_ICPOLARITY_FALLING)\r
+ {\r
+ icpolarity = (uint8_t)TIM5_ICPOLARITY_FALLING;\r
+ }\r
+ else\r
+ {\r
+ icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING;\r
+ }\r
+\r
+ /* Select the Opposite Input */\r
+ if (TIM5_ICSelection == TIM5_ICSELECTION_DIRECTTI)\r
+ {\r
+ icselection = (uint8_t)TIM5_ICSELECTION_INDIRECTTI;\r
+ }\r
+ else\r
+ {\r
+ icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI;\r
+ }\r
+\r
+ if (TIM5_Channel == TIM5_CHANNEL_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,\r
+ (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC1Prescaler(TIM5_ICPrescaler);\r
+\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC2Prescaler(TIM5_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ /* TI2 Configuration */\r
+ TI2_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection,\r
+ (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC2Prescaler(TIM5_ICPrescaler);\r
+\r
+ /* TI1 Configuration */\r
+ TI1_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter);\r
+\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM5_SetIC1Prescaler(TIM5_ICPrescaler);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM5 peripheral.\r
+ * @param NewState new state of the TIM5 peripheral.This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CR1 |= TIM5_CR1_CEN ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CR1 &= (uint8_t)(~TIM5_CR1_CEN) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM5 interrupts.\r
+ * @param NewState new state of the TIM5 peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @param TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * - TIM5_IT_UPDATE: TIM5 update Interrupt source\r
+ * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source\r
+ * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source\r
+ * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source\r
+ * @param NewState new state of the TIM5 peripheral.\r
+ * @retval None\r
+ */\r
+void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_IT_OK(TIM5_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM5->IER |= (uint8_t)TIM5_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM5->IER &= (uint8_t)(~TIM5_IT);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM5 Update event.\r
+ * @param NewState new state of the TIM5 peripheral Preload register.This parameter can\r
+ * be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CR1 |= TIM5_CR1_UDIS ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CR1 &= (uint8_t)(~TIM5_CR1_UDIS) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM5 Update Request Interrupt source.\r
+ * @param TIM5_UpdateSource specifies the Update source.\r
+ * This parameter can be one of the following values\r
+ * - TIM5_UPDATESOURCE_REGULAR\r
+ * - TIM5_UPDATESOURCE_GLOBAL\r
+ * @retval None\r
+ */\r
+void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_UPDATE_SOURCE_OK(TIM5_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM5_UpdateSource != TIM5_UPDATESOURCE_GLOBAL)\r
+ {\r
+ TIM5->CR1 |= TIM5_CR1_URS ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CR1 &= (uint8_t)(~TIM5_CR1_URS) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Selects the TIM5\92s One Pulse Mode.\r
+ * @param TIM5_OPMode specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values\r
+ * - TIM5_OPMODE_SINGLE\r
+ * - TIM5_OPMODE_REPETITIVE\r
+ * @retval None\r
+ */\r
+void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OPM_MODE_OK(TIM5_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM5_OPMode != TIM5_OPMODE_REPETITIVE)\r
+ {\r
+ TIM5->CR1 |= TIM5_CR1_OPM ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CR1 &= (uint8_t)(~TIM5_CR1_OPM) ;\r
+ }\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 Prescaler.\r
+ * @param Prescaler specifies the Prescaler Register value\r
+ * This parameter can be one of the following values\r
+ * - TIM5_PRESCALER_1\r
+ * - TIM5_PRESCALER_2\r
+ * - TIM5_PRESCALER_4\r
+ * - TIM5_PRESCALER_8\r
+ * - TIM5_PRESCALER_16\r
+ * - TIM5_PRESCALER_32\r
+ * - TIM5_PRESCALER_64\r
+ * - TIM5_PRESCALER_128\r
+ * - TIM5_PRESCALER_256\r
+ * - TIM5_PRESCALER_512\r
+ * - TIM5_PRESCALER_1024\r
+ * - TIM5_PRESCALER_2048\r
+ * - TIM5_PRESCALER_4096\r
+ * - TIM5_PRESCALER_8192\r
+ * - TIM5_PRESCALER_16384\r
+ * - TIM5_PRESCALER_32768\r
+ * @param TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode.\r
+ * This parameter can be one of the following values\r
+ * - TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded\r
+ * immediatly.\r
+ * - TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at\r
+ * the update event.\r
+ * @retval None\r
+ */\r
+void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,\r
+ TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_PRESCALER_RELOAD_OK(TIM5_PSCReloadMode));\r
+ assert_param(IS_TIM5_PRESCALER_OK(Prescaler));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM5->PSCR = (uint8_t)Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ TIM5->EGR = (uint8_t)TIM5_PSCReloadMode ;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM5 Channel1 output waveform to active or inactive level.\r
+ * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF\r
+ * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));\r
+\r
+ /* Reset the OCM Bits */ /* Configure The Forced output Mode */\r
+ TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM))\r
+ | (uint8_t)TIM5_ForcedAction);\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM5 Channel2 output waveform to active or inactive level.\r
+ * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF\r
+ * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));\r
+\r
+ /* Reset the OCM Bits */ /* Configure The Forced output Mode */\r
+ TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))\r
+ | (uint8_t)TIM5_ForcedAction);\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIM5 Channel3 output waveform to active or inactive level.\r
+ * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF\r
+ * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on\r
+ * OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));\r
+\r
+ /* Reset the OCM Bits */ /* Configure The Forced output Mode */\r
+ TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) \r
+ | (uint8_t)TIM5_ForcedAction);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables TIM5 peripheral Preload register on ARR.\r
+ * @param NewState new state of the TIM5 peripheral Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CR1 |= TIM5_CR1_ARPE ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CR1 &= (uint8_t)(~TIM5_CR1_ARPE) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM5 peripheral Preload Register on CCR1.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_OC1PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC1PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCMR1 |= TIM5_CCMR_OCxPE ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCMR1 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM5 peripheral Preload Register on CCR2.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_OC2PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC2PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCMR2 |= TIM5_CCMR_OCxPE ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCMR2 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM5 peripheral Preload Register on CCR3.\r
+ * @param NewState new state of the Capture Compare Preload register.\r
+ * This parameter can be ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_OC3PreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the OC3PE Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCMR3 |= TIM5_CCMR_OCxPE ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCMR3 &= (uint8_t)(~TIM5_CCMR_OCxPE) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 event to be generated by software.\r
+ * @param TIM5_EventSource specifies the event source.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source\r
+ * - TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source\r
+ * - TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source\r
+ * - TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source\r
+ * @retval None\r
+ */\r
+void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_EVENT_SOURCE_OK(TIM5_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM5->EGR = (uint8_t)TIM5_EventSource;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 Channel 1 polarity.\r
+ * @param TIM5_OCPolarity specifies the OC1 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM5_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+\r
+ /* Set or Reset the CC1P Bit */\r
+ if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC1P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 Channel 2 polarity.\r
+ * @param TIM5_OCPolarity specifies the OC2 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM5_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+\r
+ /* Set or Reset the CC2P Bit */\r
+ if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC2P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the TIM5 Channel 3 polarity.\r
+ * @param TIM5_OCPolarity specifies the OC3 Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_OCPOLARITY_LOW: Output Compare active low\r
+ * - TIM5_OCPOLARITY_HIGH: Output Compare active high\r
+ * @retval None\r
+ */\r
+void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));\r
+\r
+ /* Set or Reset the CC3P Bit */\r
+ if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)\r
+ {\r
+ TIM5->CCER2 |= TIM5_CCER2_CC3P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the TIM5 Capture Compare Channel x.\r
+ * @param TIM5_Channel specifies the TIM5 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_Channel1: TIM5 Channel1\r
+ * - TIM5_Channel2: TIM5 Channel2\r
+ * - TIM5_Channel3: TIM5 Channel3\r
+ * @param NewState specifies the TIM5 Channel CCxE bit new state.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (TIM5_Channel == TIM5_CHANNEL_1)\r
+ {\r
+ /* Set or Reset the CC1E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC1E ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E) ;\r
+ }\r
+\r
+ }\r
+ else if (TIM5_Channel == TIM5_CHANNEL_2)\r
+ {\r
+ /* Set or Reset the CC2E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC2E;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E) ;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Set or Reset the CC3E Bit */\r
+ if (NewState != DISABLE)\r
+ {\r
+ TIM5->CCER2 |= TIM5_CCER2_CC3E;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E) ;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM5 Output Compare Mode. This function disables the\r
+ * selected channel before changing the Output Compare Mode. User has to\r
+ * enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions.\r
+ * @param TIM5_Channel specifies the TIM5 Channel.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_Channel1: TIM5 Channel1\r
+ * - TIM5_Channel2: TIM5 Channel2\r
+ * - TIM5_Channel3: TIM5 Channel3\r
+ * @param TIM5_OCMode specifies the TIM5 Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * - TIM5_OCMODE_TIMING\r
+ * - TIM5_OCMODE_ACTIVE\r
+ * - TIM5_OCMODE_TOGGLE\r
+ * - TIM5_OCMODE_PWM1\r
+ * - TIM5_OCMODE_PWM2\r
+ * - TIM5_FORCEDACTION_ACTIVE\r
+ * - TIM5_FORCEDACTION_INACTIVE\r
+ * @retval None\r
+ */\r
+void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel));\r
+ assert_param(IS_TIM5_OCM_OK(TIM5_OCMode));\r
+\r
+ if (TIM5_Channel == TIM5_CHANNEL_1)\r
+ {\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);\r
+\r
+ /* Reset the Output Compare Bits Set the Output Compare Mode */\r
+ TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) \r
+ | (uint8_t)TIM5_OCMode);\r
+ }\r
+ else if (TIM5_Channel == TIM5_CHANNEL_2)\r
+ {\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E);\r
+\r
+ /* Reset the Output Compare Bits ** Set the Output Compare Mode */\r
+ TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM))\r
+ | (uint8_t)TIM5_OCMode);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E);\r
+\r
+ /* Reset the Output Compare Bits ** Set the Output Compare Mode */\r
+ TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM))\r
+ | (uint8_t)TIM5_OCMode);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Counter Register value.\r
+ * @param Counter specifies the Counter register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM5_SetCounter(uint16_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM5->CNTRH = (uint8_t)(Counter >> 8);\r
+ TIM5->CNTRL = (uint8_t)(Counter);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Autoreload Register value.\r
+ * @param Autoreload specifies the Autoreload register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM5_SetAutoreload(uint16_t Autoreload)\r
+{\r
+\r
+ /* Set the Autoreload Register value */\r
+ TIM5->ARRH = (uint8_t)(Autoreload >> 8);\r
+ TIM5->ARRL = (uint8_t)(Autoreload);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Capture Compare1 Register value.\r
+ * @param Compare1 specifies the Capture Compare1 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM5_SetCompare1(uint16_t Compare1)\r
+{\r
+ /* Set the Capture Compare1 Register value */\r
+ TIM5->CCR1H = (uint8_t)(Compare1 >> 8);\r
+ TIM5->CCR1L = (uint8_t)(Compare1);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Capture Compare2 Register value.\r
+ * @param Compare2 specifies the Capture Compare2 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM5_SetCompare2(uint16_t Compare2)\r
+{\r
+ /* Set the Capture Compare2 Register value */\r
+ TIM5->CCR2H = (uint8_t)(Compare2 >> 8);\r
+ TIM5->CCR2L = (uint8_t)(Compare2);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Capture Compare3 Register value.\r
+ * @param Compare3 specifies the Capture Compare3 register new value.\r
+ * This parameter is between 0x0000 and 0xFFFF.\r
+ * @retval None\r
+ */\r
+void TIM5_SetCompare3(uint16_t Compare3)\r
+{\r
+ /* Set the Capture Compare3 Register value */\r
+ TIM5->CCR3H = (uint8_t)(Compare3 >> 8);\r
+ TIM5->CCR3L = (uint8_t)(Compare3);\r
+\r
+}\r
+\r
+\r
+/**\r
+ * @brief Sets the TIM5 Input Capture 1 prescaler.\r
+ * @param TIM5_IC1Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPSC_DIV1: no prescaler\r
+ * - TIM5_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM5_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM5_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC1Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */\r
+ TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_ICxPSC))|\r
+ (uint8_t)TIM5_IC1Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM5 Input Capture 2 prescaler.\r
+ * @param TIM5_IC2Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPSC_DIV1: no prescaler\r
+ * - TIM5_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM5_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM5_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC2Prescaler));\r
+\r
+ /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */\r
+ TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_ICxPSC))\r
+ | (uint8_t)TIM5_IC2Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM5 Input Capture 3 prescaler.\r
+ * @param TIM5_IC3Prescaler specifies the Input Capture prescaler new value\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPSC_DIV1: no prescaler\r
+ * - TIM5_ICPSC_DIV2: capture is done once every 2 events\r
+ * - TIM5_ICPSC_DIV4: capture is done once every 4 events\r
+ * - TIM5_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC3Prescaler));\r
+ /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */\r
+ TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_ICxPSC)) |\r
+ (uint8_t)TIM5_IC3Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM5 Input Capture 1 value.\r
+ * @param None\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM5_GetCapture1(void)\r
+{\r
+ uint16_t temp = 0; \r
+ \r
+ temp = ((uint16_t)TIM5->CCR1H << 8); \r
+ \r
+ /* Get the Capture 1 Register value */\r
+ return (uint16_t)(temp | (uint16_t)(TIM5->CCR1L));\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM5 Input Capture 2 value.\r
+ * @param None\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM5_GetCapture2(void)\r
+{\r
+ uint16_t temp = 0; \r
+ \r
+ temp = ((uint16_t)TIM5->CCR2H << 8); \r
+ \r
+ /* Get the Capture 2 Register value */\r
+ return (uint16_t)(temp | (uint16_t)(TIM5->CCR2L));\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM5 Input Capture 3 value.\r
+ * @param None\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint16_t TIM5_GetCapture3(void)\r
+{\r
+ uint16_t temp = 0; \r
+ \r
+ temp = ((uint16_t)TIM5->CCR3H << 8);\r
+ /* Get the Capture 1 Register value */\r
+ return (uint16_t)(temp | (uint16_t)(TIM5->CCR3L));\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM5 Counter value.\r
+ * @param None\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM5_GetCounter(void)\r
+{\r
+ uint16_t tmpcntr = 0;\r
+\r
+ tmpcntr = ((uint16_t)TIM5->CNTRH << 8); \r
+ /* Get the Counter Register value */\r
+ return (uint16_t)(tmpcntr | (uint16_t)(TIM5->CNTRL));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Gets the TIM5 Prescaler value.\r
+ * @param None\r
+ * @retval Prescaler Register configuration value @ref TIM5_Prescaler_TypeDef .\r
+ */\r
+TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return (TIM5_Prescaler_TypeDef)(TIM5->PSCR);\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM5 flag is set or not.\r
+ * @param TIM5_FLAG specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_FLAG_UPDATE: TIM5 update Flag\r
+ * - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag\r
+ * - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag\r
+ * - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag\r
+ * - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag\r
+ * - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag\r
+ * - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag\r
+ * @retval FlagStatus The new state of TIM5_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint8_t tim5_flag_l, tim5_flag_h;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_GET_FLAG_OK(TIM5_FLAG));\r
+\r
+ tim5_flag_l= (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_FLAG);\r
+ tim5_flag_h= (uint8_t)((uint16_t)TIM5_FLAG >> 8);\r
+\r
+ if (((tim5_flag_l)|(uint8_t)(TIM5->SR2 & tim5_flag_h)) != RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (FlagStatus)bitstatus;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM5\92s pending flags.\r
+ * @param TIM5_FLAG specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_FLAG_UPDATE: TIM5 update Flag\r
+ * - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag\r
+ * - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag\r
+ * - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag\r
+ * - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag\r
+ * - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag\r
+ * - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag\r
+ * @retval None.\r
+ */\r
+void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_CLEAR_FLAG_OK(TIM5_FLAG));\r
+\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM5->SR1 = (uint8_t)(~((uint8_t)(TIM5_FLAG)));\r
+ TIM5->SR2 &= (uint8_t)(~((uint8_t)((uint16_t)TIM5_FLAG >> 8)));\r
+}\r
+\r
+\r
+/**\r
+ * @brief Checks whether the TIM5 interrupt has occurred or not.\r
+ * @param TIM5_IT specifies the TIM5 interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_IT_UPDATE: TIM5 update Interrupt source\r
+ * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source\r
+ * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source\r
+ * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source\r
+ * @retval ITStatus The new state of the TIM5_IT(SET or RESET).\r
+ */\r
+\r
+ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint8_t TIM5_itStatus = 0, TIM5_itEnable = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_GET_IT_OK(TIM5_IT));\r
+\r
+ TIM5_itStatus = (uint8_t)(TIM5->SR1 & TIM5_IT);\r
+\r
+ TIM5_itEnable = (uint8_t)(TIM5->IER & TIM5_IT);\r
+\r
+ if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return (ITStatus)(bitstatus);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Clears the TIM5's interrupt pending bits.\r
+ * @param TIM5_IT specifies the pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_IT_UPDATE: TIM5 update Interrupt source\r
+ * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source\r
+ * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source\r
+ * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source\r
+ * @retval None.\r
+ */\r
+void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_IT_OK(TIM5_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM5->SR1 = (uint8_t)(~TIM5_IT);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIM5_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPOLARITY_FALLING\r
+ * - TIM5_ICPOLARITY_RISING\r
+ * @param TIM5_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to\r
+ * be connected to IC1.\r
+ * - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to\r
+ * be connected to IC2.\r
+ * @param TIM5_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(uint8_t TIM5_ICPolarity,\r
+ uint8_t TIM5_ICSelection,\r
+ uint8_t TIM5_ICFilter)\r
+{\r
+ /* Disable the Channel 1: Reset the CCE Bit */\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF )))\r
+ | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));\r
+\r
+ /* Select the Polarity */\r
+ if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC1P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM5->CCER1 |= TIM5_CCER1_CC1E;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIM5_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPOLARITY_FALLING\r
+ * - TIM5_ICPOLARITY_RISING\r
+ * @param TIM5_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to\r
+ * be connected to IC2.\r
+ * - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to\r
+ * be connected to IC1.\r
+ * @param TIM5_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(uint8_t TIM5_ICPolarity,\r
+ uint8_t TIM5_ICSelection,\r
+ uint8_t TIM5_ICFilter)\r
+{\r
+ /* Disable the Channel 2: Reset the CCE Bit */\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF)))\r
+ | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));\r
+\r
+\r
+ /* Select the Polarity */\r
+ if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC2P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;\r
+ }\r
+\r
+ /* Set the CCE Bit */\r
+ TIM5->CCER1 |= TIM5_CCER1_CC2E;\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIM5_ICPolarity The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICPOLARITY_FALLING\r
+ * - TIM5_ICPOLARITY_RISING\r
+ * @param TIM5_ICSelection specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to\r
+ * be connected to IC3.\r
+ * @param TIM5_ICFilter Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection,\r
+ uint8_t TIM5_ICFilter)\r
+{\r
+ /* Disable the Channel 3: Reset the CCE Bit */\r
+ TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E);\r
+\r
+ /* Select the Input and set the filter */\r
+ TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF))) \r
+ | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4))));\r
+\r
+\r
+ /* Select the Polarity */\r
+ if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING)\r
+ {\r
+ TIM5->CCER2 |= TIM5_CCER2_CC3P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ;\r
+ }\r
+ /* Set the CCE Bit */\r
+ TIM5->CCER2 |= TIM5_CCER2_CC3E;\r
+}\r
+/**\r
+ * @brief Enables the TIM5 internal Clock.\r
+ * @par Parameters:\r
+ * None\r
+ * @retval None\r
+ */\r
+void TIM5_InternalClockConfig(void)\r
+{\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIM5->SMCR &= (uint8_t)(~TIM5_SMCR_SMS);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM5 Trigger Output Mode.\r
+ * @param TIM5_TRGOSource : Specifies the Trigger Output source.\r
+ * This parameter can be one of the @ref TIM5_TRGOSource_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource)\r
+{\r
+ uint8_t tmpcr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_TRGO_SOURCE_OK(TIM5_TRGOSource));\r
+\r
+ tmpcr2 = TIM5->CR2;\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= (uint8_t)(~TIM5_CR2_MMS);\r
+\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= (uint8_t)TIM5_TRGOSource;\r
+\r
+ TIM5->CR2 = tmpcr2;\r
+}\r
+/**\r
+ * @brief Selects the TIM5 Slave Mode.\r
+ * @param TIM5_SlaveMode : Specifies the TIM5 Slave Mode.\r
+ * This parameter can be one of the @ref TIM5_SlaveMode_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode)\r
+{\r
+ uint8_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_SLAVE_MODE_OK(TIM5_SlaveMode));\r
+\r
+ tmpsmcr = TIM5->SMCR;\r
+\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint8_t)(~TIM5_SMCR_SMS);\r
+\r
+ /* Select the Slave Mode */\r
+ tmpsmcr |= (uint8_t)TIM5_SlaveMode;\r
+\r
+ TIM5->SMCR = tmpsmcr;\r
+}\r
+/**\r
+ * @brief Selects the TIM5 Input Trigger source.\r
+ * @param TIM5_InputTriggerSource : Specifies Input Trigger source.\r
+ * This parameter can be one of the @ref TIM5_TS_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource)\r
+{\r
+ uint8_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_TRIGGER_SELECTION_OK(TIM5_InputTriggerSource));\r
+\r
+ tmpsmcr = TIM5->SMCR;\r
+\r
+ /* Select the Tgigger Source */\r
+ tmpsmcr &= (uint8_t)(~TIM5_SMCR_TS);\r
+ tmpsmcr |= (uint8_t)TIM5_InputTriggerSource;\r
+\r
+ TIM5->SMCR = (uint8_t)tmpsmcr;\r
+}\r
+/**\r
+ * @brief Configures the TIM5 Encoder Interface.\r
+ * @param TIM5_EncoderMode : Specifies the TIM5 Encoder Mode.\r
+ * This parameter can be one of the @ref TIM5_EncoderMode_TypeDef enumeration.\r
+ * @param TIM5_IC1Polarity : Specifies the IC1 Polarity.\r
+ * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.\r
+ * @param TIM5_IC2Polarity : Specifies the IC2 Polarity.\r
+ * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,\r
+ TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,\r
+ TIM5_ICPolarity_TypeDef TIM5_IC2Polarity)\r
+{\r
+ uint8_t tmpsmcr = 0;\r
+ uint8_t tmpccmr1 = 0;\r
+ uint8_t tmpccmr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM5_ENCODER_MODE_OK(TIM5_EncoderMode));\r
+ assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC1Polarity));\r
+ assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC2Polarity));\r
+\r
+ tmpsmcr = TIM5->SMCR;\r
+ tmpccmr1 = TIM5->CCMR1;\r
+ tmpccmr2 = TIM5->CCMR2;\r
+\r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint8_t)(TIM5_SMCR_MSM | TIM5_SMCR_TS) ;\r
+ tmpsmcr |= (uint8_t)TIM5_EncoderMode;\r
+\r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint8_t)(~TIM5_CCMR_CCxS);\r
+ tmpccmr2 &= (uint8_t)(~TIM5_CCMR_CCxS);\r
+ tmpccmr1 |= TIM5_CCMR_TIxDirect_Set;\r
+ tmpccmr2 |= TIM5_CCMR_TIxDirect_Set;\r
+\r
+ /* Set the TI1 and the TI2 Polarities */\r
+ if (TIM5_IC1Polarity == TIM5_ICPOLARITY_FALLING)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC1P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ;\r
+ }\r
+\r
+ if (TIM5_IC2Polarity == TIM5_ICPOLARITY_FALLING)\r
+ {\r
+ TIM5->CCER1 |= TIM5_CCER1_CC2P ;\r
+ }\r
+ else\r
+ {\r
+ TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ;\r
+ }\r
+\r
+ TIM5->SMCR = tmpsmcr;\r
+ TIM5->CCMR1 = tmpccmr1;\r
+ TIM5->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm8s_tim6.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the TIM6 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_tim6.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/**\r
+ * @addtogroup TIM6_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIM6 peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM6_DeInit(void)\r
+{\r
+ TIM6->CR1 = TIM6_CR1_RESET_VALUE;\r
+ TIM6->CR2 = TIM6_CR2_RESET_VALUE;\r
+ TIM6->SMCR = TIM6_SMCR_RESET_VALUE;\r
+ TIM6->IER = TIM6_IER_RESET_VALUE;\r
+ TIM6->CNTR = TIM6_CNTR_RESET_VALUE;\r
+ TIM6->PSCR = TIM6_PSCR_RESET_VALUE;\r
+ TIM6->ARR = TIM6_ARR_RESET_VALUE;\r
+ TIM6->SR1 = TIM6_SR1_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM6 Time Base Unit according to the specified\r
+ * parameters.\r
+ * @param TIM6_Prescaler : This parameter can be any of the @Ref TIM5_Prescaler_TypeDef enumeration.\r
+ * @param TIM6_Period : This parameter must be a value between 0x00 and 0xFF.\r
+ * @retval None\r
+ */\r
+void TIM6_TimeBaseInit(TIM6_Prescaler_TypeDef TIM6_Prescaler,\r
+ uint8_t TIM6_Period)\r
+{\r
+ /* Check TIM6 prescaler value */\r
+ assert_param(IS_TIM6_PRESCALER_OK(TIM6_Prescaler));\r
+ /* Set the Autoreload value */\r
+ TIM6->ARR = (uint8_t)(TIM6_Period);\r
+ /* Set the Prescaler value */\r
+ TIM6->PSCR = (uint8_t)(TIM6_Prescaler);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM6 peripheral.\r
+ * @param NewState : The new state of the TIM6 peripheral.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* set or Reset the CEN Bit */\r
+ if (NewState == ENABLE)\r
+ {\r
+ TIM6->CR1 |= TIM6_CR1_CEN ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->CR1 &= (uint8_t)(~TIM6_CR1_CEN) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIM6 Update event.\r
+ * @param NewState : The new state of the TIM6 peripheral Preload register.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_UpdateDisableConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the UDIS Bit */\r
+ if (NewState == ENABLE)\r
+ {\r
+ TIM6->CR1 |= TIM6_CR1_UDIS ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->CR1 &= (uint8_t)(~TIM6_CR1_UDIS) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM6 Update Request Interrupt source.\r
+ * @param TIM6_UpdateSource : Specifies the Update source.\r
+ * This parameter can be one of the @ref TIM6_UpdateSource_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_UpdateRequestConfig(TIM6_UpdateSource_TypeDef TIM6_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_UPDATE_SOURCE_OK(TIM6_UpdateSource));\r
+\r
+ /* Set or Reset the URS Bit */\r
+ if (TIM6_UpdateSource == TIM6_UPDATESOURCE_REGULAR)\r
+ {\r
+ TIM6->CR1 |= TIM6_CR1_URS ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->CR1 &= (uint8_t)(~TIM6_CR1_URS) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM6\92s One Pulse Mode.\r
+ * @param TIM6_OPMode : Specifies the OPM Mode to be used.\r
+ * This parameter can be one of the @ref TIM6_OPMode_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_SelectOnePulseMode(TIM6_OPMode_TypeDef TIM6_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_OPM_MODE_OK(TIM6_OPMode));\r
+\r
+ /* Set or Reset the OPM Bit */\r
+ if (TIM6_OPMode == TIM6_OPMODE_SINGLE)\r
+ {\r
+ TIM6->CR1 |= TIM6_CR1_OPM ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->CR1 &= (uint8_t)(~TIM6_CR1_OPM) ;\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM6 Prescaler.\r
+ * @param Prescaler : Specifies the Prescaler Register value\r
+ * This parameter can be one of the @ref TIM6_Prescaler_TypeDef enumeration.\r
+ * @param TIM6_PSCReloadMode : Specifies the TIM6 Prescaler Reload mode.\r
+ * This parameter can be one of the @ref TIM6_PSCReloadMode_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_PrescalerConfig(TIM6_Prescaler_TypeDef Prescaler,\r
+ TIM6_PSCReloadMode_TypeDef TIM6_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_PRESCALER_RELOAD_OK(TIM6_PSCReloadMode));\r
+ assert_param(IS_TIM6_PRESCALER_OK(Prescaler));\r
+\r
+ /* Set the Prescaler value */\r
+ TIM6->PSCR = (uint8_t)Prescaler;\r
+\r
+ /* Set or reset the UG Bit */\r
+ if (TIM6_PSCReloadMode == TIM6_PSCRELOADMODE_IMMEDIATE)\r
+ {\r
+ TIM6->EGR |= TIM6_EGR_UG ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->EGR &= (uint8_t)(~TIM6_EGR_UG) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIM6 peripheral Preload register on ARR.\r
+ * @param NewState : The new state of the TIM6 peripheral Preload register.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_ARRPreloadConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the ARPE Bit */\r
+ if (NewState == ENABLE)\r
+ {\r
+ TIM6->CR1 |= TIM6_CR1_ARPE ;\r
+ }\r
+ else\r
+ {\r
+ TIM6->CR1 &= (uint8_t)(~TIM6_CR1_ARPE) ;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM6 Counter Register value.\r
+ * @param Counter : Specifies the Counter register new value.\r
+ * This parameter is between 0x00 and 0xFF.\r
+ * @retval None\r
+ */\r
+void TIM6_SetCounter(uint8_t Counter)\r
+{\r
+ /* Set the Counter Register value */\r
+ TIM6->CNTR = (uint8_t)(Counter);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIM6 Autoreload Register value.\r
+ * @param Autoreload : Specifies the Autoreload register new value.\r
+ * This parameter is between 0x00 and 0xFF.\r
+ * @retval None\r
+ */\r
+void TIM6_SetAutoreload(uint8_t Autoreload)\r
+{\r
+\r
+ /* Set the Autoreload Register value */\r
+ TIM6->ARR = (uint8_t)(Autoreload);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM6 Counter value.\r
+ * @param None\r
+ * @retval uint8_t: Counter Register value.\r
+ */\r
+uint8_t TIM6_GetCounter(void)\r
+{\r
+ uint8_t tmpcntr=0;\r
+ tmpcntr = TIM6->CNTR;\r
+ /* Get the Counter Register value */\r
+ return ((uint8_t)tmpcntr);\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIM6 Prescaler value.\r
+ * @param None\r
+ * @retval TIM6_Prescaler_TypeDef : Prescaler Register configuration value.\r
+ */\r
+TIM6_Prescaler_TypeDef TIM6_GetPrescaler(void)\r
+{\r
+ /* Get the Prescaler Register value */\r
+ return ((TIM6_Prescaler_TypeDef)TIM6->PSCR);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM6 interrupts.\r
+ * @param TIM6_IT : Specifies the TIM6 interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the @ref TIM6_IT_TypeDef enumeration.\r
+ * @param NewState : The new state of the TIM6 peripheral.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ * @par Required preconditions:\r
+ * If QST option bit is enabled, the TIM6 Interrupt vector will be mapped on IRQ number 2 (irq0).\r
+ * Otherwise, it will be mapped on IRQ number 27 (irq25).\r
+ */\r
+void TIM6_ITConfig(TIM6_IT_TypeDef TIM6_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_IT_OK(TIM6_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState == ENABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIM6->IER |= (uint8_t)TIM6_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIM6->IER &= (uint8_t)(~(uint8_t)TIM6_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM\92s pending flags.\r
+ * @param TIM6_FLAG : Specifies the flag to clear.\r
+ * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_ClearFlag(TIM6_FLAG_TypeDef TIM6_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_CLEAR_FLAG_OK((uint8_t)TIM6_FLAG));\r
+ /* Clear the flags (rc_w0) clear this bit by writing 0. Writing \911\92 has no effect*/\r
+ TIM6->SR1 &= (uint8_t)(~((uint8_t)TIM6_FLAG));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM6 interrupt has occurred or not.\r
+ * @param TIM6_IT : Specifies the TIM6 interrupt source to check.\r
+ * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.\r
+ * @retval ITStatus : The new state of the TIM6_IT.\r
+ * This parameter can be any of the @ref ITStatus enumeration.\r
+ */\r
+\r
+ITStatus TIM6_GetITStatus(TIM6_IT_TypeDef TIM6_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint8_t itStatus = 0, itEnable = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_GET_IT_OK(TIM6_IT));\r
+\r
+ itStatus = (uint8_t)(TIM6->SR1 & (uint8_t)TIM6_IT);\r
+\r
+ itEnable = (uint8_t)(TIM6->IER & (uint8_t)TIM6_IT);\r
+\r
+ if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))\r
+ {\r
+ bitstatus = (ITStatus)SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (ITStatus)RESET;\r
+ }\r
+ return ((ITStatus)bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM6 event to be generated by software.\r
+ * @param TIM6_EventSource : Specifies the event source.\r
+ * This parameter can be one of the @ref TIM6_EventSource_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_GenerateEvent(TIM6_EventSource_TypeDef TIM6_EventSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_EVENT_SOURCE_OK((uint8_t)TIM6_EventSource));\r
+\r
+ /* Set the event sources */\r
+ TIM6->EGR |= (uint8_t)TIM6_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM6 flag is set or not.\r
+ * @param TIM6_FLAG : Specifies the flag to check.\r
+ * This parameter can be one of the @ref TIM6_FLAG_TypeDef enumeration.\r
+ * @retval FlagStatus : The new state of TIM6_FLAG.\r
+ * This parameter can be any of the @ref FlagStatus enumeration.\r
+ */\r
+FlagStatus TIM6_GetFlagStatus(TIM6_FLAG_TypeDef TIM6_FLAG)\r
+{\r
+ volatile FlagStatus bitstatus = RESET;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_GET_FLAG_OK(TIM6_FLAG));\r
+\r
+ if ((TIM6->SR1 & (uint8_t)TIM6_FLAG) != 0)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return ((FlagStatus)bitstatus);\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIM6's interrupt pending bits.\r
+ * @param TIM6_IT : Specifies the pending bit to clear.\r
+ * This parameter can be one of the @ref TIM6_IT_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_ClearITPendingBit(TIM6_IT_TypeDef TIM6_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_IT_OK(TIM6_IT));\r
+\r
+ /* Clear the IT pending Bit */\r
+ TIM6->SR1 &= (uint8_t)(~(uint8_t)TIM6_IT);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM6 Trigger Output Mode.\r
+ * @param TIM6_TRGOSource : Specifies the Trigger Output source.\r
+ * This parameter can be one of the @ref TIM6_TRGOSource_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_SelectOutputTrigger(TIM6_TRGOSource_TypeDef TIM6_TRGOSource)\r
+{\r
+ uint8_t tmpcr2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_TRGO_SOURCE_OK(TIM6_TRGOSource));\r
+\r
+ tmpcr2 = TIM6->CR2;\r
+\r
+ /* Reset the MMS Bits */\r
+ tmpcr2 &= (uint8_t)(~TIM6_CR2_MMS);\r
+\r
+ /* Select the TRGO source */\r
+ tmpcr2 |= (uint8_t)TIM6_TRGOSource;\r
+\r
+ TIM6->CR2 = tmpcr2;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM6 Master/Slave Mode.\r
+ * @param NewState : The new state of the synchronization between TIM6 and its slaves (through TRGO).\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+\r
+void TIM6_SelectMasterSlaveMode(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Set or Reset the MSM Bit */\r
+ if (NewState == ENABLE)\r
+ {\r
+ TIM6->SMCR |= TIM6_SMCR_MSM;\r
+ }\r
+ else\r
+ {\r
+ TIM6->SMCR &= (uint8_t)(~TIM6_SMCR_MSM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM6 Input Trigger source.\r
+ * @param TIM6_InputTriggerSource : Specifies Input Trigger source.\r
+ * This parameter can be one of the @ref TIM6_TS_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_SelectInputTrigger(TIM6_TS_TypeDef TIM6_InputTriggerSource)\r
+{\r
+ uint8_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_TRIGGER_SELECTION_OK(TIM6_InputTriggerSource));\r
+\r
+ tmpsmcr = TIM6->SMCR;\r
+\r
+ /* Select the Tgigger Source */\r
+ tmpsmcr &= (uint8_t)(~TIM6_SMCR_TS);\r
+ tmpsmcr |= (uint8_t)TIM6_InputTriggerSource;\r
+\r
+ TIM6->SMCR = (uint8_t)tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Enables the TIM6 internal Clock.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void TIM6_InternalClockConfig(void)\r
+{\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIM6->SMCR &= (uint8_t)(~TIM6_SMCR_SMS);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM6 Slave Mode.\r
+ * @param TIM6_SlaveMode : Specifies the TIM6 Slave Mode.\r
+ * This parameter can be one of the @ref TIM6_SlaveMode_TypeDef enumeration.\r
+ * @retval None\r
+ */\r
+void TIM6_SelectSlaveMode(TIM6_SlaveMode_TypeDef TIM6_SlaveMode)\r
+{\r
+ uint8_t tmpsmcr = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM6_SLAVE_MODE_OK(TIM6_SlaveMode));\r
+\r
+ tmpsmcr = TIM6->SMCR;\r
+\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint8_t)(~TIM6_SMCR_SMS);\r
+\r
+ /* Select the Slave Mode */\r
+ tmpsmcr |= (uint8_t)TIM6_SlaveMode;\r
+\r
+ TIM6->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart1.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the UART1 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_uart1.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/** @}\r
+ * @addtogroup UART1_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the UART peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UART1_DeInit(void)\r
+{\r
+ /* Clear the Idle Line Detected bit in the status rerister by a read\r
+ to the UART1_SR register followed by a Read to the UART1_DR register */\r
+ (void)UART1->SR;\r
+ (void)UART1->DR;\r
+\r
+ UART1->BRR2 = UART1_BRR2_RESET_VALUE; /* Set UART1_BRR2 to reset value 0x00 */\r
+ UART1->BRR1 = UART1_BRR1_RESET_VALUE; /* Set UART1_BRR1 to reset value 0x00 */\r
+\r
+ UART1->CR1 = UART1_CR1_RESET_VALUE; /* Set UART1_CR1 to reset value 0x00 */\r
+ UART1->CR2 = UART1_CR2_RESET_VALUE; /* Set UART1_CR2 to reset value 0x00 */\r
+ UART1->CR3 = UART1_CR3_RESET_VALUE; /* Set UART1_CR3 to reset value 0x00 */\r
+ UART1->CR4 = UART1_CR4_RESET_VALUE; /* Set UART1_CR4 to reset value 0x00 */\r
+ UART1->CR5 = UART1_CR5_RESET_VALUE; /* Set UART1_CR5 to reset value 0x00 */\r
+\r
+ UART1->GTR = UART1_GTR_RESET_VALUE;\r
+ UART1->PSCR = UART1_PSCR_RESET_VALUE;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the UART1 according to the specified parameters.\r
+ * @note Configure in Push Pull or Open Drain mode the Tx pin by setting the\r
+ * correct I/O Port register according the product package and line\r
+ * configuration\r
+ * @param BaudRate: The baudrate.\r
+ * @param WordLength : This parameter can be any of the \r
+ * @ref UART1_WordLength_TypeDef enumeration.\r
+ * @param StopBits: This parameter can be any of the \r
+ * @ref UART1_StopBits_TypeDef enumeration.\r
+ * @param Parity: This parameter can be any of the \r
+ * @ref UART1_Parity_TypeDef enumeration.\r
+ * @param SyncMode: This parameter can be any of the \r
+ * @ref UART1_SyncMode_TypeDef values.\r
+ * @param Mode: This parameter can be any of the @ref UART1_Mode_TypeDef values\r
+ * @retval None\r
+ */\r
+void UART1_Init(uint32_t BaudRate, UART1_WordLength_TypeDef WordLength, \r
+ UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, \r
+ UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)\r
+{\r
+ uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART1_BAUDRATE_OK(BaudRate));\r
+ assert_param(IS_UART1_WORDLENGTH_OK(WordLength));\r
+ assert_param(IS_UART1_STOPBITS_OK(StopBits));\r
+ assert_param(IS_UART1_PARITY_OK(Parity));\r
+ assert_param(IS_UART1_MODE_OK((uint8_t)Mode));\r
+ assert_param(IS_UART1_SYNCMODE_OK((uint8_t)SyncMode));\r
+\r
+ /* Clear the word length bit */\r
+ UART1->CR1 &= (uint8_t)(~UART1_CR1_M); \r
+ \r
+ /* Set the word length bit according to UART1_WordLength value */\r
+ UART1->CR1 |= (uint8_t)WordLength;\r
+\r
+ /* Clear the STOP bits */\r
+ UART1->CR3 &= (uint8_t)(~UART1_CR3_STOP); \r
+ /* Set the STOP bits number according to UART1_StopBits value */\r
+ UART1->CR3 |= (uint8_t)StopBits; \r
+\r
+ /* Clear the Parity Control bit */\r
+ UART1->CR1 &= (uint8_t)(~(UART1_CR1_PCEN | UART1_CR1_PS )); \r
+ /* Set the Parity Control bit to UART1_Parity value */\r
+ UART1->CR1 |= (uint8_t)Parity; \r
+\r
+ /* Clear the LSB mantissa of UART1DIV */\r
+ UART1->BRR1 &= (uint8_t)(~UART1_BRR1_DIVM); \r
+ /* Clear the MSB mantissa of UART1DIV */\r
+ UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVM); \r
+ /* Clear the Fraction bits of UART1DIV */\r
+ UART1->BRR2 &= (uint8_t)(~UART1_BRR2_DIVF); \r
+\r
+ /* Set the UART1 BaudRates in BRR1 and BRR2 registers according to UART1_BaudRate value */\r
+ BaudRate_Mantissa = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));\r
+ BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));\r
+ /* Set the fraction of UART1DIV */\r
+ UART1->BRR2 |= (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (uint8_t)0x0F); \r
+ /* Set the MSB mantissa of UART1DIV */\r
+ UART1->BRR2 |= (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0); \r
+ /* Set the LSB mantissa of UART1DIV */\r
+ UART1->BRR1 |= (uint8_t)BaudRate_Mantissa; \r
+\r
+ /* Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */\r
+ UART1->CR2 &= (uint8_t)~(UART1_CR2_TEN | UART1_CR2_REN); \r
+ /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */\r
+ UART1->CR3 &= (uint8_t)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL); \r
+ /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */\r
+ UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART1_CR3_CPOL | \r
+ UART1_CR3_CPHA | UART1_CR3_LBCL)); \r
+\r
+ if ((uint8_t)(Mode & UART1_MODE_TX_ENABLE))\r
+ {\r
+ /* Set the Transmitter Enable bit */\r
+ UART1->CR2 |= (uint8_t)UART1_CR2_TEN; \r
+ }\r
+ else\r
+ {\r
+ /* Clear the Transmitter Disable bit */\r
+ UART1->CR2 &= (uint8_t)(~UART1_CR2_TEN); \r
+ }\r
+ if ((uint8_t)(Mode & UART1_MODE_RX_ENABLE))\r
+ {\r
+ /* Set the Receiver Enable bit */\r
+ UART1->CR2 |= (uint8_t)UART1_CR2_REN; \r
+ }\r
+ else\r
+ {\r
+ /* Clear the Receiver Disable bit */\r
+ UART1->CR2 &= (uint8_t)(~UART1_CR2_REN); \r
+ }\r
+ /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock \r
+ pulse bits according to UART1_Mode value */\r
+ if ((uint8_t)(SyncMode & UART1_SYNCMODE_CLOCK_DISABLE))\r
+ {\r
+ /* Clear the Clock Enable bit */\r
+ UART1->CR3 &= (uint8_t)(~UART1_CR3_CKEN); \r
+ }\r
+ else\r
+ {\r
+ UART1->CR3 |= (uint8_t)((uint8_t)SyncMode & UART1_CR3_CKEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the UART1 peripheral.\r
+ * @param NewState : The new state of the UART Communication.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void UART1_Cmd(FunctionalState NewState)\r
+{\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* UART1 Enable */\r
+ UART1->CR1 &= (uint8_t)(~UART1_CR1_UARTD); \r
+ }\r
+ else\r
+ {\r
+ /* UART Disable */\r
+ UART1->CR1 |= UART1_CR1_UARTD; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param UART1_IT specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * - UART1_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART1_IT_TC: Transmission complete interrupt\r
+ * - UART1_IT_RXNE: Receive Data register not empty interrupt\r
+ * - UART1_IT_OR: Overrun error interrupt\r
+ * - UART1_IT_IDLE: Idle line detection interrupt\r
+ * - USRT1_IT_ERR: Error interrupt\r
+ * @param NewState new state of the specified USART interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)\r
+{\r
+ uint8_t uartreg = 0, itpos = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Get the UART1 register index */\r
+ uartreg = (uint8_t)((uint16_t)UART1_IT >> 0x08);\r
+ /* Get the UART1 IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /**< Enable the Interrupt bits according to UART1_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART1->CR1 |= itpos;\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART1->CR2 |= itpos;\r
+ }\r
+ else\r
+ {\r
+ UART1->CR4 |= itpos;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /**< Disable the interrupt bits according to UART1_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART1->CR1 &= (uint8_t)(~itpos);\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART1->CR2 &= (uint8_t)(~itpos);\r
+ }\r
+ else\r
+ {\r
+ UART1->CR4 &= (uint8_t)(~itpos);\r
+ }\r
+ }\r
+\r
+}\r
+/**\r
+ * @brief Enables or disables the UART\92s Half Duplex communication.\r
+ * @param NewState new state of the UART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_HalfDuplexCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ UART1->CR5 |= UART1_CR5_HDSEL; /**< UART1 Half Duplex Enable */\r
+ }\r
+ else\r
+ {\r
+ UART1->CR5 &= (uint8_t)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the UART\92s IrDA interface.\r
+ * @param UART1_IrDAMode specifies the IrDA mode.\r
+ * This parameter can be any of the @ref UART1_IrDAMode_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)\r
+{\r
+ assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));\r
+\r
+ if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)\r
+ {\r
+ UART1->CR5 |= UART1_CR5_IRLP;\r
+ }\r
+ else\r
+ {\r
+ UART1->CR5 &= ((uint8_t)~UART1_CR5_IRLP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the UART\92s IrDA interface.\r
+ * @param NewState new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_IrDACmd(FunctionalState NewState)\r
+{\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ UART1->CR5 |= UART1_CR5_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ UART1->CR5 &= ((uint8_t)~UART1_CR5_IREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the UART1 LIN Break detection length.\r
+ * @param UART1_LINBreakDetectionLength specifies the LIN break detection length.\r
+ * This parameter can be any of the\r
+ * @ref UART1_LINBreakDetectionLength_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)\r
+{\r
+ assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));\r
+\r
+ if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)\r
+ {\r
+ UART1->CR4 |= UART1_CR4_LBDL;\r
+ }\r
+ else\r
+ {\r
+ UART1->CR4 &= ((uint8_t)~UART1_CR4_LBDL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the UART1\92s LIN mode.\r
+ * @param NewState is new state of the UART1 LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_LINCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINE bit in the CR2 register */\r
+ UART1->CR3 |= UART1_CR3_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINE bit in the CR2 register */\r
+ UART1->CR3 &= ((uint8_t)~UART1_CR3_LINEN);\r
+ }\r
+}\r
+/**\r
+ * @brief Enables or disables the UART1 Smart Card mode.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_SmartCardCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR5 register */\r
+ UART1->CR5 |= UART1_CR5_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR5 register */\r
+ UART1->CR5 &= ((uint8_t)(~UART1_CR5_SCEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @note This function is valid only for UART1 because is related to SmartCard mode.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_SmartCardNACKCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR5 register */\r
+ UART1->CR5 |= UART1_CR5_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */\r
+ UART1->CR5 &= ((uint8_t)~(UART1_CR5_NACK));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the UART1 WakeUp method.\r
+ * @param UART1_WakeUp: specifies the UART1 wakeup method.\r
+ * This parameter can be any of the @ref UART1_WakeUp_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)\r
+{\r
+ assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));\r
+\r
+ UART1->CR1 &= ((uint8_t)~UART1_CR1_WAKE);\r
+ UART1->CR1 |= (uint8_t)UART1_WakeUp;\r
+}\r
+/**\r
+ * @brief Determines if the UART1 is in mute mode or not.\r
+ * @param NewState: new state of the UART1 mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART1_ReceiverWakeUpCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the mute mode UART1 by setting the RWU bit in the CR2 register */\r
+ UART1->CR2 |= UART1_CR2_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the mute mode UART1 by clearing the RWU bit in the CR1 register */\r
+ UART1->CR2 &= ((uint8_t)~UART1_CR2_RWU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART1 peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint8_t UART1_ReceiveData8(void)\r
+{\r
+ return ((uint8_t)UART1->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART1 peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint16_t UART1_ReceiveData9(void)\r
+{\r
+ uint16_t temp = 0;\r
+ \r
+ temp = (uint16_t)(((uint16_t)( (uint16_t)UART1->CR1 & (uint16_t)UART1_CR1_R8)) << 1);\r
+ return (uint16_t)( (((uint16_t) UART1->DR) | temp ) & ((uint16_t)0x01FF));\r
+}\r
+\r
+/**\r
+ * @brief Transmits 8 bit data through the UART1 peripheral.\r
+ * @param Data: The data to transmit.\r
+ * @retval None\r
+ */\r
+void UART1_SendData8(uint8_t Data)\r
+{\r
+ /* Transmit Data */\r
+ UART1->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Transmits 9 bit data through the UART peripheral.\r
+ * @param Data : The data to transmit.\r
+ * This parameter should be lower than 0x1FF.\r
+ * @retval None\r
+ */\r
+void UART1_SendData9(uint16_t Data)\r
+{\r
+ /**< Clear the transmit data bit 8 [8] */\r
+ UART1->CR1 &= ((uint8_t)~UART1_CR1_T8);\r
+ /**< Write the transmit data bit [8] */\r
+ UART1->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART1_CR1_T8);\r
+ /**< Write the transmit data bit [0:7] */\r
+ UART1->DR = (uint8_t)(Data);\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UART1_SendBreak(void)\r
+{\r
+ UART1->CR2 |= UART1_CR2_SBK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the UART1 node.\r
+ * @param UART1_Address: Indicates the address of the UART1 node.\r
+ * @retval None\r
+ */\r
+void UART1_SetAddress(uint8_t UART1_Address)\r
+{\r
+ /*assert_param for UART1_Address*/\r
+ assert_param(IS_UART1_ADDRESS_OK(UART1_Address));\r
+\r
+ /* Clear the UART1 address */\r
+ UART1->CR4 &= ((uint8_t)~UART1_CR4_ADD);\r
+ /* Set the UART1 address node */\r
+ UART1->CR4 |= UART1_Address;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified UART guard time.\r
+ * @note SmartCard Mode should be Enabled\r
+ * @param UART1_GuardTime: specifies the guard time.\r
+ * @retval None\r
+ */\r
+void UART1_SetGuardTime(uint8_t UART1_GuardTime)\r
+{\r
+ /* Set the UART1 guard time */\r
+ UART1->GTR = UART1_GuardTime;\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @note IrDA Low Power mode or smartcard mode should be enabled\r
+ * @note This function is related to SmartCard and IrDa mode.\r
+ * @param UART1_Prescaler: specifies the prescaler clock.\r
+ * This parameter can be one of the following values:\r
+ * @par IrDA Low Power Mode\r
+ * The clock source is divided by the value given in the register (8 bits)\r
+ * - 0000 0000 Reserved\r
+ * - 0000 0001 divides the clock source by 1\r
+ * - 0000 0010 divides the clock source by 2\r
+ * - ...........................................................\r
+ * @par Smart Card Mode\r
+ * The clock source is divided by the value given in the register\r
+ * (5 significant bits) multiplied by 2\r
+ * - 0 0000 Reserved\r
+ * - 0 0001 divides the clock source by 2\r
+ * - 0 0010 divides the clock source by 4\r
+ * - 0 0011 divides the clock source by 6\r
+ * - ...........................................................\r
+ * @retval None\r
+ */\r
+void UART1_SetPrescaler(uint8_t UART1_Prescaler)\r
+{\r
+ /* Load the UART1 prescaler value*/\r
+ UART1->PSCR = UART1_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART1 flag is set or not.\r
+ * @param UART1_FLAG specifies the flag to check.\r
+ * This parameter can be any of the @ref UART1_Flag_TypeDef enumeration.\r
+ * @retval FlagStatus (SET or RESET)\r
+ */\r
+FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)\r
+{\r
+ FlagStatus status = RESET;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART1_FLAG_OK(UART1_FLAG));\r
+\r
+\r
+ /* Check the status of the specified UART1 flag*/\r
+ if (UART1_FLAG == UART1_FLAG_LBDF)\r
+ {\r
+ if ((UART1->CR4 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART1_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART1_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else if (UART1_FLAG == UART1_FLAG_SBK)\r
+ {\r
+ if ((UART1->CR2 & (uint8_t)UART1_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART1_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART1_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((UART1->SR & (uint8_t)UART1_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART1_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART1_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ /* Return the UART1_FLAG status*/\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Clears the UART1 flags.\r
+ * @param UART1_FLAG specifies the flag to clear\r
+ * This parameter can be any combination of the following values:\r
+ * - UART1_FLAG_LBDF: LIN Break detection flag.\r
+ * - UART1_FLAG_RXNE: Receive data register not empty flag.\r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) flags are \r
+ * cleared by software sequence: a read operation to UART1_SR register\r
+ * (UART1_GetFlagStatus())followed by a read operation to UART1_DR \r
+ * register(UART1_ReceiveData8() or UART1_ReceiveData9()).\r
+ * \r
+ * - RXNE flag can be also cleared by a read to the UART1_DR register\r
+ * (UART1_ReceiveData8()or UART1_ReceiveData9()).\r
+ * \r
+ * - TC flag can be also cleared by software sequence: a read operation\r
+ * to UART1_SR register (UART1_GetFlagStatus()) followed by a write \r
+ * operation to UART1_DR register (UART1_SendData8() or UART1_SendData9()).\r
+ * \r
+ * - TXE flag is cleared only by a write to the UART1_DR register \r
+ * (UART1_SendData8() or UART1_SendData9()).\r
+ * \r
+ * - SBK flag is cleared during the stop bit of break.\r
+ * @retval None\r
+ */\r
+\r
+void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)\r
+{\r
+ assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));\r
+\r
+ /* Clear the Receive Register Not Empty flag */\r
+ if (UART1_FLAG == UART1_FLAG_RXNE)\r
+ {\r
+ UART1->SR = (uint8_t)~(UART1_SR_RXNE);\r
+ }\r
+ /* Clear the LIN Break Detection flag */\r
+ else\r
+ {\r
+ UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART1 interrupt has occurred or not.\r
+ * @param UART1_IT: Specifies the UART1 interrupt pending bit to check.\r
+ * This parameter can be one of the following values:\r
+ * - UART1_IT_LBDF: LIN Break detection interrupt\r
+ * - UART1_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART1_IT_TC: Transmission complete interrupt\r
+ * - UART1_IT_RXNE: Receive Data register not empty interrupt\r
+ * - UART1_IT_IDLE: Idle line detection interrupt\r
+ * - UART1_IT_OR: OverRun Error interrupt\r
+ * - UART1_IT_PE: Parity Error interrupt\r
+ * @retval The new state of UART1_IT (SET or RESET).\r
+ */\r
+ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ uint8_t itpos = 0;\r
+ uint8_t itmask1 = 0;\r
+ uint8_t itmask2 = 0;\r
+ uint8_t enablestatus = 0;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART1_GET_IT_OK(UART1_IT));\r
+\r
+ /* Get the UART1 IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART1_IT & (uint8_t)0x0F));\r
+ /* Get the UART1 IT index */\r
+ itmask1 = (uint8_t)((uint8_t)UART1_IT >> (uint8_t)4);\r
+ /* Set the IT mask*/\r
+ itmask2 = (uint8_t)((uint8_t)1 << itmask1);\r
+\r
+\r
+ /* Check the status of the specified UART1 pending bit*/\r
+ if (UART1_IT == UART1_IT_PE)\r
+ {\r
+ /* Get the UART1_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART1->CR1 & itmask2);\r
+ /* Check the status of the specified UART1 interrupt*/\r
+\r
+ if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+\r
+ else if (UART1_IT == UART1_IT_LBDF)\r
+ {\r
+ /* Get the UART1_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART1->CR4 & itmask2);\r
+ /* Check the status of the specified UART1 interrupt*/\r
+ if (((UART1->CR4 & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the UART1_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART1->CR2 & itmask2);\r
+ /* Check the status of the specified UART1 interrupt*/\r
+ if (((UART1->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+\r
+ /* Return the UART1_IT status*/\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the UART1 pending flags.\r
+ * @param UART1_IT specifies the pending bit to clear\r
+ * This parameter can be one of the following values:\r
+ * - UART1_IT_LBDF: LIN Break detection interrupt\r
+ * - UART1_IT_RXNE: Receive Data register not empty interrupt.\r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) pending bits are \r
+ * cleared by software sequence: a read operation to UART1_SR register\r
+ * (UART1_GetITStatus()) followed by a read operation to UART1_DR register\r
+ * (UART1_ReceiveData8() or UART1_ReceiveData9()).\r
+ * \r
+ * - RXNE pending bit can be also cleared by a read to the UART1_DR register\r
+ * (UART1_ReceiveData8() or UART1_ReceiveData9()).\r
+ * \r
+ * - TC (Transmit complete) pending bit can be cleared by software \r
+ * sequence: a read operation to UART1_SR register (UART1_GetITStatus())\r
+ * followed by a write operation to UART1_DR register (UART1_SendData8()\r
+ * or UART1_SendData9()).\r
+ * \r
+ * - TXE pending bit is cleared only by a write to the UART1_DR register\r
+ * (UART1_SendData8() or UART1_SendData9()).\r
+ * @retval None\r
+ */\r
+void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)\r
+{\r
+ assert_param(IS_UART1_CLEAR_IT_OK(UART1_IT));\r
+\r
+ /* Clear the Receive Register Not Empty pending bit */\r
+ if (UART1_IT == UART1_IT_RXNE)\r
+ {\r
+ UART1->SR = (uint8_t)~(UART1_SR_RXNE);\r
+ }\r
+ /* Clear the LIN Break Detection pending bit */\r
+ else\r
+ {\r
+ UART1->CR4 &= (uint8_t)~(UART1_CR4_LBDF);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart2.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the UART2 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_uart2.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/** @}\r
+ * @addtogroup UART2_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the UART peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void UART2_DeInit(void)\r
+{\r
+ /* Clear the Idle Line Detected bit in the status register by a read\r
+ to the UART2_SR register followed by a Read to the UART2_DR register */\r
+ (void) UART2->SR;\r
+ (void)UART2->DR;\r
+\r
+ UART2->BRR2 = UART2_BRR2_RESET_VALUE; /* Set UART2_BRR2 to reset value 0x00 */\r
+ UART2->BRR1 = UART2_BRR1_RESET_VALUE; /* Set UART2_BRR1 to reset value 0x00 */\r
+\r
+ UART2->CR1 = UART2_CR1_RESET_VALUE; /* Set UART2_CR1 to reset value 0x00 */\r
+ UART2->CR2 = UART2_CR2_RESET_VALUE; /* Set UART2_CR2 to reset value 0x00 */\r
+ UART2->CR3 = UART2_CR3_RESET_VALUE; /* Set UART2_CR3 to reset value 0x00 */\r
+ UART2->CR4 = UART2_CR4_RESET_VALUE; /* Set UART2_CR4 to reset value 0x00 */\r
+ UART2->CR5 = UART2_CR5_RESET_VALUE; /* Set UART2_CR5 to reset value 0x00 */\r
+ UART2->CR6 = UART2_CR6_RESET_VALUE; /* Set UART2_CR6 to reset value 0x00 */\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the UART2 according to the specified parameters.\r
+ * @param BaudRate: The baudrate.\r
+ * @param WordLength : This parameter can be any of the \r
+ * @ref UART2_WordLength_TypeDef enumeration.\r
+ * @param StopBits: This parameter can be any of the \r
+ * @ref UART2_StopBits_TypeDef enumeration.\r
+ * @param Parity: This parameter can be any of the \r
+ * @ref UART2_Parity_TypeDef enumeration.\r
+ * @param SyncMode: This parameter can be any of the \r
+ * @ref UART2_SyncMode_TypeDef values.\r
+ * @param Mode: This parameter can be any of the @ref UART2_Mode_TypeDef values\r
+ * @retval None\r
+ */\r
+void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)\r
+{\r
+ uint8_t BRR2_1 = 0, BRR2_2 = 0;\r
+ uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART2_BAUDRATE_OK(BaudRate));\r
+ assert_param(IS_UART2_WORDLENGTH_OK(WordLength));\r
+ assert_param(IS_UART2_STOPBITS_OK(StopBits));\r
+ assert_param(IS_UART2_PARITY_OK(Parity));\r
+ assert_param(IS_UART2_MODE_OK((uint8_t)Mode));\r
+ assert_param(IS_UART2_SYNCMODE_OK((uint8_t)SyncMode));\r
+\r
+ /* Clear the word length bit */\r
+ UART2->CR1 &= (uint8_t)(~UART2_CR1_M);\r
+ /* Set the word length bit according to UART2_WordLength value */\r
+ UART2->CR1 |= (uint8_t)WordLength; \r
+\r
+ /* Clear the STOP bits */\r
+ UART2->CR3 &= (uint8_t)(~UART2_CR3_STOP);\r
+ /* Set the STOP bits number according to UART2_StopBits value */\r
+ UART2->CR3 |= (uint8_t)StopBits; \r
+\r
+ /* Clear the Parity Control bit */\r
+ UART2->CR1 &= (uint8_t)(~(UART2_CR1_PCEN | UART2_CR1_PS ));\r
+ /* Set the Parity Control bit to UART2_Parity value */\r
+ UART2->CR1 |= (uint8_t)Parity;\r
+\r
+ /* Clear the LSB mantissa of UART2DIV */\r
+ UART2->BRR1 &= (uint8_t)(~UART2_BRR1_DIVM);\r
+ /* Clear the MSB mantissa of UART2DIV */\r
+ UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVM);\r
+ /* Clear the Fraction bits of UART2DIV */\r
+ UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVF);\r
+\r
+ /* Set the UART2 BaudRates in BRR1 and BRR2 registers according to UART2_BaudRate value */\r
+ BaudRate_Mantissa = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));\r
+ BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));\r
+ \r
+ /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register*/\r
+ /* Set the fraction of UARTDIV */\r
+ BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))\r
+ << 4) / 100) & (uint8_t)0x0F); \r
+ BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);\r
+\r
+ UART2->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);\r
+ /* Set the LSB mantissa of UARTDIV */\r
+ UART2->BRR1 = (uint8_t)BaudRate_Mantissa; \r
+\r
+ /* Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */\r
+ UART2->CR2 &= (uint8_t)~(UART2_CR2_TEN | UART2_CR2_REN);\r
+ /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */\r
+ UART2->CR3 &= (uint8_t)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL);\r
+ /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */\r
+ UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART2_CR3_CPOL | \\r
+ UART2_CR3_CPHA | UART2_CR3_LBCL));\r
+\r
+ if ((uint8_t)(Mode & UART2_MODE_TX_ENABLE))\r
+ {\r
+ /* Set the Transmitter Enable bit */\r
+ UART2->CR2 |= (uint8_t)UART2_CR2_TEN;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the Transmitter Disable bit */\r
+ UART2->CR2 &= (uint8_t)(~UART2_CR2_TEN);\r
+ }\r
+ if ((uint8_t)(Mode & UART2_MODE_RX_ENABLE))\r
+ {\r
+ /* Set the Receiver Enable bit */\r
+ UART2->CR2 |= (uint8_t)UART2_CR2_REN;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the Receiver Disable bit */\r
+ UART2->CR2 &= (uint8_t)(~UART2_CR2_REN);\r
+ }\r
+ /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock \r
+ pulse bits according to UART2_Mode value */\r
+ if ((uint8_t)(SyncMode & UART2_SYNCMODE_CLOCK_DISABLE))\r
+ {\r
+ /* Clear the Clock Enable bit */\r
+ UART2->CR3 &= (uint8_t)(~UART2_CR3_CKEN); \r
+ }\r
+ else\r
+ {\r
+ UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & UART2_CR3_CKEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the UART2 peripheral.\r
+ * @param NewState : The new state of the UART Communication.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void UART2_Cmd(FunctionalState NewState)\r
+{\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* UART2 Enable */\r
+ UART2->CR1 &= (uint8_t)(~UART2_CR1_UARTD);\r
+ }\r
+ else\r
+ {\r
+ /* UART2 Disable */\r
+ UART2->CR1 |= UART2_CR1_UARTD; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified UART2 interrupts.\r
+ * @param UART2_IT specifies the UART2 interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * - UART2_IT_LBDF: LIN Break detection interrupt\r
+ * - UART2_IT_LHDF: LIN Break detection interrupt\r
+ * - UART2_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART2_IT_TC: Transmission complete interrupt\r
+ * - UART2_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt\r
+ * - UART2_IT_IDLE: Idle line detection interrupt\r
+ * - UART2_IT_PE: Parity Error interrupt\r
+ * @param NewState new state of the specified UART2 interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)\r
+{\r
+ uint8_t uartreg = 0, itpos = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Get the UART2 register index */\r
+ uartreg = (uint8_t)((uint16_t)UART2_IT >> 0x08);\r
+\r
+ /* Get the UART2 IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt bits according to UART2_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART2->CR1 |= itpos;\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART2->CR2 |= itpos;\r
+ }\r
+ else if (uartreg == 0x03)\r
+ {\r
+ UART2->CR4 |= itpos;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR6 |= itpos;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt bits according to UART2_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART2->CR1 &= (uint8_t)(~itpos);\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART2->CR2 &= (uint8_t)(~itpos);\r
+ }\r
+ else if (uartreg == 0x03)\r
+ {\r
+ UART2->CR4 &= (uint8_t)(~itpos);\r
+ }\r
+ else\r
+ {\r
+ UART2->CR6 &= (uint8_t)(~itpos);\r
+ }\r
+ }\r
+}\r
+/**\r
+ * @brief Configures the UART2\92s IrDA interface.\r
+ * @param UART2_IrDAMode specifies the IrDA mode.\r
+ * This parameter can be any of the @ref UART2_IrDAMode_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode)\r
+{\r
+ assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode));\r
+\r
+ if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL)\r
+ {\r
+ UART2->CR5 |= UART2_CR5_IRLP;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR5 &= ((uint8_t)~UART2_CR5_IRLP);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the UART2\92s IrDA interface.\r
+ * @param NewState new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART2_IrDACmd(FunctionalState NewState)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ UART2->CR5 |= UART2_CR5_IREN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ UART2->CR5 &= ((uint8_t)~UART2_CR5_IREN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the UART2 LIN Break detection length.\r
+ * @param UART2_LINBreakDetectionLength specifies the LIN break detection length.\r
+ * This parameter can be any of the \r
+ * @ref UART2_LINBreakDetectionLength_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)\r
+{\r
+ /* Check parameters */ \r
+ assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength));\r
+\r
+ if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS)\r
+ {\r
+ UART2->CR4 |= UART2_CR4_LBDL;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR4 &= ((uint8_t)~UART2_CR4_LBDL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the UART2 peripheral.\r
+ * @param UART2_Mode specifies the LIN mode.\r
+ * This parameter can be any of the @ref UART2_LinMode_TypeDef values.\r
+ * @param UART2_Autosync specifies the LIN automatic resynchronization mode.\r
+ * This parameter can be any of the @ref UART2_LinAutosync_TypeDef values.\r
+ * @param UART2_DivUp specifies the LIN divider update method.\r
+ * This parameter can be any of the @ref UART2_LinDivUp_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode, \r
+ UART2_LinAutosync_TypeDef UART2_Autosync, \r
+ UART2_LinDivUp_TypeDef UART2_DivUp)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_UART2_SLAVE_OK(UART2_Mode));\r
+ assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync));\r
+ assert_param(IS_UART2_DIVUP_OK(UART2_DivUp));\r
+\r
+ if (UART2_Mode != UART2_LIN_MODE_MASTER)\r
+ {\r
+ UART2->CR6 |= UART2_CR6_LSLV;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR6 &= ((uint8_t)~UART2_CR6_LSLV);\r
+ }\r
+\r
+ if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE)\r
+ {\r
+ UART2->CR6 |= UART2_CR6_LASE ;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR6 &= ((uint8_t)~ UART2_CR6_LASE );\r
+ }\r
+\r
+ if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1)\r
+ {\r
+ UART2->CR6 |= UART2_CR6_LDUM;\r
+ }\r
+ else\r
+ {\r
+ UART2->CR6 &= ((uint8_t)~ UART2_CR6_LDUM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the UART2 LIN mode.\r
+ * @param NewState is new state of the UART2 LIN mode.\r
+ * This parameter can be ENABLE or DISABLE\r
+ * @retval None\r
+ */\r
+void UART2_LINCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINE bit in the CR2 register */\r
+ UART2->CR3 |= UART2_CR3_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINE bit in the CR2 register */\r
+ UART2->CR3 &= ((uint8_t)~UART2_CR3_LINEN);\r
+ }\r
+}\r
+/**\r
+ * @brief Enables or disables the UART2 Smart Card mode.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART2_SmartCardCmd(FunctionalState NewState)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR5 register */\r
+ UART2->CR5 |= UART2_CR5_SCEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR5 register */\r
+ UART2->CR5 &= ((uint8_t)(~UART2_CR5_SCEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART2_SmartCardNACKCmd(FunctionalState NewState)\r
+{\r
+ /* Check parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR5 register */\r
+ UART2->CR5 |= UART2_CR5_NACK;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR5 register */\r
+ UART2->CR5 &= ((uint8_t)~(UART2_CR5_NACK));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the UART2 WakeUp method.\r
+ * @param UART2_WakeUp: specifies the UART2 wakeup method.\r
+ * This parameter can be any of the @ref UART2_WakeUp_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp)\r
+{\r
+ assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp));\r
+\r
+ UART2->CR1 &= ((uint8_t)~UART2_CR1_WAKE);\r
+ UART2->CR1 |= (uint8_t)UART2_WakeUp;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the UART2 is in mute mode or not.\r
+ * @param NewState: new state of the UART2 mode.\r
+ * This parameter can be ENABLE or DISABLE\r
+ * @retval None\r
+ */\r
+void UART2_ReceiverWakeUpCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the mute mode UART2 by setting the RWU bit in the CR2 register */\r
+ UART2->CR2 |= UART2_CR2_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the mute mode UART2 by clearing the RWU bit in the CR1 register */\r
+ UART2->CR2 &= ((uint8_t)~UART2_CR2_RWU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART2 peripheral.\r
+ * @param None\r
+ * @retval Received Data\r
+ */\r
+uint8_t UART2_ReceiveData8(void)\r
+{\r
+ return ((uint8_t)UART2->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART2 peripheral.\r
+ * @param None \r
+ * @retval Received Data\r
+ */\r
+uint16_t UART2_ReceiveData9(void)\r
+{\r
+ uint16_t temp = 0;\r
+\r
+ temp = ((uint16_t)(((uint16_t)((uint16_t)UART2->CR1 & (uint16_t)UART2_CR1_R8)) << 1));\r
+ \r
+ return (uint16_t)((((uint16_t)UART2->DR) | temp) & ((uint16_t)0x01FF));\r
+}\r
+\r
+/**\r
+ * @brief Transmits 8 bit data through the UART2 peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void UART2_SendData8(uint8_t Data)\r
+{\r
+ /* Transmit Data */\r
+ UART2->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Transmits 9 bit data through the UART2 peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void UART2_SendData9(uint16_t Data)\r
+{\r
+ /* Clear the transmit data bit 8 */\r
+ UART2->CR1 &= ((uint8_t)~UART2_CR1_T8); \r
+ \r
+ /* Write the transmit data bit [8] */\r
+ UART2->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART2_CR1_T8); \r
+ \r
+ /* Write the transmit data bit [0:7] */\r
+ UART2->DR = (uint8_t)(Data); \r
+\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UART2_SendBreak(void)\r
+{\r
+ UART2->CR2 |= UART2_CR2_SBK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the UART2 node.\r
+ * @param UART2_Address: Indicates the address of the UART2 node.\r
+ * @retval None\r
+ */\r
+void UART2_SetAddress(uint8_t UART2_Address)\r
+{\r
+ /*assert_param for x UART2_Address*/\r
+ assert_param(IS_UART2_ADDRESS_OK(UART2_Address));\r
+\r
+ /* Clear the UART2 address */\r
+ UART2->CR4 &= ((uint8_t)~UART2_CR4_ADD);\r
+ /* Set the UART2 address node */\r
+ UART2->CR4 |= UART2_Address;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified UART2 guard time.\r
+ * @note SmartCard Mode should be Enabled \r
+ * @param UART2_GuardTime: specifies the guard time.\r
+ * @retval None\r
+ */\r
+void UART2_SetGuardTime(uint8_t UART2_GuardTime)\r
+{\r
+ /* Set the UART2 guard time */\r
+ UART2->GTR = UART2_GuardTime;\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @note IrDA Low Power mode or smartcard mode should be enabled\r
+ * @note This function is related to SmartCard and IrDa mode.\r
+ * @param UART2_Prescaler: specifies the prescaler clock.\r
+ * This parameter can be one of the following values:\r
+ * @par IrDA Low Power Mode\r
+ * The clock source is divided by the value given in the register (8 bits)\r
+ * - 0000 0000 Reserved\r
+ * - 0000 0001 divides the clock source by 1\r
+ * - 0000 0010 divides the clock source by 2\r
+ * - ...........................................................\r
+ * @par Smart Card Mode\r
+ * The clock source is divided by the value given in the register\r
+ * (5 significant bits) multiped by 2\r
+ * - 0 0000 Reserved\r
+ * - 0 0001 divides the clock source by 2\r
+ * - 0 0010 divides the clock source by 4\r
+ * - 0 0011 divides the clock source by 6\r
+ * - ...........................................................\r
+ * @retval None\r
+ */\r
+void UART2_SetPrescaler(uint8_t UART2_Prescaler)\r
+{\r
+ /* Load the UART2 prescaler value*/\r
+ UART2->PSCR = UART2_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART2 flag is set or not.\r
+ * @param UART2_FLAG specifies the flag to check.\r
+ * This parameter can be any of the @ref UART2_Flag_TypeDef enumeration.\r
+ * @retval FlagStatus (SET or RESET)\r
+ */\r
+FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)\r
+{\r
+ FlagStatus status = RESET;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART2_FLAG_OK(UART2_FLAG));\r
+\r
+ /* Check the status of the specified UART2 flag*/\r
+ if (UART2_FLAG == UART2_FLAG_LBDF)\r
+ {\r
+ if ((UART2->CR4 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART2_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART2_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else if (UART2_FLAG == UART2_FLAG_SBK)\r
+ {\r
+ if ((UART2->CR2 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART2_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART2_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))\r
+ {\r
+ if ((UART2->CR6 & (uint8_t)UART2_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART2_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART2_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((UART2->SR & (uint8_t)UART2_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART2_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART2_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+\r
+ /* Return the UART2_FLAG status*/\r
+ return status;\r
+}\r
+/**\r
+ * @brief Clears the UART2 flags.\r
+ * @param UART2_FLAG specifies the flag to clear\r
+ * This parameter can be any combination of the following values:\r
+ * - UART2_FLAG_LBDF: LIN Break detection flag.\r
+ * - UART2_FLAG_LHDF: LIN Header detection flag.\r
+ * - UART2_FLAG_LSF: LIN synchrone field flag.\r
+ * - UART2_FLAG_RXNE: Receive data register not empty flag.\r
+ * @note:\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) flags are cleared\r
+ * by software sequence: a read operation to UART2_SR register \r
+ * (UART2_GetFlagStatus())followed by a read operation to UART2_DR \r
+ * register(UART2_ReceiveData8() or UART2_ReceiveData9()).\r
+ * \r
+ * - RXNE flag can be also cleared by a read to the UART2_DR register\r
+ * (UART2_ReceiveData8()or UART2_ReceiveData9()).\r
+ *\r
+ * - TC flag can be also cleared by software sequence: a read operation\r
+ * to UART2_SR register (UART2_GetFlagStatus()) followed by a write \r
+ * operation to UART2_DR register (UART2_SendData8() or UART2_SendData9()).\r
+ * \r
+ * - TXE flag is cleared only by a write to the UART2_DR register \r
+ * (UART2_SendData8() or UART2_SendData9()).\r
+ * \r
+ * - SBK flag is cleared during the stop bit of break.\r
+ * @retval None\r
+ */\r
+void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)\r
+{\r
+ assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));\r
+\r
+ /* Clear the Receive Register Not Empty flag */\r
+ if (UART2_FLAG == UART2_FLAG_RXNE)\r
+ {\r
+ UART2->SR = (uint8_t)~(UART2_SR_RXNE);\r
+ }\r
+ /* Clear the LIN Break Detection flag */\r
+ else if (UART2_FLAG == UART2_FLAG_LBDF)\r
+ {\r
+ UART2->CR4 &= (uint8_t)(~UART2_CR4_LBDF);\r
+ }\r
+ /* Clear the LIN Header Detection Flag */\r
+ else if (UART2_FLAG == UART2_FLAG_LHDF)\r
+ {\r
+ UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);\r
+ }\r
+ /* Clear the LIN Synch Field flag */\r
+ else\r
+ {\r
+ UART2->CR6 &= (uint8_t)(~UART2_CR6_LSF);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART2 interrupt has occurred or not.\r
+ * @param UART2_IT: Specifies the UART2 interrupt pending bit to check.\r
+ * This parameter can be one of the following values:\r
+ * - UART2_IT_LBDF: LIN Break detection interrupt\r
+ * - UART2_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART2_IT_TC: Transmission complete interrupt\r
+ * - UART2_IT_RXNE: Receive Data register not empty interrupt\r
+ * - UART2_IT_IDLE: Idle line detection interrupt\r
+ * - UART2_IT_OR: OverRun Error interrupt\r
+ * - UART2_IT_PE: Parity Error interrupt\r
+ * @retval The state of UART2_IT (SET or RESET).\r
+ */\r
+ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ uint8_t itpos = 0;\r
+ uint8_t itmask1 = 0;\r
+ uint8_t itmask2 = 0;\r
+ uint8_t enablestatus = 0;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART2_GET_IT_OK(UART2_IT));\r
+\r
+ /* Get the UART2 IT index*/\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F));\r
+ /* Get the UART2 IT index*/\r
+ itmask1 = (uint8_t)((uint8_t)UART2_IT >> (uint8_t)4);\r
+ /* Set the IT mask*/\r
+ itmask2 = (uint8_t)((uint8_t)1 << itmask1);\r
+\r
+ /* Check the status of the specified UART2 pending bit*/\r
+ if (UART2_IT == UART2_IT_PE)\r
+ {\r
+ /* Get the UART2_ITPENDINGBIT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART2->CR1 & itmask2);\r
+ /* Check the status of the specified UART2 interrupt*/\r
+\r
+ if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else if (UART2_IT == UART2_IT_LBDF)\r
+ {\r
+ /* Get the UART2_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART2->CR4 & itmask2);\r
+ /* Check the status of the specified UART2 interrupt*/\r
+ if (((UART2->CR4 & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else if (UART2_IT == UART2_IT_LHDF)\r
+ {\r
+ /* Get the UART2_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART2->CR6 & itmask2);\r
+ /* Check the status of the specified UART2 interrupt*/\r
+ if (((UART2->CR6 & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the UART2_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART2->CR2 & itmask2);\r
+ /* Check the status of the specified UART2 interrupt*/\r
+ if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the UART2_IT status*/\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the UART2 pending flags.\r
+ * @param UART2_IT specifies the pending bit to clear\r
+ * This parameter can be one of the following values:\r
+ * - UART2_IT_LBDF: LIN Break detection interrupt\r
+ * - UART2_IT_LHDF: LIN Header detection interrupt\r
+ * - UART2_IT_RXNE: Receive Data register not empty interrupt.\r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) pending bits are \r
+ * cleared by software sequence: a read operation to UART2_SR register\r
+ * (UART2_GetITStatus()) followed by a read operation to UART2_DR register\r
+ * (UART2_ReceiveData8() or UART2_ReceiveData9()).\r
+ * \r
+ * - RXNE pending bit can be also cleared by a read to the UART2_DR \r
+ * register (UART2_ReceiveData8() or UART2_ReceiveData9()).\r
+ * \r
+ * - TC (Transmit complete) pending bit can be cleared by software \r
+ * sequence: a read operation to UART2_SR register \r
+ * (UART2_GetITStatus()) followed by a write operation to UART2_DR \r
+ * register (UART2_SendData8()or UART2_SendData9()).\r
+ * \r
+ * - TXE pending bit is cleared only by a write to the UART2_DR register\r
+ * (UART2_SendData8() or UART2_SendData9()).\r
+ * @retval None\r
+ */\r
+void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)\r
+{\r
+ assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));\r
+\r
+ /* Clear the Receive Register Not Empty pending bit */\r
+ if (UART2_IT == UART2_IT_RXNE)\r
+ {\r
+ UART2->SR = (uint8_t)~(UART2_SR_RXNE);\r
+ }\r
+ /* Clear the LIN Break Detection pending bit */\r
+ else if (UART2_IT == UART2_IT_LBDF)\r
+ {\r
+ UART2->CR4 &= (uint8_t)~(UART2_CR4_LBDF);\r
+ }\r
+ /* Clear the LIN Header Detection pending bit */\r
+ else\r
+ {\r
+ UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF);\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_uart3.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the uart3 peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_uart3.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+/* Public functions ----------------------------------------------------------*/\r
+\r
+/** @}\r
+ * @addtogroup UART3_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the UART peripheral.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+\r
+void UART3_DeInit(void)\r
+{\r
+ /* Clear the Idle Line Detected bit in the status rerister by a read\r
+ to the UART3_SR register followed by a Read to the UART3_DR register */\r
+ (void) UART3->SR;\r
+ (void) UART3->DR;\r
+\r
+ UART3->BRR2 = UART3_BRR2_RESET_VALUE; /*Set UART3_BRR2 to reset value 0x00 */\r
+ UART3->BRR1 = UART3_BRR1_RESET_VALUE; /*Set UART3_BRR1 to reset value 0x00 */\r
+\r
+ UART3->CR1 = UART3_CR1_RESET_VALUE; /*Set UART3_CR1 to reset value 0x00 */\r
+ UART3->CR2 = UART3_CR2_RESET_VALUE; /*Set UART3_CR2 to reset value 0x00 */\r
+ UART3->CR3 = UART3_CR3_RESET_VALUE; /*Set UART3_CR3 to reset value 0x00 */\r
+ UART3->CR4 = UART3_CR4_RESET_VALUE; /*Set UART3_CR4 to reset value 0x00 */\r
+ UART3->CR6 = UART3_CR6_RESET_VALUE; /*Set UART3_CR6 to reset value 0x00 */\r
+\r
+}\r
+\r
+/**\r
+ * @brief Initializes the UART3 according to the specified parameters.\r
+ * @param BaudRate: The baudrate.\r
+ * @param WordLength : This parameter can be any of \r
+ * the @ref UART3_WordLength_TypeDef enumeration.\r
+ * @param StopBits: This parameter can be any of the \r
+ * @ref UART3_StopBits_TypeDef enumeration.\r
+ * @param Parity: This parameter can be any of the \r
+ * @ref UART3_Parity_TypeDef enumeration.\r
+ * @param Mode: This parameter can be any of the @ref UART3_Mode_TypeDef values\r
+ * @retval None\r
+ */\r
+void UART3_Init(uint32_t BaudRate, UART3_WordLength_TypeDef WordLength, \r
+ UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, \r
+ UART3_Mode_TypeDef Mode)\r
+{\r
+ uint8_t BRR2_1 = 0, BRR2_2 = 0;\r
+ uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_WORDLENGTH_OK(WordLength));\r
+ assert_param(IS_UART3_STOPBITS_OK(StopBits));\r
+ assert_param(IS_UART3_PARITY_OK(Parity));\r
+ assert_param(IS_UART3_BAUDRATE_OK(BaudRate));\r
+ assert_param(IS_UART3_MODE_OK((uint8_t)Mode));\r
+\r
+ /* Clear the word length bit */\r
+ UART3->CR1 &= (uint8_t)(~UART3_CR1_M); \r
+ /* Set the word length bit according to UART3_WordLength value */\r
+ UART3->CR1 |= (uint8_t)WordLength; \r
+\r
+ /* Clear the STOP bits */\r
+ UART3->CR3 &= (uint8_t)(~UART3_CR3_STOP); \r
+ /* Set the STOP bits number according to UART3_StopBits value */\r
+ UART3->CR3 |= (uint8_t)StopBits; \r
+\r
+ /* Clear the Parity Control bit */\r
+ UART3->CR1 &= (uint8_t)(~(UART3_CR1_PCEN | UART3_CR1_PS)); \r
+ /* Set the Parity Control bit to UART3_Parity value */\r
+ UART3->CR1 |= (uint8_t)Parity; \r
+\r
+ /* Clear the LSB mantissa of UART3DIV */\r
+ UART3->BRR1 &= (uint8_t)(~UART3_BRR1_DIVM); \r
+ /* Clear the MSB mantissa of UART3DIV */\r
+ UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVM); \r
+ /* Clear the Fraction bits of UART3DIV */\r
+ UART3->BRR2 &= (uint8_t)(~UART3_BRR2_DIVF); \r
+\r
+ /* Set the UART3 BaudRates in BRR1 and BRR2 registers according to UART3_BaudRate value */\r
+ BaudRate_Mantissa = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4));\r
+ BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4));\r
+ /* The fraction and MSB mantissa should be loaded in one step in the BRR2 register */\r
+ /* Set the fraction of UART3DIV */\r
+ BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))\r
+ << 4) / 100) & (uint8_t)0x0F); \r
+ BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0);\r
+\r
+ UART3->BRR2 = (uint8_t)(BRR2_1 | BRR2_2);\r
+ /* Set the LSB mantissa of UART3DIV */\r
+ UART3->BRR1 = (uint8_t)BaudRate_Mantissa; \r
+\r
+ if ((uint8_t)(Mode & UART3_MODE_TX_ENABLE))\r
+ {\r
+ /* Set the Transmitter Enable bit */\r
+ UART3->CR2 |= UART3_CR2_TEN; \r
+ }\r
+ else\r
+ {\r
+ /* Clear the Transmitter Disable bit */\r
+ UART3->CR2 &= (uint8_t)(~UART3_CR2_TEN); \r
+ }\r
+ if ((uint8_t)(Mode & UART3_MODE_RX_ENABLE))\r
+ {\r
+ /* Set the Receiver Enable bit */\r
+ UART3->CR2 |= UART3_CR2_REN; \r
+ }\r
+ else\r
+ {\r
+ /* Clear the Receiver Disable bit */\r
+ UART3->CR2 &= (uint8_t)(~UART3_CR2_REN); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enable the UART1 peripheral.\r
+ * @param NewState : The new state of the UART Communication.\r
+ * This parameter can be any of the @ref FunctionalState enumeration.\r
+ * @retval None\r
+ */\r
+void UART3_Cmd(FunctionalState NewState)\r
+{\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* UART3 Enable */\r
+ UART3->CR1 &= (uint8_t)(~UART3_CR1_UARTD); \r
+ }\r
+ else\r
+ {\r
+ /* UART3 Disable */\r
+ UART3->CR1 |= UART3_CR1_UARTD; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified UART3 interrupts.\r
+ * @param UART3_IT specifies the UART3 interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * - UART3_IT_LBDF: LIN Break detection interrupt\r
+ * - UART3_IT_LHDF: LIN Break detection interrupt\r
+ * - UART3_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART3_IT_TC: Transmission complete interrupt\r
+ * - UART3_IT_RXNE_OR: Receive Data register not empty/Over run error interrupt\r
+ * - UART3_IT_IDLE: Idle line detection interrupt\r
+ * - UART3_IT_PE: Parity Error interrupt\r
+ * @param NewState new state of the specified UART3 interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState)\r
+{\r
+ uint8_t uartreg = 0, itpos = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_CONFIG_IT_OK(UART3_IT));\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ /* Get the UART3 register index */\r
+ uartreg = (uint8_t)((uint16_t)UART3_IT >> 0x08);\r
+\r
+ /* Get the UART3 IT index */\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt bits according to UART3_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART3->CR1 |= itpos;\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART3->CR2 |= itpos;\r
+ }\r
+ else if (uartreg == 0x03)\r
+ {\r
+ UART3->CR4 |= itpos;\r
+ }\r
+ else\r
+ {\r
+ UART3->CR6 |= itpos;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt bits according to UART3_IT mask */\r
+ if (uartreg == 0x01)\r
+ {\r
+ UART3->CR1 &= (uint8_t)(~itpos);\r
+ }\r
+ else if (uartreg == 0x02)\r
+ {\r
+ UART3->CR2 &= (uint8_t)(~itpos);\r
+ }\r
+ else if (uartreg == 0x03)\r
+ {\r
+ UART3->CR4 &= (uint8_t)(~itpos);\r
+ }\r
+ else\r
+ {\r
+ UART3->CR6 &= (uint8_t)(~itpos);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the UART3 LIN Break detection length.\r
+ * @param UART3_LINBreakDetectionLength specifies the LIN break detection length.\r
+ * This parameter can be any of the \r
+ * @ref UART3_LINBreakDetectionLength_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART3_LINBreakDetectionConfig(UART3_LINBreakDetectionLength_TypeDef UART3_LINBreakDetectionLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_LINBREAKDETECTIONLENGTH_OK(UART3_LINBreakDetectionLength));\r
+\r
+ if (UART3_LINBreakDetectionLength != UART3_LINBREAKDETECTIONLENGTH_10BITS)\r
+ {\r
+ UART3->CR4 |= UART3_CR4_LBDL;\r
+ }\r
+ else\r
+ {\r
+ UART3->CR4 &= ((uint8_t)~UART3_CR4_LBDL);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configure the UART3 peripheral.\r
+ * @param UART3_Mode specifies the LIN mode.\r
+ * This parameter can be any of the @ref UART3_LinMode_TypeDef values.\r
+ * @param UART3_Autosync specifies the LIN automatic resynchronization mode.\r
+ * This parameter can be any of the @ref UART3_LinAutosync_TypeDef values.\r
+ * @param UART3_DivUp specifies the LIN divider update method.\r
+ * This parameter can be any of the @ref UART3_LinDivUp_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART3_LINConfig(UART3_LinMode_TypeDef UART3_Mode,\r
+ UART3_LinAutosync_TypeDef UART3_Autosync, \r
+ UART3_LinDivUp_TypeDef UART3_DivUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_SLAVE_OK(UART3_Mode));\r
+ assert_param(IS_UART3_AUTOSYNC_OK(UART3_Autosync));\r
+ assert_param(IS_UART3_DIVUP_OK(UART3_DivUp));\r
+\r
+ if (UART3_Mode != UART3_LIN_MODE_MASTER)\r
+ {\r
+ UART3->CR6 |= UART3_CR6_LSLV;\r
+ }\r
+ else\r
+ {\r
+ UART3->CR6 &= ((uint8_t)~UART3_CR6_LSLV);\r
+ }\r
+\r
+ if (UART3_Autosync != UART3_LIN_AUTOSYNC_DISABLE)\r
+ {\r
+ UART3->CR6 |= UART3_CR6_LASE ;\r
+ }\r
+ else\r
+ {\r
+ UART3->CR6 &= ((uint8_t)~ UART3_CR6_LASE );\r
+ }\r
+\r
+ if (UART3_DivUp != UART3_LIN_DIVUP_LBRR1)\r
+ {\r
+ UART3->CR6 |= UART3_CR6_LDUM;\r
+ }\r
+ else\r
+ {\r
+ UART3->CR6 &= ((uint8_t)~ UART3_CR6_LDUM);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the UART3 LIN mode.\r
+ * @param NewState is new state of the UART3 LIN mode.\r
+ * This parameter can be ENABLE or DISABLE\r
+ * @retval None\r
+ */\r
+void UART3_LINCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINE bit in the CR2 register */\r
+ UART3->CR3 |= UART3_CR3_LINEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINE bit in the CR2 register */\r
+ UART3->CR3 &= ((uint8_t)~UART3_CR3_LINEN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the UART3 WakeUp method.\r
+ * @param UART3_WakeUp: specifies the UART3 wakeup method.\r
+ * This parameter can be any of the @ref UART3_WakeUp_TypeDef values.\r
+ * @retval None\r
+ */\r
+void UART3_WakeUpConfig(UART3_WakeUp_TypeDef UART3_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_WAKEUP_OK(UART3_WakeUp));\r
+\r
+ UART3->CR1 &= ((uint8_t)~UART3_CR1_WAKE);\r
+ UART3->CR1 |= (uint8_t)UART3_WakeUp;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the UART3 is in mute mode or not.\r
+ * @param NewState: new state of the UART3 mode.\r
+ * This parameter can be ENABLE or DISABLE\r
+ * @retval None\r
+ */\r
+void UART3_ReceiverWakeUpCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONALSTATE_OK(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the mute mode UART3 by setting the RWU bit in the CR2 register */\r
+ UART3->CR2 |= UART3_CR2_RWU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the mute mode UART3 by clearing the RWU bit in the CR1 register */\r
+ UART3->CR2 &= ((uint8_t)~UART3_CR2_RWU);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART3 peripheral.\r
+ * @param None\r
+ * @retval Received Data\r
+ */\r
+uint8_t UART3_ReceiveData8(void)\r
+{\r
+ return ((uint8_t)UART3->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the UART3 peripheral.\r
+ * @param None\r
+ * @retval Received Data\r
+ */\r
+uint16_t UART3_ReceiveData9(void)\r
+{\r
+ uint16_t temp = 0;\r
+\r
+ temp = (uint16_t)(((uint16_t)((uint16_t)UART3->CR1 & (uint16_t)UART3_CR1_R8)) << 1);\r
+ return (uint16_t)((((uint16_t)UART3->DR) | temp) & ((uint16_t)0x01FF));\r
+}\r
+\r
+/**\r
+ * @brief Transmits 8 bit data through the UART3 peripheral.\r
+ * @param Data the data to transmit.\r
+ * @retval None\r
+ */\r
+void UART3_SendData8(uint8_t Data)\r
+{\r
+ /* Transmit Data */\r
+ UART3->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Transmits 9 bit data through the UART3 peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void UART3_SendData9(uint16_t Data)\r
+{\r
+ /* Clear the transmit data bit 8 */\r
+ UART3->CR1 &= ((uint8_t)~UART3_CR1_T8); \r
+ \r
+ /* Write the transmit data bit [8] */\r
+ UART3->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART3_CR1_T8); \r
+ \r
+ /* Write the transmit data bit [0:7] */\r
+ UART3->DR = (uint8_t)(Data); \r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void UART3_SendBreak(void)\r
+{\r
+ UART3->CR2 |= UART3_CR2_SBK;\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the UART3 node.\r
+ * @param UART3_Address: Indicates the address of the UART3 node.\r
+ * @retval None\r
+ */\r
+void UART3_SetAddress(uint8_t UART3_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_ADDRESS_OK(UART3_Address));\r
+\r
+ /* Clear the UART3 address */\r
+ UART3->CR4 &= ((uint8_t)~UART3_CR4_ADD);\r
+ /* Set the UART3 address node */\r
+ UART3->CR4 |= UART3_Address;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART3 flag is set or not.\r
+ * @param UART3_FLAG specifies the flag to check.\r
+ * This parameter can be any of the @ref UART3_Flag_TypeDef enumeration.\r
+ * @retval FlagStatus (SET or RESET)\r
+ */\r
+FlagStatus UART3_GetFlagStatus(UART3_Flag_TypeDef UART3_FLAG)\r
+{\r
+ FlagStatus status = RESET;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART3_FLAG_OK(UART3_FLAG));\r
+\r
+ /* Check the status of the specified UART3 flag*/\r
+ if (UART3_FLAG == UART3_FLAG_LBDF)\r
+ {\r
+ if ((UART3->CR4 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART3_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART3_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else if (UART3_FLAG == UART3_FLAG_SBK)\r
+ {\r
+ if ((UART3->CR2 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART3_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART3_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else if ((UART3_FLAG == UART3_FLAG_LHDF) || (UART3_FLAG == UART3_FLAG_LSF))\r
+ {\r
+ if ((UART3->CR6 & (uint8_t)UART3_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART3_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART3_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if ((UART3->SR & (uint8_t)UART3_FLAG) != (uint8_t)0x00)\r
+ {\r
+ /* UART3_FLAG is set*/\r
+ status = SET;\r
+ }\r
+ else\r
+ {\r
+ /* UART3_FLAG is reset*/\r
+ status = RESET;\r
+ }\r
+ }\r
+\r
+ /* Return the UART3_FLAG status*/\r
+ return status;\r
+}\r
+/**\r
+ * @brief Clears the UART3 flags.\r
+ * @param UART3_FLAG specifies the flag to clear\r
+ * This parameter can be any combination of the following values:\r
+ * - UART3_FLAG_LBDF: LIN Break detection flag.\r
+ * - UART3_FLAG_LHDF: LIN Header detection flag.\r
+ * - UART3_FLAG_LSF: LIN synchrone field flag.\r
+ * - UART3_FLAG_RXNE: Receive data register not empty flag.\r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NF (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) flags are cleared\r
+ * by software sequence: a read operation to UART3_SR register \r
+ * (UART3_GetFlagStatus())followed by a read operation to UART3_DR \r
+ * register(UART3_ReceiveData8() or UART3_ReceiveData9()).\r
+ * \r
+ * - RXNE flag can be also cleared by a read to the UART3_DR register\r
+ * (UART3_ReceiveData8()or UART3_ReceiveData9()).\r
+ * \r
+ * - TC flag can be also cleared by software sequence: a read operation\r
+ * to UART3_SR register (UART3_GetFlagStatus()) followed by a write \r
+ * operation to UART3_DR register (UART3_SendData8() or UART3_SendData9()).\r
+ * \r
+ * - TXE flag is cleared only by a write to the UART3_DR register \r
+ * (UART3_SendData8() or UART3_SendData9()).\r
+ * \r
+ * - SBK flag is cleared during the stop bit of break.\r
+ * @retval None\r
+ */\r
+void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_CLEAR_FLAG_OK(UART3_FLAG));\r
+\r
+ /*Clear the Receive Register Not Empty flag */\r
+ if (UART3_FLAG == UART3_FLAG_RXNE)\r
+ {\r
+ UART3->SR = (uint8_t)~(UART3_SR_RXNE);\r
+ }\r
+ /*Clear the LIN Break Detection flag */\r
+ else if (UART3_FLAG == UART3_FLAG_LBDF)\r
+ {\r
+ UART3->CR4 &= (uint8_t)(~UART3_CR4_LBDF);\r
+ }\r
+ /*Clear the LIN Header Detection Flag */\r
+ else if (UART3_FLAG == UART3_FLAG_LHDF)\r
+ {\r
+ UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);\r
+ }\r
+ /*Clear the LIN Synch Field flag */\r
+ else\r
+ {\r
+ UART3->CR6 &= (uint8_t)(~UART3_CR6_LSF);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified UART3 interrupt has occurred or not.\r
+ * @param UART3_IT: Specifies the UART3 interrupt pending bit to check.\r
+ * This parameter can be one of the following values:\r
+ * - UART3_IT_LBDF: LIN Break detection interrupt\r
+ * - UART3_IT_TXE: Tansmit Data Register empty interrupt\r
+ * - UART3_IT_TC: Transmission complete interrupt\r
+ * - UART3_IT_RXNE: Receive Data register not empty interrupt\r
+ * - UART3_IT_IDLE: Idle line detection interrupt\r
+ * - UART3_IT_OR: OverRun Error interrupt\r
+ * - UART3_IT_PE: Parity Error interrupt\r
+ * @retval The state of UART3_IT (SET or RESET).\r
+ */\r
+ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ uint8_t itpos = 0;\r
+ uint8_t itmask1 = 0;\r
+ uint8_t itmask2 = 0;\r
+ uint8_t enablestatus = 0;\r
+\r
+ /* Check parameters */\r
+ assert_param(IS_UART3_GET_IT_OK(UART3_IT));\r
+\r
+ /* Get the UART3 IT index*/\r
+ itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART3_IT & (uint8_t)0x0F));\r
+ /* Get the UART3 IT index*/\r
+ itmask1 = (uint8_t)((uint8_t)UART3_IT >> (uint8_t)4);\r
+ /* Set the IT mask*/\r
+ itmask2 = (uint8_t)((uint8_t)1 << itmask1);\r
+\r
+ /* Check the status of the specified UART3 pending bit*/\r
+ if (UART3_IT == UART3_IT_PE)\r
+ {\r
+ /* Get the UART3_ITPENDINGBIT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART3->CR1 & itmask2);\r
+ /* Check the status of the specified UART3 interrupt*/\r
+\r
+ if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else if (UART3_IT == UART3_IT_LBDF)\r
+ {\r
+ /* Get the UART3_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART3->CR4 & itmask2);\r
+ /* Check the status of the specified UART3 interrupt*/\r
+ if (((UART3->CR4 & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else if (UART3_IT == UART3_IT_LHDF)\r
+ {\r
+ /* Get the UART3_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART3->CR6 & itmask2);\r
+ /* Check the status of the specified UART3 interrupt*/\r
+ if (((UART3->CR6 & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Get the UART3_IT enable bit status*/\r
+ enablestatus = (uint8_t)((uint8_t)UART3->CR2 & itmask2);\r
+ /* Check the status of the specified UART3 interrupt*/\r
+ if (((UART3->SR & itpos) != (uint8_t)0x00) && enablestatus)\r
+ {\r
+ /* Interrupt occurred*/\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* Interrupt not occurred*/\r
+ pendingbitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the UART3_IT status*/\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the UART3 pending flags.\r
+ * @param UART3_IT specifies the pending bit to clear\r
+ * This parameter can be one of the following values:\r
+ * - UART3_IT_LBDF: LIN Break detection interrupt\r
+ * - UART3_IT_LHDF: LIN Header detection interrupt\r
+ * - UART3_IT_RXNE: Receive Data register not empty interrupt.\r
+ *\r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NF (Noise error), \r
+ * OR (OverRun error) and IDLE (Idle line detected) pending bits are \r
+ * cleared by software sequence: a read operation to UART3_SR register\r
+ * (UART3_GetITStatus()) followed by a read operation to UART3_DR register \r
+ * (UART3_ReceiveData8() or UART3_ReceiveData9()).\r
+ * \r
+ * - RXNE pending bit can be also cleared by a read to the UART3_DR register\r
+ * (UART3_ReceiveData8() or UART3_ReceiveData9() ).\r
+ * \r
+ * - TC (Transmit complete) pending bit can be cleared by software \r
+ * sequence: a read operation to UART3_SR register (UART3_GetITStatus())\r
+ * followed by a write operation to UART3_DR register \r
+ * (UART3_SendData8()or UART3_SendData9()).\r
+ * \r
+ * - TXE pending bit is cleared only by a write to the UART3_DR register\r
+ * (UART3_SendData8() or UART3_SendData9()).\r
+ * @retval None\r
+ */\r
+void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_UART3_CLEAR_IT_OK(UART3_IT));\r
+\r
+ /*Clear the Receive Register Not Empty pending bit */\r
+ if (UART3_IT == UART3_IT_RXNE)\r
+ {\r
+ UART3->SR = (uint8_t)~(UART3_SR_RXNE);\r
+ }\r
+ /*Clear the LIN Break Detection pending bit */\r
+ else if (UART3_IT == UART3_IT_LBDF)\r
+ {\r
+ UART3->CR4 &= (uint8_t)~(UART3_CR4_LBDF);\r
+ }\r
+ /*Clear the LIN Header Detection pending bit */\r
+ else\r
+ {\r
+ UART3->CR6 &= (uint8_t)(~UART3_CR6_LHDF);\r
+ }\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ********************************************************************************\r
+ * @file stm8s_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all the functions for the WWDG peripheral.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm8s_wwdg.h"\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+/* Private define ------------------------------------------------------------*/\r
+#define BIT_MASK ((uint8_t)0x7F)\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/** @addtogroup WWDG_Public_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Initializes the WWDG peripheral.\r
+ * This function set Window Register = WindowValue, Counter Register\r
+ * according to Counter and \b ENABLE \b WWDG\r
+ * @param Counter : WWDG counter value\r
+ * @param WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_Init(uint8_t Counter, uint8_t WindowValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));\r
+ \r
+ WWDG->WR = WWDG_WR_RESET_VALUE;\r
+ WWDG->CR = (uint8_t)((uint8_t)(WWDG_CR_WDGA | WWDG_CR_T6) | (uint8_t)Counter);\r
+ WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));\r
+}\r
+\r
+/**\r
+ * @brief Refreshes the WWDG peripheral.\r
+ * @param Counter : WWDG Counter Value\r
+ * This parameter must be a number between 0x40 and 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTERVALUE_OK(Counter));\r
+\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);\r
+\r
+}\r
+\r
+/**\r
+ * @brief Gets the WWDG Counter Value.\r
+ * This value could be used to check if WWDG is in the window, where\r
+ * refresh is allowed.\r
+ * @param None\r
+ * @retval WWDG Counter Value\r
+ */\r
+uint8_t WWDG_GetCounter(void)\r
+{\r
+ return(WWDG->CR);\r
+}\r
+\r
+/**\r
+ * @brief Generates immediate WWDG RESET.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_SWReset(void)\r
+{\r
+ WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the\r
+ * downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOWLIMITVALUE_OK(WindowValue));\r
+ \r
+ WWDG->WR = (uint8_t)((uint8_t)(~WWDG_CR_WDGA) & (uint8_t)(WWDG_CR_T6 | WindowValue));\r
+}\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+ \r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+#include "lcd.h"
+
+void main()
+{
+ lcd_init();
+ clear_display();
+ move_to(0, 0);
+ draw_string("test");
+
+ return;
+}
+
projects / stm8dev.git / commitdiff