+/**\r
+ ******************************************************************************\r
+ * @file stm8s.h\r
+ * @author MCD Application Team\r
+ * @version V2.1.0\r
+ * @date 18-November-2011\r
+ * @brief This file contains all HW registers definitions and memory mapping.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM8S_H\r
+#define __STM8S_H\r
+\r
+/** @addtogroup STM8S_StdPeriph_Driver\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM8S or STM8A device used in your\r
+ application. */\r
+\r
+ /* #define STM8S208 */ /*!< STM8S High density devices with CAN */\r
+ /* #define STM8S207 */ /*!< STM8S High density devices without CAN */\r
+ /* #define STM8S007 */ /*!< STM8S Value Line High density devices */\r
+ /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */\r
+ /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */\r
+ /* #define STM8S105 */ /*!< STM8S Medium density devices */\r
+ /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */\r
+ /* #define STM8AF626x */ /*!< STM8A Medium density devices */\r
+ /* #define STM8S103 */ /*!< STM8S Low density devices */\r
+ /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */\r
+ /* #define STM8S903 */ /*!< STM8S Low density devices */\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor. \r
+\r
+ - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,\r
+ STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory\r
+ density ranges between 32 to 128 Kbytes\r
+ - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,\r
+ STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory \r
+ density ranges between 8 to 32 Kbytes\r
+ - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers\r
+ where the Flash memory density ranges between 32 to 128 Kbytes.\r
+ - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers\r
+ where the Flash memory density ranges between 16 to 32-Kbytes.\r
+ - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers\r
+ where the Flash density is 8 Kbytes. */\r
+\r
+#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \\r
+ !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \\r
+ !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \\r
+ !defined (STM8S003)&& !defined (STM8S005) \r
+ #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)"\r
+#endif\r
+\r
+/******************************************************************************/\r
+/* Library configuration section */\r
+/******************************************************************************/\r
+/* Check the used compiler */\r
+#if defined(__CSMC__)\r
+ #define _COSMIC_\r
+#elif defined(__RCST7__)\r
+ #define _RAISONANCE_\r
+#elif defined(__ICCSTM8__)\r
+ #define _IAR_\r
+#else\r
+ #error "Unsupported Compiler!" /* Compiler defines not found */\r
+#endif\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/* Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will be\r
+ based on direct access to peripherals registers */\r
+ #define USE_STDPERIPH_DRIVER\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application\r
+\r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */\r
+#if !defined HSE_Value\r
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define HSE_VALUE ((u32)24000000) /* Value of the External oscillator in Hz*/\r
+ #else\r
+ #define HSE_VALUE ((u32)16000000) /* Value of the External oscillator in Hz*/\r
+ #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax */\r
+#endif /* HSE_Value */\r
+\r
+/**\r
+ * @brief Definition of Device on-chip RC oscillator frequencies\r
+ */\r
+#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */\r
+#define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */\r
+\r
+#ifdef _COSMIC_\r
+ #define FAR @far\r
+ #define NEAR @near\r
+ #define TINY @tiny\r
+ #define EEPROM @eeprom\r
+ #define CONST const\r
+#elif defined (_RAISONANCE_) /* __RCST7__ */\r
+ #define FAR far\r
+ #define NEAR data\r
+ #define TINY page0\r
+ #define EEPROM eeprom\r
+ #define CONST code\r
+ #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ /*!< Used with memory Models for code higher than 64K */\r
+ #define MEMCPY fmemcpy\r
+ #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x */\r
+ /*!< Used with memory Models for code less than 64K */\r
+ #define MEMCPY memcpy\r
+ #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */ \r
+#else /*_IAR_*/\r
+ #define FAR __far\r
+ #define NEAR __near\r
+ #define TINY __tiny\r
+ #define EEPROM __eeprom\r
+ #define CONST const\r
+#endif /* __CSMC__ */\r
+\r
+/* For FLASH routines, select whether pointer will be declared as near (2 bytes,\r
+ to handle code smaller than 64KB) or far (3 bytes, to handle code larger \r
+ than 64K) */\r
+\r
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \\r
+ defined (STM8S903) || defined (STM8AF626x)\r
+/*!< Used with memory Models for code smaller than 64K */\r
+ #define PointerAttr NEAR\r
+#else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */\r
+/*!< Used with memory Models for code higher than 64K */\r
+ #define PointerAttr FAR\r
+#endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x */\r
+\r
+/* Uncomment the line below to enable the FLASH functions execution from RAM */\r
+#if !defined (RAM_EXECUTION)\r
+/* #define RAM_EXECUTION (1) */\r
+#endif /* RAM_EXECUTION */\r
+\r
+#ifdef RAM_EXECUTION\r
+ #ifdef _COSMIC_\r
+ #define IN_RAM(a) a\r
+ #elif defined (_RAISONANCE_) /* __RCST7__ */\r
+ #define IN_RAM(a) a inram\r
+ #else /*_IAR_*/\r
+ #define IN_RAM(a) __ramfunc a\r
+ #endif /* _COSMIC_ */\r
+#else \r
+ #define IN_RAM(a) a\r
+#endif /* RAM_EXECUTION */\r
+\r
+/*!< [31:16] STM8S Standard Peripheral Library main version V2.1.0*/\r
+#define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */ \r
+#define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x01) /*!< [23:16] sub1 version */\r
+#define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */\r
+#define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ \r
+#define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM8S_STDPERIPH_VERSION_RC))\r
+\r
+/******************************************************************************/\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/* Exported types and constants ----------------------------------------------*/\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*!< Signed integer types */\r
+typedef signed char int8_t;\r
+typedef signed short int16_t;\r
+typedef signed long int32_t;\r
+\r
+/*!< Unsigned integer types */\r
+typedef unsigned char uint8_t;\r
+typedef unsigned short uint16_t;\r
+typedef unsigned long uint32_t;\r
+\r
+/*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */\r
+\r
+typedef int32_t s32;\r
+typedef int16_t s16;\r
+typedef int8_t s8;\r
+\r
+typedef uint32_t u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t u8;\r
+\r
+\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+#define U8_MAX (255)\r
+#define S8_MAX (127)\r
+#define S8_MIN (-128)\r
+#define U16_MAX (65535u)\r
+#define S16_MAX (32767)\r
+#define S16_MIN (-32768)\r
+#define U32_MAX (4294967295uL)\r
+#define S32_MAX (2147483647)\r
+#define S32_MIN (-2147483648uL)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup MAP_FILE_Exported_Types_and_Constants\r
+ * @{\r
+ */\r
+\r
+/******************************************************************************/\r
+/* IP registers structures */\r
+/******************************************************************************/\r
+\r
+/**\r
+ * @brief General Purpose I/Os (GPIO)\r
+ */\r
+typedef struct GPIO_struct\r
+{\r
+ __IO uint8_t ODR; /*!< Output Data Register */\r
+ __IO uint8_t IDR; /*!< Input Data Register */\r
+ __IO uint8_t DDR; /*!< Data Direction Register */\r
+ __IO uint8_t CR1; /*!< Configuration Register 1 */\r
+ __IO uint8_t CR2; /*!< Configuration Register 2 */\r
+}\r
+GPIO_TypeDef;\r
+\r
+/** @addtogroup GPIO_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+/**\r
+ * @brief Analog to Digital Converter (ADC1)\r
+ */\r
+ typedef struct ADC1_struct\r
+ {\r
+ __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */\r
+ __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */\r
+ uint8_t RESERVED[12]; /*!< Reserved byte */\r
+ __IO uint8_t CSR; /*!< ADC1 control status register */\r
+ __IO uint8_t CR1; /*!< ADC1 configuration register 1 */\r
+ __IO uint8_t CR2; /*!< ADC1 configuration register 2 */\r
+ __IO uint8_t CR3; /*!< ADC1 configuration register 3 */\r
+ __IO uint8_t DRH; /*!< ADC1 Data high */\r
+ __IO uint8_t DRL; /*!< ADC1 Data low */\r
+ __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */\r
+ __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */\r
+ __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/\r
+ __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/\r
+ __IO uint8_t LTRH; /*!< ADC1 low threshold register high */\r
+ __IO uint8_t LTRL; /*!< ADC1 low threshold register low */\r
+ __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */\r
+ __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */\r
+ __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */\r
+ __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */\r
+ }\r
+ ADC1_TypeDef;\r
+\r
+/** @addtogroup ADC1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+ #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03)\r
+ #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF)\r
+ #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */\r
+ #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */\r
+ #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */\r
+ #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */\r
+ #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */\r
+\r
+ #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */\r
+ #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */\r
+ #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */\r
+\r
+ #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */\r
+ #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */\r
+ #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */\r
+ #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */\r
+\r
+ #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */\r
+ #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */\r
+\r
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Analog to Digital Converter (ADC2)\r
+ */\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax)\r
+ typedef struct ADC2_struct\r
+ {\r
+ __IO uint8_t CSR; /*!< ADC2 control status register */\r
+ __IO uint8_t CR1; /*!< ADC2 configuration register 1 */\r
+ __IO uint8_t CR2; /*!< ADC2 configuration register 2 */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t DRH; /*!< ADC2 Data high */\r
+ __IO uint8_t DRL; /*!< ADC2 Data low */\r
+ __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */\r
+ __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */\r
+ }\r
+ ADC2_TypeDef;\r
+\r
+/** @addtogroup ADC2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+ #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)\r
+ #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup ADC2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */\r
+ #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */\r
+ #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */\r
+\r
+ #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */\r
+ #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */\r
+ #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */\r
+\r
+ #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */\r
+ #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */\r
+ #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */\r
+\r
+#endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Auto Wake Up (AWU) peripheral registers.\r
+ */\r
+typedef struct AWU_struct\r
+{\r
+ __IO uint8_t CSR; /*!< AWU Control status register */\r
+ __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */\r
+ __IO uint8_t TBR; /*!< AWU Time base selection register */\r
+}\r
+AWU_TypeDef;\r
+\r
+/** @addtogroup AWU_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define AWU_CSR_RESET_VALUE ((uint8_t)0x00)\r
+#define AWU_APR_RESET_VALUE ((uint8_t)0x3F)\r
+#define AWU_TBR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup AWU_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */\r
+#define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */\r
+#define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */\r
+\r
+#define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */\r
+\r
+#define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Beeper (BEEP) peripheral registers.\r
+ */\r
+\r
+typedef struct BEEP_struct\r
+{\r
+ __IO uint8_t CSR; /*!< BEEP Control status register */\r
+}\r
+BEEP_TypeDef;\r
+\r
+/** @addtogroup BEEP_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup BEEP_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+#define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */\r
+#define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */\r
+#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Clock Controller (CLK)\r
+ */\r
+typedef struct CLK_struct\r
+{\r
+ __IO uint8_t ICKR; /*!< Internal Clocks Control Register */\r
+ __IO uint8_t ECKR; /*!< External Clocks Control Register */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t CMSR; /*!< Clock Master Status Register */\r
+ __IO uint8_t SWR; /*!< Clock Master Switch Register */\r
+ __IO uint8_t SWCR; /*!< Switch Control Register */\r
+ __IO uint8_t CKDIVR; /*!< Clock Divider Register */\r
+ __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */\r
+ __IO uint8_t CSSR; /*!< Clock Security System Register */\r
+ __IO uint8_t CCOR; /*!< Configurable Clock Output Register */\r
+ __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */\r
+ __IO uint8_t SWIMCCR; /*!< SWIM clock control register */\r
+}\r
+CLK_TypeDef;\r
+\r
+/** @addtogroup CLK_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)\r
+#define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)\r
+#define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)\r
+#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)\r
+#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)\r
+#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)\r
+#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)\r
+#define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CLK_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+#define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */\r
+#define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */\r
+#define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */\r
+#define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */\r
+#define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */\r
+#define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */\r
+\r
+#define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */\r
+#define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */\r
+\r
+#define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */\r
+\r
+#define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */\r
+\r
+#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */\r
+#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */\r
+#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */\r
+#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/\r
+\r
+#define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */\r
+#define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */\r
+\r
+#define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */ \r
+#define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */\r
+#define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */\r
+#define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */\r
+#define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */\r
+#define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */\r
+#define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */\r
+#define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */\r
+#define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */\r
+#define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */\r
+#define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */\r
+\r
+#define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */\r
+#define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */\r
+#define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */\r
+\r
+#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */\r
+#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */\r
+#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */\r
+#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */\r
+\r
+#define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */\r
+#define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */\r
+#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */\r
+#define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */\r
+\r
+#define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */\r
+\r
+#define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer with complementary PWM outputs (TIM1)\r
+ */\r
+\r
+typedef struct TIM1_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t SMCR; /*!< Synchro mode control register */\r
+ __IO uint8_t ETR; /*!< external trigger register */\r
+ __IO uint8_t IER; /*!< interrupt enable register*/\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */\r
+ __IO uint8_t CCMR4; /*!< CC mode register 4 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CCER2; /*!< CC enable register 2 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCRH; /*!< prescaler high */\r
+ __IO uint8_t PSCRL; /*!< prescaler low */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t RCR; /*!< Repetition Counter register */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */\r
+ __IO uint8_t CCR4H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR4L; /*!< capture/compare register 3 low */\r
+ __IO uint8_t BKR; /*!< Break Register */\r
+ __IO uint8_t DTR; /*!< dead-time register */\r
+ __IO uint8_t OISR; /*!< Output idle register */\r
+}\r
+TIM1_TypeDef;\r
+\r
+/** @addtogroup TIM1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */\r
+#define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */\r
+#define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/* CR2*/\r
+#define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */\r
+#define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */\r
+#define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */\r
+#define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */\r
+/* SMCR*/\r
+#define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */\r
+#define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */\r
+#define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */\r
+/*ETR*/\r
+#define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */\r
+#define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */\r
+#define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */\r
+#define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */\r
+/*IER*/\r
+#define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */\r
+#define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */\r
+#define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/\r
+#define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */\r
+#define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */\r
+#define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */\r
+#define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */\r
+#define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */\r
+#define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */\r
+#define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */\r
+#define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+\r
+#define CCMR_TIxDirect_Set ((uint8_t)0x01)\r
+/*CCER1*/\r
+#define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */\r
+#define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */\r
+#define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */\r
+#define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */\r
+#define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */\r
+#define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */\r
+#define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */\r
+#define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */\r
+#define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTRH*/\r
+#define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+/*CNTRL*/\r
+#define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCH*/\r
+#define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*PSCL*/\r
+#define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */\r
+/*ARR*/\r
+#define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*RCR*/\r
+#define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */\r
+/*CCR1*/\r
+#define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+/*CCR4*/\r
+#define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */\r
+#define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */\r
+/*BKR*/\r
+#define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */\r
+#define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */\r
+#define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */\r
+#define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */\r
+#define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */\r
+#define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */\r
+#define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */\r
+/*DTR*/\r
+#define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */\r
+/*OISR*/\r
+#define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */\r
+#define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */\r
+#define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */\r
+#define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */\r
+#define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */\r
+#define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */\r
+#define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer (TIM2)\r
+ */\r
+\r
+typedef struct TIM2_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+#if defined(STM8S103) || defined(STM8S003)\r
+ uint8_t RESERVED1; /*!< Reserved register */\r
+ uint8_t RESERVED2; /*!< Reserved register */\r
+#endif\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCMR3; /*!< CC mode register 3 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CCER2; /*!< CC enable register 2 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+ __IO uint8_t CCR3H; /*!< capture/compare register 3 high */\r
+ __IO uint8_t CCR3L; /*!< capture/compare register 3 low */\r
+}\r
+TIM2_TypeDef;\r
+\r
+/** @addtogroup TIM2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTR*/\r
+#define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer (TIM3)\r
+ */\r
+typedef struct TIM3_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t SR2; /*!< status register 2 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CCMR1; /*!< CC mode register 1 */\r
+ __IO uint8_t CCMR2; /*!< CC mode register 2 */\r
+ __IO uint8_t CCER1; /*!< CC enable register 1 */\r
+ __IO uint8_t CNTRH; /*!< counter high */\r
+ __IO uint8_t CNTRL; /*!< counter low */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARRH; /*!< auto-reload register high */\r
+ __IO uint8_t ARRL; /*!< auto-reload register low */\r
+ __IO uint8_t CCR1H; /*!< capture/compare register 1 high */\r
+ __IO uint8_t CCR1L; /*!< capture/compare register 1 low */\r
+ __IO uint8_t CCR2H; /*!< capture/compare register 2 high */\r
+ __IO uint8_t CCR2L; /*!< capture/compare register 2 low */\r
+}\r
+TIM3_TypeDef;\r
+\r
+/** @addtogroup TIM3_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM3_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CNTR*/\r
+#define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 8-bit system timer (TIM4)\r
+ */\r
+\r
+typedef struct TIM4_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+#if defined(STM8S103) || defined(STM8S003)\r
+ uint8_t RESERVED1; /*!< Reserved register */\r
+ uint8_t RESERVED2; /*!< Reserved register */\r
+#endif\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CNTR; /*!< counter register */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARR; /*!< auto-reload register */\r
+}\r
+TIM4_TypeDef;\r
+\r
+/** @addtogroup TIM4_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM4_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*CR1*/\r
+#define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/*IER*/\r
+#define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*EGR*/\r
+#define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CNTR*/\r
+#define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */\r
+/*ARR*/\r
+#define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 16-bit timer with synchro module (TIM5)\r
+ */\r
+\r
+typedef struct TIM5_struct\r
+{\r
+ __IO uint8_t CR1; /*!<TIM5 Control Register 1 */\r
+ __IO uint8_t CR2; /*!<TIM5 Control Register 2 */\r
+ __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */\r
+ __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */\r
+ __IO uint8_t SR1; /*!<TIM5 Status Register 1 */\r
+ __IO uint8_t SR2; /*!<TIM5 Status Register 2 */\r
+ __IO uint8_t EGR; /*!<TIM5 Event Generation Register */\r
+ __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */\r
+ __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */\r
+ __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */\r
+ __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */\r
+ __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */\r
+ __IO uint8_t CNTRH; /*!<TIM5 Counter High */\r
+ __IO uint8_t CNTRL; /*!<TIM5 Counter Low */\r
+ __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */\r
+ __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */\r
+ __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */\r
+ __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */\r
+ __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */\r
+ __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */\r
+ __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */\r
+ __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */\r
+ __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */\r
+}TIM5_TypeDef;\r
+\r
+/** @addtogroup TIM5_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)\r
+#define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup TIM5_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */\r
+#define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */\r
+#define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */\r
+#define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */\r
+#define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */\r
+/* CR2*/\r
+#define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */\r
+#define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */\r
+/* SMCR*/\r
+#define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */\r
+#define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */\r
+#define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */\r
+/*IER*/\r
+#define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */\r
+#define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */\r
+#define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */\r
+#define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */\r
+#define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */\r
+/*SR1*/\r
+#define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */\r
+#define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */\r
+#define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */\r
+#define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */\r
+/*SR2*/\r
+#define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */\r
+#define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */\r
+#define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */\r
+/*EGR*/\r
+#define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */\r
+#define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */\r
+#define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */\r
+#define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */\r
+/*CCMR*/\r
+#define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */\r
+#define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */\r
+#define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */\r
+#define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */\r
+#define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */\r
+/*CCER1*/\r
+#define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */\r
+#define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */\r
+#define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */\r
+#define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */\r
+/*CCER2*/\r
+#define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */\r
+#define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */\r
+/*CNTR*/\r
+#define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */\r
+#define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */\r
+/*PSCR*/\r
+#define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */\r
+/*ARR*/\r
+#define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */\r
+#define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */\r
+/*CCR1*/\r
+#define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */\r
+#define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */\r
+/*CCR2*/\r
+#define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */\r
+#define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */\r
+/*CCR3*/\r
+#define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */\r
+#define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */\r
+/*CCMR*/\r
+#define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief 8-bit system timer with synchro module(TIM6)\r
+ */\r
+\r
+typedef struct TIM6_struct\r
+{\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t SMCR; /*!< Synchro mode control register */\r
+ __IO uint8_t IER; /*!< interrupt enable register */\r
+ __IO uint8_t SR1; /*!< status register 1 */\r
+ __IO uint8_t EGR; /*!< event generation register */\r
+ __IO uint8_t CNTR; /*!< counter register */\r
+ __IO uint8_t PSCR; /*!< prescaler register */\r
+ __IO uint8_t ARR; /*!< auto-reload register */\r
+}\r
+TIM6_TypeDef;\r
+/** @addtogroup TIM6_Registers_Reset_Value\r
+ * @{\r
+ */\r
+#define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+#define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+* @}\r
+*/\r
+\r
+/** @addtogroup TIM6_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/* CR1*/\r
+#define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */\r
+#define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */\r
+#define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */\r
+#define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */\r
+#define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */\r
+/* CR2*/\r
+#define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */\r
+/* SMCR*/\r
+#define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */\r
+#define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */\r
+#define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */\r
+/* IER*/\r
+#define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */\r
+#define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */\r
+/* SR1*/\r
+#define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */\r
+#define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */\r
+/* EGR*/\r
+#define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */\r
+#define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */\r
+/* CNTR*/\r
+#define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */\r
+/* PSCR*/\r
+#define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */\r
+\r
+#define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */\r
+/**\r
+ * @}\r
+ */\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Inter-Integrated Circuit (I2C)\r
+ */\r
+\r
+typedef struct I2C_struct\r
+{\r
+ __IO uint8_t CR1; /*!< I2C control register 1 */\r
+ __IO uint8_t CR2; /*!< I2C control register 2 */\r
+ __IO uint8_t FREQR; /*!< I2C frequency register */\r
+ __IO uint8_t OARL; /*!< I2C own address register LSB */\r
+ __IO uint8_t OARH; /*!< I2C own address register MSB */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ __IO uint8_t DR; /*!< I2C data register */\r
+ __IO uint8_t SR1; /*!< I2C status register 1 */\r
+ __IO uint8_t SR2; /*!< I2C status register 2 */\r
+ __IO uint8_t SR3; /*!< I2C status register 3 */\r
+ __IO uint8_t ITR; /*!< I2C interrupt register */\r
+ __IO uint8_t CCRL; /*!< I2C clock control register low */\r
+ __IO uint8_t CCRH; /*!< I2C clock control register high */\r
+ __IO uint8_t TRISER; /*!< I2C maximum rise time register */\r
+ uint8_t RESERVED2; /*!< Reserved byte */\r
+}\r
+I2C_TypeDef;\r
+\r
+/** @addtogroup I2C_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define I2C_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_OARL_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_OARH_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_DR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR1_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR2_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_SR3_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_ITR_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)\r
+#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup I2C_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */\r
+#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */\r
+\r
+#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */\r
+#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */\r
+#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */\r
+#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */\r
+#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */\r
+\r
+#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */\r
+\r
+#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */\r
+#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */\r
+\r
+#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */\r
+#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */\r
+#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */\r
+\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */\r
+\r
+#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */\r
+#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */\r
+#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */\r
+#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */\r
+#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */\r
+#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */\r
+\r
+#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */\r
+#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */\r
+#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */\r
+#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */\r
+#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */\r
+\r
+#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */\r
+#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */\r
+#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */\r
+#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */\r
+\r
+#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */\r
+#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */\r
+#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */\r
+\r
+#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */\r
+\r
+#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */\r
+#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */\r
+#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */\r
+\r
+#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Interrupt Controller (ITC)\r
+ */\r
+\r
+typedef struct ITC_struct\r
+{\r
+ __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */\r
+ __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */\r
+ __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */\r
+ __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */\r
+ __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */\r
+ __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */\r
+ __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */\r
+ __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */\r
+}\r
+ITC_TypeDef;\r
+\r
+/** @addtogroup ITC_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CPU_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief External Interrupt Controller (EXTI)\r
+ */\r
+\r
+typedef struct EXTI_struct\r
+{\r
+ __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */\r
+ __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */\r
+}\r
+EXTI_TypeDef;\r
+\r
+/** @addtogroup EXTI_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup EXTI_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */\r
+#define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */\r
+\r
+#define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */\r
+#define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief FLASH program and Data memory (FLASH)\r
+ */\r
+\r
+typedef struct FLASH_struct\r
+{\r
+ __IO uint8_t CR1; /*!< Flash control register 1 */\r
+ __IO uint8_t CR2; /*!< Flash control register 2 */\r
+ __IO uint8_t NCR2; /*!< Flash complementary control register 2 */\r
+ __IO uint8_t FPR; /*!< Flash protection register */\r
+ __IO uint8_t NFPR; /*!< Flash complementary protection register */\r
+ __IO uint8_t IAPSR; /*!< Flash in-application programming status register */\r
+ uint8_t RESERVED1; /*!< Reserved byte */\r
+ uint8_t RESERVED2; /*!< Reserved byte */\r
+ __IO uint8_t PUKR; /*!< Flash program memory unprotection register */\r
+ uint8_t RESERVED3; /*!< Reserved byte */\r
+ __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */\r
+}\r
+FLASH_TypeDef;\r
+\r
+/** @addtogroup FLASH_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)\r
+#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)\r
+#define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)\r
+#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup FLASH_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */\r
+#define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */\r
+#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */\r
+#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */\r
+\r
+#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */\r
+#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */\r
+#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */\r
+#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */\r
+#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */\r
+\r
+#define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */\r
+#define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */\r
+#define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */\r
+#define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */\r
+#define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */\r
+\r
+#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */\r
+#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */\r
+#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */\r
+#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */\r
+#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */\r
+\r
+#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */\r
+\r
+#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Option Bytes (OPT)\r
+ */\r
+typedef struct OPT_struct\r
+{\r
+ __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */\r
+ __IO uint8_t OPT1; /*!< Option byte 1: User boot code */\r
+ __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */\r
+ __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */\r
+ __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */\r
+ __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */\r
+ __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */\r
+ __IO uint8_t OPT4; /*!< Option byte 4: Clock option */\r
+ __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */\r
+ __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */\r
+ __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */\r
+ uint8_t RESERVED1; /*!< Reserved Option byte*/\r
+ uint8_t RESERVED2; /*!< Reserved Option byte*/\r
+ __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */\r
+ __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */\r
+}\r
+OPT_TypeDef;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Independent Watchdog (IWDG)\r
+ */\r
+\r
+typedef struct IWDG_struct\r
+{\r
+ __IO uint8_t KR; /*!< Key Register */\r
+ __IO uint8_t PR; /*!< Prescaler Register */\r
+ __IO uint8_t RLR; /*!< Reload Register */\r
+}\r
+IWDG_TypeDef;\r
+\r
+/** @addtogroup IWDG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define IWDG_PR_RESET_VALUE ((uint8_t)0x00)\r
+#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Window Watchdog (WWDG)\r
+ */\r
+\r
+typedef struct WWDG_struct\r
+{\r
+ __IO uint8_t CR; /*!< Control Register */\r
+ __IO uint8_t WR; /*!< Window Register */\r
+}\r
+WWDG_TypeDef;\r
+\r
+/** @addtogroup WWDG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)\r
+#define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup WWDG_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */\r
+\r
+#define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */\r
+#define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Reset Controller (RST)\r
+ */\r
+\r
+typedef struct RST_struct\r
+{\r
+ __IO uint8_t SR; /*!< Reset status register */\r
+}\r
+RST_TypeDef;\r
+\r
+/** @addtogroup RST_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */\r
+#define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */\r
+#define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */\r
+#define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */\r
+#define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Serial Peripheral Interface (SPI)\r
+ */\r
+\r
+typedef struct SPI_struct\r
+{\r
+ __IO uint8_t CR1; /*!< SPI control register 1 */\r
+ __IO uint8_t CR2; /*!< SPI control register 2 */\r
+ __IO uint8_t ICR; /*!< SPI interrupt control register */\r
+ __IO uint8_t SR; /*!< SPI status register */\r
+ __IO uint8_t DR; /*!< SPI data I/O register */\r
+ __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */\r
+ __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */\r
+ __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */\r
+}\r
+SPI_TypeDef;\r
+\r
+/** @addtogroup SPI_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */\r
+#define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */\r
+#define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register reset value */\r
+#define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */\r
+#define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */\r
+#define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */\r
+#define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */\r
+#define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup SPI_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */\r
+#define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */\r
+#define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */\r
+#define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */\r
+#define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */\r
+#define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */\r
+\r
+#define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */\r
+#define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */\r
+#define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */\r
+#define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */\r
+#define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */\r
+#define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */\r
+#define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */\r
+\r
+#define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */\r
+#define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */\r
+#define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */\r
+#define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */\r
+\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */\r
+#define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)\r
+ */\r
+\r
+typedef struct UART1_struct\r
+{\r
+ __IO uint8_t SR; /*!< UART1 status register */\r
+ __IO uint8_t DR; /*!< UART1 data register */\r
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */\r
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< UART1 control register 1 */\r
+ __IO uint8_t CR2; /*!< UART1 control register 2 */\r
+ __IO uint8_t CR3; /*!< UART1 control register 3 */\r
+ __IO uint8_t CR4; /*!< UART1 control register 4 */\r
+ __IO uint8_t CR5; /*!< UART1 control register 5 */\r
+ __IO uint8_t GTR; /*!< UART1 guard time register */\r
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */\r
+}\r
+UART1_TypeDef;\r
+\r
+/** @addtogroup UART1_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART1_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_CR5_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_GTR_RESET_VALUE ((uint8_t)0x00)\r
+#define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART1_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */\r
+\r
+#define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */\r
+#define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */\r
+\r
+#define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */\r
+#define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */\r
+#define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */\r
+#define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */\r
+\r
+#define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+#define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */\r
+#define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */\r
+#define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */\r
+#define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */\r
+\r
+#define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */\r
+\r
+#define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */\r
+#define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */\r
+#define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */\r
+#define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */\r
+#define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)\r
+ */\r
+\r
+typedef struct UART2_struct\r
+{\r
+ __IO uint8_t SR; /*!< UART1 status register */\r
+ __IO uint8_t DR; /*!< UART1 data register */\r
+ __IO uint8_t BRR1; /*!< UART1 baud rate register */\r
+ __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< UART1 control register 1 */\r
+ __IO uint8_t CR2; /*!< UART1 control register 2 */\r
+ __IO uint8_t CR3; /*!< UART1 control register 3 */\r
+ __IO uint8_t CR4; /*!< UART1 control register 4 */\r
+ __IO uint8_t CR5; /*!< UART1 control register 5 */\r
+ __IO uint8_t CR6; /*!< UART1 control register 6 */\r
+ __IO uint8_t GTR; /*!< UART1 guard time register */\r
+ __IO uint8_t PSCR; /*!< UART1 prescaler register */\r
+}\r
+UART2_TypeDef;\r
+\r
+/** @addtogroup UART2_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART2_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR5_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_CR6_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_GTR_RESET_VALUE ((uint8_t)0x00)\r
+#define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART2_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */\r
+\r
+#define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */\r
+#define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */\r
+\r
+#define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */\r
+#define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */\r
+#define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */\r
+#define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */\r
+\r
+#define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+#define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */\r
+#define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */\r
+#define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */\r
+#define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */\r
+\r
+#define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */\r
+\r
+#define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */\r
+#define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */\r
+#define UART2_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */\r
+#define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */\r
+#define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */\r
+\r
+#define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */\r
+#define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */\r
+#define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */\r
+#define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */\r
+#define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */\r
+#define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)\r
+ */\r
+\r
+typedef struct UART3_struct\r
+{\r
+ __IO uint8_t SR; /*!< status register */\r
+ __IO uint8_t DR; /*!< data register */\r
+ __IO uint8_t BRR1; /*!< baud rate register */\r
+ __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */\r
+ __IO uint8_t CR1; /*!< control register 1 */\r
+ __IO uint8_t CR2; /*!< control register 2 */\r
+ __IO uint8_t CR3; /*!< control register 3 */\r
+ __IO uint8_t CR4; /*!< control register 4 */\r
+ uint8_t RESERVED; /*!< Reserved byte */\r
+ __IO uint8_t CR6; /*!< control register 5 */\r
+}\r
+UART3_TypeDef;\r
+\r
+/** @addtogroup UART3_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define UART3_SR_RESET_VALUE ((uint8_t)0xC0)\r
+#define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR1_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR2_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR3_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR4_RESET_VALUE ((uint8_t)0x00)\r
+#define UART3_CR6_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup UART3_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */\r
+#define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */\r
+#define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */\r
+#define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */\r
+#define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */\r
+#define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */\r
+#define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */\r
+#define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */\r
+\r
+#define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */\r
+\r
+#define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */\r
+#define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */\r
+\r
+#define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */\r
+#define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */\r
+#define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */\r
+#define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */\r
+#define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */\r
+#define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */\r
+#define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */\r
+#define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */\r
+\r
+#define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */\r
+#define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */\r
+#define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */\r
+#define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */\r
+#define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */\r
+#define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */\r
+#define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */\r
+#define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */\r
+\r
+#define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */\r
+#define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */\r
+\r
+#define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */\r
+#define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */\r
+#define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */\r
+#define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */\r
+\r
+#define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */\r
+#define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */\r
+#define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */\r
+#define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */\r
+#define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */\r
+#define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * @brief Controller Area Network (CAN)\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint8_t MCR; /*!< CAN master control register */\r
+ __IO uint8_t MSR; /*!< CAN master status register */\r
+ __IO uint8_t TSR; /*!< CAN transmit status register */\r
+ __IO uint8_t TPR; /*!< CAN transmit priority register */\r
+ __IO uint8_t RFR; /*!< CAN receive FIFO register */\r
+ __IO uint8_t IER; /*!< CAN interrupt enable register */\r
+ __IO uint8_t DGR; /*!< CAN diagnosis register */\r
+ __IO uint8_t PSR; /*!< CAN page selection register */\r
+\r
+ union\r
+ {\r
+ struct\r
+ {\r
+ __IO uint8_t MCSR;\r
+ __IO uint8_t MDLCR;\r
+ __IO uint8_t MIDR1;\r
+ __IO uint8_t MIDR2;\r
+ __IO uint8_t MIDR3;\r
+ __IO uint8_t MIDR4;\r
+ __IO uint8_t MDAR1;\r
+ __IO uint8_t MDAR2;\r
+ __IO uint8_t MDAR3;\r
+ __IO uint8_t MDAR4;\r
+ __IO uint8_t MDAR5;\r
+ __IO uint8_t MDAR6;\r
+ __IO uint8_t MDAR7;\r
+ __IO uint8_t MDAR8;\r
+ __IO uint8_t MTSRL;\r
+ __IO uint8_t MTSRH;\r
+ }\r
+ TxMailbox;\r
+\r
+ struct\r
+ {\r
+ __IO uint8_t FR01;\r
+ __IO uint8_t FR02;\r
+ __IO uint8_t FR03;\r
+ __IO uint8_t FR04;\r
+ __IO uint8_t FR05;\r
+ __IO uint8_t FR06;\r
+ __IO uint8_t FR07;\r
+ __IO uint8_t FR08;\r
+\r
+ __IO uint8_t FR09;\r
+ __IO uint8_t FR10;\r
+ __IO uint8_t FR11;\r
+ __IO uint8_t FR12;\r
+ __IO uint8_t FR13;\r
+ __IO uint8_t FR14;\r
+ __IO uint8_t FR15;\r
+ __IO uint8_t FR16;\r
+ }\r
+ Filter;\r
+ \r
+\r
+ struct\r
+ {\r
+ __IO uint8_t F0R1;\r
+ __IO uint8_t F0R2;\r
+ __IO uint8_t F0R3;\r
+ __IO uint8_t F0R4;\r
+ __IO uint8_t F0R5;\r
+ __IO uint8_t F0R6;\r
+ __IO uint8_t F0R7;\r
+ __IO uint8_t F0R8;\r
+\r
+ __IO uint8_t F1R1;\r
+ __IO uint8_t F1R2;\r
+ __IO uint8_t F1R3;\r
+ __IO uint8_t F1R4;\r
+ __IO uint8_t F1R5;\r
+ __IO uint8_t F1R6;\r
+ __IO uint8_t F1R7;\r
+ __IO uint8_t F1R8;\r
+ }\r
+ Filter01;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t F2R1;\r
+ __IO uint8_t F2R2;\r
+ __IO uint8_t F2R3;\r
+ __IO uint8_t F2R4;\r
+ __IO uint8_t F2R5;\r
+ __IO uint8_t F2R6;\r
+ __IO uint8_t F2R7;\r
+ __IO uint8_t F2R8;\r
+ \r
+ __IO uint8_t F3R1;\r
+ __IO uint8_t F3R2;\r
+ __IO uint8_t F3R3;\r
+ __IO uint8_t F3R4;\r
+ __IO uint8_t F3R5;\r
+ __IO uint8_t F3R6;\r
+ __IO uint8_t F3R7;\r
+ __IO uint8_t F3R8;\r
+ }\r
+ Filter23;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t F4R1;\r
+ __IO uint8_t F4R2;\r
+ __IO uint8_t F4R3;\r
+ __IO uint8_t F4R4;\r
+ __IO uint8_t F4R5;\r
+ __IO uint8_t F4R6;\r
+ __IO uint8_t F4R7;\r
+ __IO uint8_t F4R8;\r
+ \r
+ __IO uint8_t F5R1;\r
+ __IO uint8_t F5R2;\r
+ __IO uint8_t F5R3;\r
+ __IO uint8_t F5R4;\r
+ __IO uint8_t F5R5;\r
+ __IO uint8_t F5R6;\r
+ __IO uint8_t F5R7;\r
+ __IO uint8_t F5R8;\r
+ }\r
+ Filter45;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t ESR;\r
+ __IO uint8_t EIER;\r
+ __IO uint8_t TECR;\r
+ __IO uint8_t RECR;\r
+ __IO uint8_t BTR1;\r
+ __IO uint8_t BTR2;\r
+ u8 Reserved1[2];\r
+ __IO uint8_t FMR1;\r
+ __IO uint8_t FMR2;\r
+ __IO uint8_t FCR1;\r
+ __IO uint8_t FCR2;\r
+ __IO uint8_t FCR3;\r
+ u8 Reserved2[3];\r
+ }\r
+ Config;\r
+ \r
+ struct\r
+ {\r
+ __IO uint8_t MFMI;\r
+ __IO uint8_t MDLCR;\r
+ __IO uint8_t MIDR1;\r
+ __IO uint8_t MIDR2;\r
+ __IO uint8_t MIDR3;\r
+ __IO uint8_t MIDR4;\r
+ __IO uint8_t MDAR1;\r
+ __IO uint8_t MDAR2;\r
+ __IO uint8_t MDAR3;\r
+ __IO uint8_t MDAR4;\r
+ __IO uint8_t MDAR5;\r
+ __IO uint8_t MDAR6;\r
+ __IO uint8_t MDAR7;\r
+ __IO uint8_t MDAR8;\r
+ __IO uint8_t MTSRL;\r
+ __IO uint8_t MTSRH;\r
+ }\r
+ RxFIFO;\r
+ }Page; \r
+} CAN_TypeDef;\r
+/** @addtogroup CAN_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+/*******************************Common****************************************/\r
+/* CAN Master Control Register bits */\r
+#define CAN_MCR_INRQ ((uint8_t)0x01)\r
+#define CAN_MCR_SLEEP ((uint8_t)0x02)\r
+#define CAN_MCR_TXFP ((uint8_t)0x04)\r
+#define CAN_MCR_RFLM ((uint8_t)0x08)\r
+#define CAN_MCR_NART ((uint8_t)0x10)\r
+#define CAN_MCR_AWUM ((uint8_t)0x20)\r
+#define CAN_MCR_ABOM ((uint8_t)0x40)\r
+#define CAN_MCR_TTCM ((uint8_t)0x80)\r
+\r
+/* CAN Master Status Register bits */\r
+#define CAN_MSR_INAK ((uint8_t)0x01)\r
+#define CAN_MSR_SLAK ((uint8_t)0x02)\r
+#define CAN_MSR_ERRI ((uint8_t)0x04)\r
+#define CAN_MSR_WKUI ((uint8_t)0x08)\r
+#define CAN_MSR_TX ((uint8_t)0x10)\r
+#define CAN_MSR_RX ((uint8_t)0x20)\r
+\r
+/* CAN Transmit Status Register bits */\r
+#define CAN_TSR_RQCP0 ((uint8_t)0x01)\r
+#define CAN_TSR_RQCP1 ((uint8_t)0x02)\r
+#define CAN_TSR_RQCP2 ((uint8_t)0x04)\r
+#define CAN_TSR_RQCP012 ((uint8_t)0x07)\r
+#define CAN_TSR_TXOK0 ((uint8_t)0x10)\r
+#define CAN_TSR_TXOK1 ((uint8_t)0x20)\r
+#define CAN_TSR_TXOK2 ((uint8_t)0x40)\r
+\r
+#define CAN_TPR_CODE0 ((uint8_t)0x01)\r
+#define CAN_TPR_TME0 ((uint8_t)0x04)\r
+#define CAN_TPR_TME1 ((uint8_t)0x08)\r
+#define CAN_TPR_TME2 ((uint8_t)0x10)\r
+#define CAN_TPR_LOW0 ((uint8_t)0x20)\r
+#define CAN_TPR_LOW1 ((uint8_t)0x40)\r
+#define CAN_TPR_LOW2 ((uint8_t)0x80)\r
+/* CAN Receive FIFO Register bits */\r
+#define CAN_RFR_FMP01 ((uint8_t)0x03)\r
+#define CAN_RFR_FULL ((uint8_t)0x08)\r
+#define CAN_RFR_FOVR ((uint8_t)0x10)\r
+#define CAN_RFR_RFOM ((uint8_t)0x20)\r
+\r
+/* CAN Interrupt Register bits */\r
+#define CAN_IER_TMEIE ((uint8_t)0x01)\r
+#define CAN_IER_FMPIE ((uint8_t)0x02)\r
+#define CAN_IER_FFIE ((uint8_t)0x04)\r
+#define CAN_IER_FOVIE ((uint8_t)0x08)\r
+#define CAN_IER_WKUIE ((uint8_t)0x80)\r
+\r
+\r
+/* CAN diagnostic Register bits */\r
+#define CAN_DGR_LBKM ((uint8_t)0x01)\r
+#define CAN_DGR_SLIM ((uint8_t)0x02)\r
+#define CAN_DGR_SAMP ((uint8_t)0x04)\r
+#define CAN_DGR_RX ((uint8_t)0x08)\r
+#define CAN_DGR_TXM2E ((uint8_t)0x10)\r
+\r
+\r
+/* CAN page select Register bits */\r
+#define CAN_PSR_PS0 ((uint8_t)0x01)\r
+#define CAN_PSR_PS1 ((uint8_t)0x02)\r
+#define CAN_PSR_PS2 ((uint8_t)0x04)\r
+\r
+/*********************Tx MailBox & Fifo Page common bits***********************/\r
+#define CAN_MCSR_TXRQ ((uint8_t)0x01)\r
+#define CAN_MCSR_ABRQ ((uint8_t)0x02)\r
+#define CAN_MCSR_RQCP ((uint8_t)0x04)\r
+#define CAN_MCSR_TXOK ((uint8_t)0x08)\r
+#define CAN_MCSR_ALST ((uint8_t)0x10)\r
+#define CAN_MCSR_TERR ((uint8_t)0x20)\r
+\r
+#define CAN_MDLCR_DLC ((uint8_t)0x0F)\r
+#define CAN_MDLCR_TGT ((uint8_t)0x80)\r
+\r
+#define CAN_MIDR1_RTR ((uint8_t)0x20)\r
+#define CAN_MIDR1_IDE ((uint8_t)0x40)\r
+\r
+\r
+/*************************Filter Page******************************************/\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_ESR_EWGF ((uint8_t)0x01)\r
+#define CAN_ESR_EPVF ((uint8_t)0x02)\r
+#define CAN_ESR_BOFF ((uint8_t)0x04)\r
+#define CAN_ESR_LEC0 ((uint8_t)0x10)\r
+#define CAN_ESR_LEC1 ((uint8_t)0x20)\r
+#define CAN_ESR_LEC2 ((uint8_t)0x40)\r
+#define CAN_ESR_LEC ((uint8_t)0x70)\r
+\r
+/* CAN Error Status Register bits */\r
+#define CAN_EIER_EWGIE ((uint8_t)0x01)\r
+#define CAN_EIER_EPVIE ((uint8_t)0x02)\r
+#define CAN_EIER_BOFIE ((uint8_t)0x04)\r
+#define CAN_EIER_LECIE ((uint8_t)0x10)\r
+#define CAN_EIER_ERRIE ((uint8_t)0x80) \r
+\r
+/* CAN transmit error counter Register bits(CAN_TECR) */\r
+#define CAN_TECR_TEC0 ((uint8_t)0x01) \r
+#define CAN_TECR_TEC1 ((uint8_t)0x02) \r
+#define CAN_TECR_TEC2 ((uint8_t)0x04) \r
+#define CAN_TECR_TEC3 ((uint8_t)0x08) \r
+#define CAN_TECR_TEC4 ((uint8_t)0x10) \r
+#define CAN_TECR_TEC5 ((uint8_t)0x20) \r
+#define CAN_TECR_TEC6 ((uint8_t)0x40) \r
+#define CAN_TECR_TEC7 ((uint8_t)0x80) \r
+\r
+/* CAN RECEIVE error counter Register bits(CAN_TECR) */\r
+#define CAN_RECR_REC0 ((uint8_t)0x01) \r
+#define CAN_RECR_REC1 ((uint8_t)0x02) \r
+#define CAN_RECR_REC2 ((uint8_t)0x04) \r
+#define CAN_RECR_REC3 ((uint8_t)0x08) \r
+#define CAN_RECR_REC4 ((uint8_t)0x10) \r
+#define CAN_RECR_REC5 ((uint8_t)0x20) \r
+#define CAN_RECR_REC6 ((uint8_t)0x40) \r
+#define CAN_RECR_REC7 ((uint8_t)0x80) \r
+\r
+/* CAN filter mode register bits (CAN_FMR) */\r
+#define CAN_FMR1_FML0 ((uint8_t)0x01) \r
+#define CAN_FMR1_FMH0 ((uint8_t)0x02) \r
+#define CAN_FMR1_FML1 ((uint8_t)0x04) \r
+#define CAN_FMR1_FMH1 ((uint8_t)0x08) \r
+#define CAN_FMR1_FML2 ((uint8_t)0x10) \r
+#define CAN_FMR1_FMH2 ((uint8_t)0x20) \r
+#define CAN_FMR1_FML3 ((uint8_t)0x40) \r
+#define CAN_FMR1_FMH3 ((uint8_t)0x80) \r
+\r
+#define CAN_FMR2_FML4 ((uint8_t)0x01) \r
+#define CAN_FMR2_FMH4 ((uint8_t)0x02) \r
+#define CAN_FMR2_FML5 ((uint8_t)0x04) \r
+#define CAN_FMR2_FMH5 ((uint8_t)0x08) \r
+\r
+/* CAN filter Config register bits (CAN_FCR) */\r
+#define CAN_FCR1_FACT0 ((uint8_t)0x01) \r
+#define CAN_FCR1_FACT1 ((uint8_t)0x10) \r
+#define CAN_FCR2_FACT2 ((uint8_t)0x01) \r
+#define CAN_FCR2_FACT3 ((uint8_t)0x10) \r
+#define CAN_FCR3_FACT4 ((uint8_t)0x01) \r
+#define CAN_FCR3_FACT5 ((uint8_t)0x10) \r
+\r
+#define CAN_FCR1_FSC00 ((uint8_t)0x02) \r
+#define CAN_FCR1_FSC01 ((uint8_t)0x04) \r
+#define CAN_FCR1_FSC10 ((uint8_t)0x20) \r
+#define CAN_FCR1_FSC11 ((uint8_t)0x40) \r
+#define CAN_FCR2_FSC20 ((uint8_t)0x02) \r
+#define CAN_FCR2_FSC21 ((uint8_t)0x04) \r
+#define CAN_FCR2_FSC30 ((uint8_t)0x20) \r
+#define CAN_FCR2_FSC31 ((uint8_t)0x40) \r
+#define CAN_FCR3_FSC40 ((uint8_t)0x02) \r
+#define CAN_FCR3_FSC41 ((uint8_t)0x04) \r
+#define CAN_FCR3_FSC50 ((uint8_t)0x20) \r
+#define CAN_FCR3_FSC51 ((uint8_t)0x40)\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CAN_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CAN_MCR_RESET_VALUE ((uint8_t)0x02)\r
+#define CAN_MSR_RESET_VALUE ((uint8_t)0x02)\r
+#define CAN_TSR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)\r
+#define CAN_RFR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_IER_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)\r
+#define CAN_PSR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+#define CAN_ESR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_EIER_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_TECR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_RECR_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)\r
+#define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)\r
+#define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_FCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+#define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)\r
+#define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration Registers (CFG)\r
+ */\r
+\r
+typedef struct CFG_struct\r
+{\r
+ __IO uint8_t GCR; /*!< Global Configuration register */\r
+}\r
+CFG_TypeDef;\r
+\r
+/** @addtogroup CFG_Registers_Reset_Value\r
+ * @{\r
+ */\r
+\r
+#define CFG_GCR_RESET_VALUE ((uint8_t)0x00)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup CFG_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */\r
+#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripherals Base Address */\r
+/******************************************************************************/\r
+\r
+/** @addtogroup MAP_FILE_Base_Addresses\r
+ * @{\r
+ */\r
+#define OPT_BaseAddress 0x4800\r
+#define GPIOA_BaseAddress 0x5000\r
+#define GPIOB_BaseAddress 0x5005\r
+#define GPIOC_BaseAddress 0x500A\r
+#define GPIOD_BaseAddress 0x500F\r
+#define GPIOE_BaseAddress 0x5014\r
+#define GPIOF_BaseAddress 0x5019\r
+#define GPIOG_BaseAddress 0x501E\r
+#define GPIOH_BaseAddress 0x5023\r
+#define GPIOI_BaseAddress 0x5028\r
+#define FLASH_BaseAddress 0x505A\r
+#define EXTI_BaseAddress 0x50A0\r
+#define RST_BaseAddress 0x50B3\r
+#define CLK_BaseAddress 0x50C0\r
+#define WWDG_BaseAddress 0x50D1\r
+#define IWDG_BaseAddress 0x50E0\r
+#define AWU_BaseAddress 0x50F0\r
+#define BEEP_BaseAddress 0x50F3\r
+#define SPI_BaseAddress 0x5200\r
+#define I2C_BaseAddress 0x5210\r
+#define UART1_BaseAddress 0x5230\r
+#define UART2_BaseAddress 0x5240\r
+#define UART3_BaseAddress 0x5240\r
+#define TIM1_BaseAddress 0x5250\r
+#define TIM2_BaseAddress 0x5300\r
+#define TIM3_BaseAddress 0x5320\r
+#define TIM4_BaseAddress 0x5340\r
+#define TIM5_BaseAddress 0x5300\r
+#define TIM6_BaseAddress 0x5340\r
+#define ADC1_BaseAddress 0x53E0\r
+#define ADC2_BaseAddress 0x5400\r
+#define CAN_BaseAddress 0x5420\r
+#define CFG_BaseAddress 0x7F60\r
+#define ITC_BaseAddress 0x7F70\r
+#define DM_BaseAddress 0x7F90\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripherals declarations */\r
+/******************************************************************************/\r
+\r
+#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \\r
+ defined(STM8S903) || defined(STM8AF626x)\r
+ #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)\r
+#endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) */\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+#define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */\r
+\r
+#define AWU ((AWU_TypeDef *) AWU_BaseAddress)\r
+\r
+#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)\r
+\r
+#if defined (STM8S208) || defined (STM8AF52Ax)\r
+ #define CAN ((CAN_TypeDef *) CAN_BaseAddress)\r
+#endif /* (STM8S208) || (STM8AF52Ax) */\r
+\r
+#define CLK ((CLK_TypeDef *) CLK_BaseAddress)\r
+\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)\r
+\r
+#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)\r
+\r
+#define OPT ((OPT_TypeDef *) OPT_BaseAddress)\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)\r
+\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)\r
+\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)\r
+\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)\r
+\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)\r
+\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)\r
+\r
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */\r
+\r
+#if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)\r
+ #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+\r
+#define RST ((RST_TypeDef *) RST_BaseAddress)\r
+\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)\r
+\r
+#define SPI ((SPI_TypeDef *) SPI_BaseAddress)\r
+#define I2C ((I2C_TypeDef *) I2C_BaseAddress)\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)\r
+ #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */\r
+\r
+#if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)\r
+ #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)\r
+#endif /* STM8S105 || STM8S005 || STM8AF626x */\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax)\r
+ #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */\r
+\r
+#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/\r
+\r
+#if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \\r
+ defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/\r
+\r
+#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \\r
+ defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \\r
+ defined (STM8AF62Ax) || defined (STM8AF626x)\r
+ #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)\r
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/\r
+\r
+#ifdef STM8S903\r
+ #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)\r
+ #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)\r
+#endif /* STM8S903 */ \r
+\r
+#define ITC ((ITC_TypeDef *) ITC_BaseAddress)\r
+\r
+#define CFG ((CFG_TypeDef *) CFG_BaseAddress)\r
+\r
+#define DM ((DM_TypeDef *) DM_BaseAddress)\r
+\r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm8s_conf.h"\r
+#endif\r
+\r
+/* Exported macro --------------------------------------------------------------*/\r
+\r
+/*============================== Interrupts ====================================*/\r
+#ifdef _RAISONANCE_\r
+ #include <intrins.h>\r
+ #define enableInterrupts() _rim_() /* enable interrupts */\r
+ #define disableInterrupts() _sim_() /* disable interrupts */\r
+ #define rim() _rim_() /* enable interrupts */\r
+ #define sim() _sim_() /* disable interrupts */\r
+ #define nop() _nop_() /* No Operation */\r
+ #define trap() _trap_() /* Trap (soft IT) */\r
+ #define wfi() _wfi_() /* Wait For Interrupt */\r
+ #define halt() _halt_() /* Halt */\r
+#elif defined(_COSMIC_)\r
+ #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */\r
+ #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */\r
+ #define rim() {_asm("rim\n");} /* enable interrupts */\r
+ #define sim() {_asm("sim\n");} /* disable interrupts */\r
+ #define nop() {_asm("nop\n");} /* No Operation */\r
+ #define trap() {_asm("trap\n");} /* Trap (soft IT) */\r
+ #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */\r
+ #define halt() {_asm("halt\n");} /* Halt */\r
+#else /*_IAR_*/\r
+ #include <intrinsics.h>\r
+ #define enableInterrupts() __enable_interrupt() /* enable interrupts */\r
+ #define disableInterrupts() __disable_interrupt() /* disable interrupts */\r
+ #define rim() __enable_interrupt() /* enable interrupts */\r
+ #define sim() __disable_interrupt() /* disable interrupts */\r
+ #define nop() __no_operation() /* No Operation */\r
+ #define trap() __trap() /* Trap (soft IT) */\r
+ #define wfi() __wait_for_interrupt() /* Wait For Interrupt */\r
+ #define halt() __halt() /* Halt */\r
+#endif /*_RAISONANCE_*/\r
+\r
+/*============================== Interrupt vector Handling ========================*/\r
+\r
+#ifdef _COSMIC_\r
+ #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)\r
+ #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)\r
+#endif /* _COSMIC_ */\r
+\r
+#ifdef _RAISONANCE_\r
+ #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b\r
+ #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap\r
+#endif /* _RAISONANCE_ */\r
+\r
+#ifdef _IAR_\r
+ #define STRINGVECTOR(x) #x\r
+ #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )\r
+ #define INTERRUPT_HANDLER( a, b ) \\r
+ _Pragma( VECTOR_ID( (b)+2 ) ) \\r
+ __interrupt void (a)( void )\r
+ #define INTERRUPT_HANDLER_TRAP(a) \\r
+ _Pragma( VECTOR_ID( 1 ) ) \\r
+ __interrupt void (a) (void) \r
+#endif /* _IAR_ */\r
+\r
+/*============================== Interrupt Handler declaration ========================*/\r
+#ifdef _COSMIC_\r
+ #define INTERRUPT @far @interrupt\r
+#elif defined(_IAR_)\r
+ #define INTERRUPT __interrupt\r
+#endif /* _COSMIC_ */\r
+\r
+/*============================== Handling bits ====================================*/\r
+/*-----------------------------------------------------------------------------\r
+Method : I\r
+Description : Handle the bit from the character variables.\r
+Comments : The different parameters of commands are\r
+ - VAR : Name of the character variable where the bit is located.\r
+ - Place : Bit position in the variable (7 6 5 4 3 2 1 0)\r
+ - Value : Can be 0 (reset bit) or not 0 (set bit)\r
+ The "MskBit" command allows to select some bits in a source\r
+ variables and copy it in a destination var (return the value).\r
+ The "ValBit" command returns the value of a bit in a char\r
+ variable: the bit is reset if it returns 0 else the bit is set.\r
+ This method generates not an optimised code yet.\r
+-----------------------------------------------------------------------------*/\r
+#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )\r
+#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )\r
+\r
+#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )\r
+#define AffBit(VAR,Place,Value) ((Value) ? \\r
+ ((VAR) |= ((uint8_t)1<<(Place))) : \\r
+ ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))\r
+#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )\r
+\r
+#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))\r
+\r
+#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */\r
+#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */\r
+#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */\r
+#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */\r
+\r
+/*============================== Assert Macros ====================================*/\r
+#define IS_STATE_VALUE_OK(SensitivityValue) \\r
+ (((SensitivityValue) == ENABLE) || \\r
+ ((SensitivityValue) == DISABLE))\r
+\r
+/*-----------------------------------------------------------------------------\r
+Method : II\r
+Description : Handle directly the bit.\r
+Comments : The idea is to handle directly with the bit name. For that, it is\r
+ necessary to have RAM area descriptions (example: HW register...)\r
+ and the following command line for each area.\r
+ This method generates the most optimized code.\r
+-----------------------------------------------------------------------------*/\r
+\r
+#define AREA 0x00 /* The area of bits begins at address 0x10. */\r
+\r
+#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )\r
+#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )\r
+#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )\r
+\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+#endif /* __STM8S_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r
projects / stm8dev.git / commitdiff