+/**\r
+ ******************************************************************************\r
+ * @file stm32f4_discovery_lis302dl.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 28-October-2011\r
+ * @brief This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c\r
+ * firmware driver.\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F4_DISCOVERY_LIS302DL_H\r
+#define __STM32F4_DISCOVERY_LIS302DL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+ #include "stm32f4xx.h"\r
+\r
+/** @addtogroup Utilities\r
+ * @{\r
+ */\r
+ \r
+/** @addtogroup STM32F4_DISCOVERY\r
+ * @{\r
+ */ \r
+\r
+/** @addtogroup STM32F4_DISCOVERY_LIS302DL\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Types\r
+ * @{\r
+ */\r
+ \r
+/* LIS302DL struct */\r
+typedef struct\r
+{\r
+ uint8_t Power_Mode; /* Power-down/Active Mode */\r
+ uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */\r
+ uint8_t Axes_Enable; /* Axes enable */\r
+ uint8_t Full_Scale; /* Full scale */\r
+ uint8_t Self_Test; /* Self test */\r
+}LIS302DL_InitTypeDef;\r
+\r
+/* LIS302DL High Pass Filter struct */\r
+typedef struct\r
+{\r
+ uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/\r
+ uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */\r
+ uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */ \r
+}LIS302DL_FilterConfigTypeDef; \r
+\r
+/* LIS302DL Interrupt struct */\r
+typedef struct\r
+{\r
+ uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/\r
+ uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */\r
+ uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */ \r
+}LIS302DL_InterruptConfigTypeDef; \r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback() \r
+ function implemented in stm32f4_discovery_lis302dl.c file.\r
+ LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition \r
+ occure during communication (waiting transmit data register empty flag(TXE)\r
+ or waiting receive data register is not empty flag (RXNE)). */ \r
+#define USE_DEFAULT_TIMEOUT_CALLBACK\r
+\r
+/* Maximum Timeout values for flags waiting loops. These timeouts are not based\r
+ on accurate values, they just guarantee that the application will not remain\r
+ stuck if the SPI communication is corrupted.\r
+ You may modify these timeout values depending on CPU frequency and application\r
+ conditions (interrupts routines ...). */ \r
+#define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000)\r
+\r
+/**\r
+ * @brief LIS302DL SPI Interface pins\r
+ */\r
+#define LIS302DL_SPI SPI1\r
+#define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1\r
+\r
+#define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */\r
+#define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */\r
+#define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA\r
+#define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5\r
+#define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1\r
+\r
+#define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */\r
+#define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */\r
+#define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA\r
+#define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6\r
+#define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1\r
+\r
+#define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */\r
+#define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */\r
+#define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA\r
+#define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7\r
+#define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1\r
+\r
+#define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */\r
+#define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */\r
+#define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE\r
+\r
+#define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */\r
+#define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */\r
+#define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE\r
+#define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0\r
+#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE\r
+#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0\r
+#define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn \r
+\r
+#define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */\r
+#define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */\r
+#define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE\r
+#define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1\r
+#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE\r
+#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1\r
+#define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn \r
+\r
+\r
+/******************************************************************************/\r
+/*************************** START REGISTER MAPPING **************************/\r
+/******************************************************************************/\r
+\r
+/*******************************************************************************\r
+* WHO_AM_I Register: Device Identification Register\r
+* Read only register\r
+* Default value: 0x3B\r
+*******************************************************************************/\r
+#define LIS302DL_WHO_AM_I_ADDR 0x0F\r
+\r
+/*******************************************************************************\r
+* CTRL_REG1 Register: Control Register 1\r
+* Read Write register\r
+* Default value: 0x07\r
+* 7 DR: Data Rate selection.\r
+* 0 - 100 Hz output data rate\r
+* 1 - 400 Hz output data rate\r
+* 6 PD: Power Down control.\r
+* 0 - power down mode\r
+* 1 - active mode\r
+* 5 FS: Full Scale selection.\r
+* 0 - Typical measurement range 2.3\r
+* 1 - Typical measurement range 9.2\r
+* 4:3 STP-STM Self Test Enable:\r
+* STP | STM | mode\r
+* ----------------------------\r
+* 0 | 0 | Normal mode\r
+* 0 | 1 | Self Test M\r
+* 1 | 0 | Self Test P\r
+* 2 Zen: Z axis enable.\r
+* 0 - Z axis disabled\r
+* 1- Z axis enabled\r
+* 1 Yen: Y axis enable.\r
+* 0 - Y axis disabled\r
+* 1- Y axis enabled\r
+* 0 Xen: X axis enable.\r
+* 0 - X axis disabled\r
+* 1- X axis enabled\r
+********************************************************************************/\r
+#define LIS302DL_CTRL_REG1_ADDR 0x20\r
+\r
+/*******************************************************************************\r
+* CTRL_REG2 Regsiter: Control Register 2\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7 SIM: SPI Serial Interface Mode Selection. \r
+* 0 - 4 wire interface\r
+* 1 - 3 wire interface\r
+* 6 BOOT: Reboot memory content\r
+* 0 - normal mode \r
+* 1 - reboot memory content\r
+* 5 Reserved\r
+* 4 FDS: Filtered data selection.\r
+* 0 - internal filter bypassed\r
+* 1 - data from internal filter sent to output register\r
+* 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2.\r
+* 0 - filter bypassed\r
+* 1 - filter enabled\r
+* 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1.\r
+* 0 - filter bypassed\r
+* 1 - filter enabled\r
+* 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration.\r
+* ft= ODR[hz]/6*HP coeff\r
+* HP coeff2 | HP coeff1 | HP coeff\r
+* -------------------------------------------\r
+* 0 | 0 | 8\r
+* 0 | 1 | 16\r
+* 1 | 0 | 32\r
+* 1 | 1 | 64\r
+* HP coeff | ft[hz] | ft[hz] |\r
+* |ODR 100Hz | ODR 400Hz |\r
+* --------------------------------------------\r
+* 00 | 2 | 8 |\r
+* 01 | 1 | 4 |\r
+* 10 | 0.5 | 2 |\r
+* 11 | 0.25 | 1 |\r
+*******************************************************************************/\r
+#define LIS302DL_CTRL_REG2_ADDR 0x21\r
+\r
+/*******************************************************************************\r
+* CTRL_REG3 Register: Interrupt Control Register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7 IHL active: Interrupt active high/low.\r
+* 0 - active high\r
+* 1 - active low\r
+* 6 PP_OD: push-pull/open-drain.\r
+* 0 - push-pull\r
+* 1 - open-drain\r
+* 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits\r
+* 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits\r
+* I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad\r
+* ----------------------------------------------------------\r
+* 0 | 0 | 0 | GND\r
+* 0 | 0 | 1 | FreeFall/WakeUp#1\r
+* 0 | 1 | 0 | FreeFall/WakeUp#2\r
+* 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2\r
+* 1 | 0 | 0 | Data ready\r
+* 1 | 1 | 1 | Click interrupt\r
+*******************************************************************************/\r
+#define LIS302DL_CTRL_REG3_ADDR 0x22\r
+\r
+/*******************************************************************************\r
+* HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes \r
+* instantaneously the content of the internal high pass filter. If the high pass\r
+* filter is enabled all three axes are instantaneously set to 0g.\r
+* This allows to overcome the settling time of the high pass filter.\r
+* Read only register\r
+* Default value: Dummy\r
+*******************************************************************************/\r
+#define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23\r
+\r
+/*******************************************************************************\r
+* STATUS_REG Register: Status Register\r
+* Default value: 0x00\r
+* 7 ZYXOR: X, Y and Z axis data overrun.\r
+* 0: no overrun has occurred\r
+* 1: new data has overwritten the previous one before it was read\r
+* 6 ZOR: Z axis data overrun.\r
+* 0: no overrun has occurred \r
+* 1: new data for Z-axis has overwritten the previous one before it was read\r
+* 5 yOR: y axis data overrun.\r
+* 0: no overrun has occurred\r
+* 1: new data for y-axis has overwritten the previous one before it was read\r
+* 4 XOR: X axis data overrun.\r
+* 0: no overrun has occurred\r
+* 1: new data for X-axis has overwritten the previous one before it was read\r
+* 3 ZYXDA: X, Y and Z axis new data available\r
+* 0: a new set of data is not yet available\r
+* 1: a new set of data is available\r
+* 2 ZDA: Z axis new data available.\r
+* 0: a new set of data is not yet available\r
+* 1: a new data for Z axis is available\r
+* 1 YDA: Y axis new data available\r
+* 0: a new set of data is not yet available\r
+* 1: a new data for Y axis is available\r
+* 0 XDA: X axis new data available\r
+* 0: a new set of data is not yet available\r
+* 1: a new data for X axis is available\r
+*******************************************************************************/\r
+#define LIS302DL_STATUS_REG_ADDR 0x27\r
+\r
+/*******************************************************************************\r
+* OUT_X Register: X-axis output Data\r
+* Read only register\r
+* Default value: output\r
+* 7:0 XD7-XD0: X-axis output Data\r
+*******************************************************************************/\r
+#define LIS302DL_OUT_X_ADDR 0x29\r
+\r
+/*******************************************************************************\r
+* OUT_Y Register: Y-axis output Data\r
+* Read only register\r
+* Default value: output\r
+* 7:0 YD7-YD0: Y-axis output Data\r
+*******************************************************************************/\r
+#define LIS302DL_OUT_Y_ADDR 0x2B\r
+\r
+/*******************************************************************************\r
+* OUT_Z Register: Z-axis output Data\r
+* Read only register\r
+* Default value: output\r
+* 7:0 ZD7-ZD0: Z-axis output Data\r
+*******************************************************************************/\r
+#define LIS302DL_OUT_Z_ADDR 0x2D\r
+\r
+/*******************************************************************************\r
+* FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source.\r
+* Read write register\r
+* Default value: 0x00\r
+* 7 AOI: AND/OR combination of Interrupt events. \r
+* 0: OR combination of interrupt events\r
+* 1: AND combination of interrupt events \r
+* 6 LIR: Latch/not latch interrupt request\r
+* 0: interrupt request not latched\r
+* 1: interrupt request latched\r
+* 5 ZHIE: Enable interrupt generation on Z high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 4 ZLIE: Enable interrupt generation on Z low event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+* 3 YHIE: Enable interrupt generation on Y high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 2 YLIE: Enable interrupt generation on Y low event. \r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+* 1 XHIE: Enable interrupt generation on X high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 0 XLIE: Enable interrupt generation on X low event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30\r
+\r
+/*******************************************************************************\r
+* FF_WU_SRC_1 Register: Interrupt 1 source register.\r
+* Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt\r
+* and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option\r
+* was chosen.\r
+* Read only register\r
+* Default value: 0x00\r
+* 7 Reserved\r
+* 6 IA: Interrupt active.\r
+* 0: no interrupt has been generated\r
+* 1: one or more interrupts have been generated\r
+* 5 ZH: Z high. \r
+* 0: no interrupt\r
+* 1: ZH event has occurred \r
+* 4 ZL: Z low.\r
+* 0: no interrupt\r
+* 1: ZL event has occurred\r
+* 3 YH: Y high.\r
+* 0: no interrupt\r
+* 1: YH event has occurred \r
+* 2 YL: Y low.\r
+* 0: no interrupt\r
+* 1: YL event has occurred\r
+* 1 YH: X high.\r
+* 0: no interrupt\r
+* 1: XH event has occurred \r
+* 0 YL: X low.\r
+* 0: no interrupt\r
+* 1: XL event has occurred\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31\r
+\r
+/*******************************************************************************\r
+* FF_WU_THS_1 Register: Threshold register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7 DCRM: Reset mode selection.\r
+* 0 - counter resetted\r
+* 1 - counter decremented\r
+* 6 THS6-THS0: Free-fall/wake-up threshold value.\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_THS1_REG_ADDR 0x32\r
+\r
+/*******************************************************************************\r
+* FF_WU_DURATION_1 Register: duration Register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)\r
+ ******************************************************************************/\r
+#define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33\r
+\r
+/*******************************************************************************\r
+* FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source.\r
+* Read write register\r
+* Default value: 0x00\r
+* 7 AOI: AND/OR combination of Interrupt events. \r
+* 0: OR combination of interrupt events\r
+* 1: AND combination of interrupt events \r
+* 6 LIR: Latch/not latch interrupt request\r
+* 0: interrupt request not latched\r
+* 1: interrupt request latched\r
+* 5 ZHIE: Enable interrupt generation on Z high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 4 ZLIE: Enable interrupt generation on Z low event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+* 3 YHIE: Enable interrupt generation on Y high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 2 YLIE: Enable interrupt generation on Y low event. \r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+* 1 XHIE: Enable interrupt generation on X high event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value higher than preset threshold\r
+* 0 XLIE: Enable interrupt generation on X low event.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request on measured accel. value lower than preset threshold\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34\r
+\r
+/*******************************************************************************\r
+* FF_WU_SRC_2 Register: Interrupt 2 source register.\r
+* Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt\r
+* and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option\r
+* was chosen.\r
+* Read only register\r
+* Default value: 0x00\r
+* 7 Reserved\r
+* 6 IA: Interrupt active.\r
+* 0: no interrupt has been generated\r
+* 1: one or more interrupts have been generated\r
+* 5 ZH: Z high. \r
+* 0: no interrupt\r
+* 1: ZH event has occurred \r
+* 4 ZL: Z low.\r
+* 0: no interrupt\r
+* 1: ZL event has occurred\r
+* 3 YH: Y high.\r
+* 0: no interrupt\r
+* 1: YH event has occurred \r
+* 2 YL: Y low.\r
+* 0: no interrupt\r
+* 1: YL event has occurred\r
+* 1 YH: X high.\r
+* 0: no interrupt\r
+* 1: XH event has occurred \r
+* 0 YL: X low.\r
+* 0: no interrupt\r
+* 1: XL event has occurred\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35\r
+\r
+/*******************************************************************************\r
+* FF_WU_THS_2 Register: Threshold register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7 DCRM: Reset mode selection.\r
+* 0 - counter resetted\r
+* 1 - counter decremented\r
+* 6 THS6-THS0: Free-fall/wake-up threshold value.\r
+*******************************************************************************/\r
+#define LIS302DL_FF_WU_THS2_REG_ADDR 0x36\r
+\r
+/*******************************************************************************\r
+* FF_WU_DURATION_2 Register: duration Register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)\r
+ ******************************************************************************/\r
+#define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37\r
+\r
+/******************************************************************************\r
+* CLICK_CFG Register: click Register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7 Reserved\r
+* 6 LIR: Latch Interrupt request.\r
+* 0: interrupt request not latched\r
+* 1: interrupt request latched\r
+* 5 Double_Z: Enable interrupt generation on double click event on Z axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+* 4 Single_Z: Enable interrupt generation on single click event on Z axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+* 3 Double_Y: Enable interrupt generation on double click event on Y axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+* 2 Single_Y: Enable interrupt generation on single click event on Y axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+* 1 Double_X: Enable interrupt generation on double click event on X axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+* 0 Single_y: Enable interrupt generation on single click event on X axis.\r
+* 0: disable interrupt request\r
+* 1: enable interrupt request\r
+ ******************************************************************************/\r
+#define LIS302DL_CLICK_CFG_REG_ADDR 0x38\r
+\r
+/******************************************************************************\r
+* CLICK_SRC Register: click status Register\r
+* Read only register\r
+* Default value: 0x00\r
+* 7 Reserved\r
+* 6 IA: Interrupt active.\r
+* 0: no interrupt has been generated\r
+* 1: one or more interrupts have been generated\r
+* 5 Double_Z: Double click on Z axis event.\r
+* 0: no interrupt\r
+* 1: Double Z event has occurred \r
+* 4 Single_Z: Z low.\r
+* 0: no interrupt\r
+* 1: Single Z event has occurred \r
+* 3 Double_Y: Y high.\r
+* 0: no interrupt\r
+* 1: Double Y event has occurred \r
+* 2 Single_Y: Y low.\r
+* 0: no interrupt\r
+* 1: Single Y event has occurred \r
+* 1 Double_X: X high.\r
+* 0: no interrupt\r
+* 1: Double X event has occurred \r
+* 0 Single_X: X low.\r
+* 0: no interrupt\r
+* 1: Single X event has occurred \r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_SRC_REG_ADDR 0x39\r
+\r
+/*******************************************************************************\r
+* CLICK_THSY_X Register: Click threshold Y and X register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g\r
+* 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g\r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B\r
+\r
+/*******************************************************************************\r
+* CLICK_THSZ Register: Click threshold Z register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:4 Reserved\r
+* 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g\r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C\r
+\r
+/*******************************************************************************\r
+* CLICK_TimeLimit Register: Time Limit register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:0 Dur7-Dur0: Time Limit value, step 0.5g\r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D\r
+\r
+/*******************************************************************************\r
+* CLICK_Latency Register: Latency register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:0 Lat7-Lat0: Latency value, step 1msec\r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E\r
+\r
+/*******************************************************************************\r
+* CLICK_Window Register: Window register\r
+* Read Write register\r
+* Default value: 0x00\r
+* 7:0 Win7-Win0: Window value, step 1msec\r
+*******************************************************************************/\r
+#define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F\r
+\r
+/******************************************************************************/\r
+/**************************** END REGISTER MAPPING ***************************/\r
+/******************************************************************************/\r
+\r
+#define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/\r
+#define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/\r
+\r
+/** @defgroup Data_Rate_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_DATARATE_100 ((uint8_t)0x00)\r
+#define LIS302DL_DATARATE_400 ((uint8_t)0x80)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Power_Mode_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00)\r
+#define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Full_Scale_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00)\r
+#define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup Self_Test_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00)\r
+#define LIS302DL_SELFTEST_P ((uint8_t)0x10)\r
+#define LIS302DL_SELFTEST_M ((uint8_t)0x08)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Direction_XYZ_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_X_ENABLE ((uint8_t)0x01)\r
+#define LIS302DL_Y_ENABLE ((uint8_t)0x02)\r
+#define LIS302DL_Z_ENABLE ((uint8_t)0x04)\r
+#define LIS302DL_XYZ_ENABLE ((uint8_t)0x07)\r
+/**\r
+ * @}\r
+ */\r
+ \r
+ /** @defgroup SPI_Serial_Interface_Mode_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00)\r
+#define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup Boot_Mode_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00)\r
+#define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+ /** @defgroup Filtered_Data_Selection_Mode_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00)\r
+#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /** @defgroup High_Pass_Filter_Interrupt_selection \r
+ * @{\r
+ */ \r
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00)\r
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04)\r
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08)\r
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C)\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+ /** @defgroup High_Pass_Filter_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00)\r
+#define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01)\r
+#define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02)\r
+#define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03)\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup latch_Interrupt_Request_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00)\r
+#define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Click_Interrupt_XYZ_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)\r
+#define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01)\r
+#define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04)\r
+#define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10)\r
+#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Double_Click_Interrupt_XYZ_selection \r
+ * @{\r
+ */\r
+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)\r
+#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02)\r
+#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08)\r
+#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20)\r
+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A)\r
+/**\r
+ * @}\r
+ */\r
+/**\r
+ * @}\r
+ */ \r
+ \r
+/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Macros\r
+ * @{\r
+ */\r
+#define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)\r
+#define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Functions\r
+ * @{\r
+ */ \r
+void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct);\r
+void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct);\r
+void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct);\r
+void LIS302DL_LowpowerCmd(uint8_t LowPowerMode);\r
+void LIS302DL_FullScaleCmd(uint8_t FS_value);\r
+void LIS302DL_DataRateCmd(uint8_t DataRateValue);\r
+void LIS302DL_RebootCmd(void);\r
+void LIS302DL_ReadACC(int32_t* out);\r
+void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);\r
+void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);\r
+\r
+/* USER Callbacks: This is function for which prototype only is declared in\r
+ MEMS accelerometre driver and that should be implemented into user applicaiton. */ \r
+/* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition \r
+ occure during communication (waiting transmit data register empty flag(TXE)\r
+ or waiting receive data register is not empty flag (RXNE)).\r
+ You can use the default timeout callback implementation by uncommenting the \r
+ define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file.\r
+ Typically the user implementation of this callback should reset MEMS peripheral\r
+ and re-initialize communication or in worst case reset all the application. */\r
+uint32_t LIS302DL_TIMEOUT_UserCallback(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F4_DISCOVERY_LIS302DL_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r