spring working \o/

diff --git a/fpga/Cmod-A7-Master.xdc b/fpga/Cmod-A7-Master.xdc
index 120c1a41173d751b23f67ec469fb8b7b8ae5638d..d114f15dde8e9f75343fe003559feb0e277a0bf5 100644 (file)
--- a/fpga/Cmod-A7-Master.xdc
+++ b/fpga/Cmod-A7-Master.xdc
@@ -21,8 +21,8 @@ set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { overfl
 #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
 
 ## Pmod Header JA
 #set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
 
 ## Pmod Header JA

-set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { dir }]; #IO_L5N_T0_D07_14 Sch=ja[1]
-set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { en }]; #IO_L4N_T0_D05_14 Sch=ja[2]
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33  INIT 0 } [get_ports { dir }]; #IO_L5N_T0_D07_14 Sch=ja[1]
+set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33  INIT 0 } [get_ports { en }]; #IO_L4N_T0_D05_14 Sch=ja[2]

 #set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
 #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
 #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
 #set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
 #set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
 #set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]


@@ -32,8 +32,8 @@ set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { en }];
 
 ## Analog XADC Pins
 ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
 
 ## Analog XADC Pins
 ## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12

-set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
-set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
+set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33  INIT 0 } [get_ports { xa_n }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
+set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33  INIT 0 } [get_ports { xa_p }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]

 #set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
 #set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
 
 #set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
 #set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
 

diff --git a/fpga/forcefader.srcs/sim_1/new/testbench.v b/fpga/forcefader.srcs/sim_1/new/testbench.v
index 96b918a859b60b6f92b221305548c0e6906b5be3..35c66d21f4ec174d416adbe45b59e877006d50b0 100644 (file)
--- a/fpga/forcefader.srcs/sim_1/new/testbench.v
+++ b/fpga/forcefader.srcs/sim_1/new/testbench.v
@@ -61,13 +61,47 @@ module testbench(
     initial begin
       //init
       sysclk = 0;
     initial begin
       //init
       sysclk = 0;

-      stiffness = 8'h3;
-      endposition = 10'b0111111111;
+      stiffness = 0;
+      endposition = 0;

       input_pos = 0;
       
       //wait
       #100;
       
       input_pos = 0;
       
       //wait
       #100;
       

+      //test enable
+      
+      stiffness = 8'hff;
+      input_pos = 0;
+
+      input_pos = 0;
+      endposition = 10'b0111111111;
+      #10000000;
+      
+      input_pos = 10'h3ff;
+      #10000000;
+
+      input_pos = 0;
+      #10000000;
+            
+      input_pos = 10'h3ff;
+      #10000000;
+  
+      input_pos = 0;
+      #10000000;
+      
+      input_pos = 10'h3ff;
+      #10000000;
+
+
+      //wait
+      #100000000;
+
+      //test force rendering
+
+      stiffness = 8'h3;
+      endposition = 10'b0111111111;
+      input_pos = 0;
+      

       //test
       input_pos = 10'h010;
       #10000000;
       //test
       input_pos = 10'h010;
       #10000000;

diff --git a/fpga/forcefader.srcs/sources_1/new/forceconverter.v b/fpga/forcefader.srcs/sources_1/new/forceconverter.v
index e8402d1b4bc5d1a784c86060566faf431067ebfb..4320483fa9bf49261ae6cfe8c50921aa88bf5b42 100644 (file)
--- a/fpga/forcefader.srcs/sources_1/new/forceconverter.v
+++ b/fpga/forcefader.srcs/sources_1/new/forceconverter.v
@@ -1,7 +1,7 @@
 module forceconverter(
   input sysclk,
   input signed [16:0] input_forcevalue,
 module forceconverter(
   input sysclk,
   input signed [16:0] input_forcevalue,

-  output output_direction,
+  output reg output_direction = 0,

   output reg output_pwm = 0,
   output output_overflow
 );
   output reg output_pwm = 0,
   output output_overflow
 );


@@ -9,31 +9,32 @@ module forceconverter(
   wire [15:0]absforce;
   assign absforce = input_forcevalue < 0 ? - input_forcevalue : input_forcevalue;
   
   wire [15:0]absforce;
   assign absforce = input_forcevalue < 0 ? - input_forcevalue : input_forcevalue;
   

-  assign output_direction = input_forcevalue[16];

   assign output_overflow = absforce > 12'hfff;
   
   assign output_overflow = absforce > 12'hfff;
   

-  reg [3:0] slowclkcounter = 0;
+  reg [4:0] slowclkcounter = 0;

   always @(posedge sysclk) begin
     slowclkcounter <= slowclkcounter + 1;
   end
 
   // 2.94KHz
   wire prescale;
   always @(posedge sysclk) begin
     slowclkcounter <= slowclkcounter + 1;
   end
 
   // 2.94KHz
   wire prescale;

-  assign prescale = slowclkcounter[3];
+  assign prescale = slowclkcounter[0];

   reg [7:0] currentamplitude = 0;
   reg [7:0] forcecnt = 0;
   always @(posedge prescale) begin
     forcecnt <= forcecnt + 1;
     if (forcecnt == 0) begin
   reg [7:0] currentamplitude = 0;
   reg [7:0] forcecnt = 0;
   always @(posedge prescale) begin
     forcecnt <= forcecnt + 1;
     if (forcecnt == 0) begin

-      output_pwm <= ~output_pwm;
+      output_pwm <= 1;//~output_pwm;

       if (output_overflow == 0)
       if (output_overflow == 0)

-        currentamplitude <= absforce[11:3];
+        currentamplitude <= absforce[11:4];

       else
         currentamplitude <= 8'hff;
     end
       else
         currentamplitude <= 8'hff;
     end

-    else if (forcecnt == currentamplitude) begin
-      output_pwm <= ~output_pwm;
+    if (forcecnt == currentamplitude) begin
+      output_pwm <= 0;//~output_pwm;

     end
   end
     end
   end

+  
+  always @(negedge output_pwm) output_direction <= input_forcevalue[16];

 
 endmodule
 
 endmodule

diff --git a/fpga/forcefader.v b/fpga/forcefader.v
index b5cbb8846c45ae49606170dd7a39a76e111c1e8c..a3bdf81cec72b8104400a55a3aca1056d7dc0946 100644 (file)
--- a/fpga/forcefader.v
+++ b/fpga/forcefader.v
@@ -1,6 +1,6 @@
 module forcefader (
   input sysclk, //12MHZ
 module forcefader (
   input sysclk, //12MHZ

-  input input_touch,
+  //input input_touch,

   output en,
   output dir,
   output overflow,
   output en,
   output dir,
   output overflow,


@@ -48,7 +48,7 @@ module forcefader (
   spring spring_instance(
     .position(input_pos),
     .endposition(10'b0111111111),
   spring spring_instance(
     .position(input_pos),
     .endposition(10'b0111111111),

-    .stiffness(8'b00000011),
+    .stiffness(8'b00001111),

     .outputforce(outputforce)
   );
 
     .outputforce(outputforce)
   );
 

diff --git a/fpga/forcefader.xpr b/fpga/forcefader.xpr
index 458526f71596c325e23344a6732d419d3eac279a..5d13f90d4baf397c682d529e59c8588afadfea9b 100644 (file)
--- a/fpga/forcefader.xpr
+++ b/fpga/forcefader.xpr
@@ -32,7 +32,7 @@
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSABoardId" Val="cmod_a7-35t"/>
     <Option Name="DSANumComputeUnits" Val="60"/>
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSABoardId" Val="cmod_a7-35t"/>
     <Option Name="DSANumComputeUnits" Val="60"/>

-    <Option Name="WTXSimLaunchSim" Val="92"/>
+    <Option Name="WTXSimLaunchSim" Val="94"/>

     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>


@@ -69,7 +69,6 @@
       </File>
       <File Path="$PSRCDIR/sources_1/new/spring.v">
         <FileInfo>
       </File>
       <File Path="$PSRCDIR/sources_1/new/spring.v">
         <FileInfo>

-          <Attr Name="AutoDisabled" Val="1"/>

           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>


@@ -77,7 +76,6 @@
       </File>
       <File Path="$PPRDIR/forcefader.v">
         <FileInfo>
       </File>
       <File Path="$PPRDIR/forcefader.v">
         <FileInfo>

-          <Attr Name="UserDisabled" Val="1"/>

           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>


@@ -85,7 +83,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>

-        <Option Name="TopModule" Val="forceconverter"/>
+        <Option Name="TopModule" Val="forcefader"/>

         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>


@@ -129,7 +127,6 @@
     <FileSet Name="adc" Type="BlockSrcs" RelSrcDir="$PSRCDIR/adc">
       <File Path="$PSRCDIR/sources_1/ip/adc/adc.xci">
         <FileInfo>
     <FileSet Name="adc" Type="BlockSrcs" RelSrcDir="$PSRCDIR/adc">
       <File Path="$PSRCDIR/sources_1/ip/adc/adc.xci">
         <FileInfo>

-          <Attr Name="AutoDisabled" Val="1"/>

           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>